CN102790033B - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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CN102790033B
CN102790033B CN201110176438.1A CN201110176438A CN102790033B CN 102790033 B CN102790033 B CN 102790033B CN 201110176438 A CN201110176438 A CN 201110176438A CN 102790033 B CN102790033 B CN 102790033B
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CN102790033A (zh
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孙世豪
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Subtron Technology Co Ltd
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Abstract

本发明公开一种封装结构及其制作方法。该封装结构的制作方法包括提供一金属基材。金属基材具有第一表面，且第一表面上已形成有第一种子层。形成一图案化绝缘层于第一种子层上。图案化绝缘层暴露出部分第一种子层。形成一图案化线路层于图案化绝缘层所暴露出的部分第一种子层上。图案化线路层覆盖部分图案化绝缘层。进行一芯片接合制作工艺，以电连接一芯片至图案化线路层上。形成一封装胶体，以包覆芯片与图案化线路层，且覆盖部分图案化绝缘层。移除金属基材与第一种子层，以暴露出图案化绝缘层的一底面与图案化线路层的一下表面。形成多个焊球于图案化线路层的下表面上。

Description

封装结构及其制作方法
技术领域
本发明涉及一种封装结构及其制作方法，且特别是涉及一种具有较薄厚度的封装结构及其制作方法。
背景技术
芯片封装的目的在于保护裸露的芯片、降低芯片接点的密度及提供芯片良好的散热。常见的封装方法是芯片通过打线接合(wire bonding)或覆晶接合(flip chip bonding)等方式而安装至一封装载板，以使芯片上的接点可电连接至封装载板。因此，芯片的接点分布可通过封装载板重新配置，以符合下一层级的外部元件的接点分布。
一般来说，封装载板的制作通常是以核心(core)介电层作为蕊材，并利用全加成法(fully additive process)、半加成法(semi-additive process)、减成法(subtractive process)或其他方式，将图案化线路层与图案化介电层交错堆叠于核心介电层上。如此一来，核心介电层在封装载板的整体厚度上便会占着相当大的比例。因此，若无法有效地缩减核心介电层的厚度，势必会使封装结构于厚度缩减上产生极大的障碍。
发明内容
本发明的目的在于提供一种封装结构，具有较薄的封装厚度。
本发明的再一目的在于提供一种封装结构的制作方法，用以制作上述的封装结构。
为了实现上述目的，本发明提出一种封装结构的制作方法。提供一金属基材。金属基材具有一第一表面，且第一表面上已形成有一第一种子层。形成一图案化绝缘层于第一种子层上，其中图案化绝缘层暴露出部分第一种子层。形成一图案化线路层于图案化绝缘层所暴露出的部分第一种子层上，其中图案化线路层覆盖部分图案化绝缘层。进行一芯片接合制作工艺，以电连接一芯片至图案化线路层上。形成一封装胶体，以包覆芯片与图案化线路层，且覆盖部分图案化绝缘层。移除金属基材与第一种子层，以暴露出图案化绝缘层的一底面与图案化线路层的一下表面。形成多个焊球于图案化线路层的下表面上。
在本发明的一实施例中，上述形成图案化线路层的步骤，包括：形成一第二种子层于图案化绝缘层上，其中第二种子层包覆图案化绝缘层；形成一图案化光致抗蚀剂层于部分第一种子层与部分第二种子层上以及金属基材相对于第一表面的第二表面上，其中图案化光致抗蚀剂层暴露出部分第一种子层与部分第二种子层；以图案化光致抗蚀剂层为一电镀罩幕，以电镀图案化线路层于图案化光致抗蚀剂层所暴露出的部分第一种子层与部分第二种子层上；以及移除图案化光致抗蚀剂层与部分第二种子层，以暴露出部分图案化绝缘层与金属基材的第二表面。
在本发明的一实施例中，上述的封装结构的制作方法，更包括：在移除图案化光致抗蚀剂层与部分第二种子层之前，形成一表面处理层于图案化线路层上。
在本发明的一实施例中，上述形成图案化线路层的步骤，包括：形成一金属层于第一种子层上，其中金属层覆盖图案化绝缘层与部分第一种子层；形成一图案化光致抗蚀剂层于金属层上，其中图案化光致抗蚀剂层暴露出部分金属层；以图案化光致抗蚀剂层为一蚀刻罩幕，移除部分金属层，以暴露出部分图案化绝缘层，而形成图案化线路层；以及移除图案化光致抗蚀剂层。
在本发明的一实施例中，上述封装结构的制作方法，更包括：在移除图案化光致抗蚀剂层之后，形成一表面处理层于图案化线路层上。
在本发明的一实施例中，上述芯片接合制作工艺包括一打线接合制作工艺或一覆晶接合制作工艺。
本发明提出一种封装结构，其包括一图案化绝缘层、一图案化线路层、多个焊球、一芯片以及一封装胶体。图案化绝缘层具有一底面。图案化线路层配置于图案化绝缘层上，且覆盖部分图案化绝缘层，其中图案化线路层的一下表面与图案化绝缘层的底面实质上齐平。焊球配置于图案化线路层的下表面上。芯片电连接至图案化线路层。封装胶体包覆芯片及图案化线路层，且覆盖部分图案化绝缘层。
在本发明的一实施例中，上述的封装结构更包括一表面处理层，配置于图案化线路层上。
在本发明的一实施例中，上述的表面处理层包括一镍层、一金层、一银层或一镍钯金层。
在本发明的一实施例中，上述的芯片通过打线接合或覆晶接合技术与图案化线路层电连接。
基于上述，由于本发明的封装结构具有图案化绝缘层，因此当焊球形成于图案化线路层的下表面时，图案化绝缘层可避免相邻的焊球产生短路的现象。如此一来，本发明的封装结构可具有较佳的电性效能。再者，由于本发明是先以金属基材做为载体，通过电镀法(plating)或减成法来(subtractiveprocess)形成图案化线路层，且待芯片进行完封装后，再将金属基材及种子层移除。因此，相比较于现有具有核心介电层的封装结构而言，本发明的封装结构因可具有较薄的封装厚度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1E为本发明的一实施例的一种封装结构的制作方法的剖面示意图；
图2A至图2B为本发明的另一实施例的一种封装结构的制作方法的局部步骤的剖面示意图。
主要元件符号说明
100：封装结构
110：金属基材
112：第一表面
114：第二表面
120：第一种子层
125：第二种子层
130：图案化绝缘层
132：底面
140：图案化线路层
140a：金属层
142：下表面
150：表面处理层
160：芯片
170：封装胶体
180：焊球
192、194：图案化光致抗蚀剂层
196：焊线
具体实施方式
图1A至图1E为本发明的一实施例的一种封装结构的制作方法的剖面示意图。请先参考图1A，依照本实施例的封装结构的制作方法，首先，提供一金属基材110。详细来说，金属基材110具有彼此相对的一第一表面112与一第二表面114，其中第一表面112上已形成有一第一种子层120。在本实施例中，第一种子层120的材质例如是铜，而形成第一种子层120的方法例如是电镀法。
接着，请参考图1B，形成一图案化绝缘层130于第一种子层120上，其中图案化绝缘层130暴露出部分第一种子层120。在本实施例中，形成图案化绝缘层130的方法例如是网版印刷法或曝光显影法。
接着，请参考图1C，形成一第二种子层125于图案化绝缘层130上，其中第二种子层125包覆图案化绝缘层130，且第二种子层125的材质例如是铜。接着，形成一图案化光致抗蚀剂层192于部分第一种子层120与部分第二种子层125上以及金属基材110的第二表面114上，其中图案化光致抗蚀剂层192暴露出部分第一种子层120与部分第二种子层125。
接着，请同时参考图1C与图1D，以图案化光致抗蚀剂层192为一电镀罩幕，以电镀一图案化线路层140于图案化光致抗蚀剂层192所暴露出的部分第一种子层120与部分第二种子层125上。也就是说，本实施例是通过电镀(plating)的方式来形成图案化线路层。特别是，本实施例可通过图案化光致抗蚀剂层192来控制图案化线路层140的线宽与厚度。在此，图案化线路层140的线宽例如是小于30微米，因此相较于一般线路层的线宽而言，本实施例的图案化线路层140可视为一微细线路层。
接着，请再参考图1D，并形成一表面处理层150于图案化线路层140上，其中形成表面处理层150的方法例如是再以图案化光致抗蚀剂层192(请参考图1C)为电镀罩幕，以电镀表面处理层150于图案化线路层140上。表面处理层150例如是一镍层、一金层、一银层、一镍钯金层或其他适当的材料层，在此并不加以限制。接着，移除图案化光致抗蚀剂层192以及位于图案化光致抗蚀剂层192下方的部分第二种子层125，以暴露出部分图案化绝缘层130以及与金属基材110的第二表面114。此时，图案化线路层140配置于图案化绝缘层130所暴露出的部分第一种子层120上，且局步覆盖部分图案化绝缘层130。
之后，请参考图1E，进行一芯片接合制作工艺，以电连接一芯片160至位于图案化线路层140上方的表面处理层150，其中本实施例的芯片接合制作工艺例如是一打线接合制作工艺。在本实施例中，芯片160可通过多条焊线196而与图案化线路层140电连接，其中芯片160例如是一发光二极管芯片、一激光二极管芯片、一绘图芯片、一记忆体芯片、一半导体芯片等单一芯片或是一芯片模块。
值得一提的是，本发明并不限定芯片160与图案化线路层140的接合形态，虽然此处所提及的芯片160具体化是通过打线接合而电连接至图案化线路层140上方的表面处理层150上。不过，在其他实施例中，芯片160也可通过覆晶接合的方式而电连接至位于图案化线路层140上方的表面处理层150上。由此可知，上述的芯片160与图案化线路层140的接合形态仅为举例说明之用，并非用以限定本发明。
接着，请再参考图1E，形成一封装胶体170，以包覆芯片160、表面处理层150与图案化线路层140，且覆盖部分图案化绝缘层130。之后，移除金属基材110与第一种子层120，以暴露出图案化绝缘层130的一底面132与图案化线路层140的一下表面142。此时，图案化绝缘层130的底面132与图案化线路层140的下表面142实质上齐平。最后，并形成多个焊球180于图案化线路层140的下表面142上。至此，以完成封装结构100的制作。
再结构上，请再参考图1E，封装结构100包括图案化绝缘层130、图案化线路层140、表面处理层150、芯片160、封装胶体170、这些焊球180与这些焊线196。图案化绝缘层130具有底面132。图案化线路层140配置于图案化绝缘层130上，且覆盖部分图案化绝缘层130，其中图案化线路层140的下表面142与图案化绝缘层130的底面132实质上齐平。表面处理层150配置于图案化线路层140上，其中表面处理层150例如是一镍层、一金层、一银层或一镍钯金层。芯片160通过这些焊线196电连接至图案化线路层140。封装胶体170包覆芯片160、表面处理层150及图案化线路层140，且覆盖部分图案化绝缘层130。这些焊球180配置于图案化线路层140的下表面142上。
由于本实施例的封装结构100具有图案化绝缘层130，因此当这些焊球180形成于图案化线路层140的下表面142时，图案化绝缘层130可避免相邻的这些焊球180因回焊而产生短路的现象。如此一来，本实施例的封装结构100可具有较佳的电性效能与较佳的结构可靠度。再者，由于本实施例的封装结构100的制作方法是进行完芯片160的封装后，意即形成封装胶体170，再移除金属基材110及覆盖金属基材110上的第一种子层120。如此一来，相比较于现有具有核心介电层的封装结构而言，本实施例的封装结构100因不具有金属基材110，因而可具有较薄的封装厚度。此外，由于本实施例可通过图案化光致抗蚀剂层192来控制图案化线路层140的线宽与厚度，因此可制作出所需的微细线路层。
在此必说明明的是，虽然在本实施例中所提及的形成图案化线路层140的方式为电镀法，但在其他实施例中，也可采用减成法来(subtractive process)来形成图案化线路层140。图2A至图2B为本发明的另一实施例的一种封装结构的制作方法的局部步骤的剖面示意图。详细来说，在图1B的步骤后，即形成图案化绝缘层130于第一种子层120上之后，请参考图2A，形成一金属层140a于第一种子层120上，其中金属层140a覆盖图案化绝缘层130与部分第一种子层120。接着，并形成一图案化光致抗蚀剂层194于金属层140a上，其中图案化光致抗蚀剂层194暴露出部分金属层140a。之后，请同时参考图2A与图2B，以图案化光致抗蚀剂层194为一蚀刻罩幕，移除部分金属层140a，以暴露出部分图案化绝缘层130，而形成图案化线路层140。最后，移除图案化光致抗蚀剂层194，并形成表面处理层150于图案化线路层140上，而后，再接续图1E的步骤而完成封装结构100的制作。
综上所述，由于本发明的封装结构具有图案化绝缘层，因此当焊球形成于图案化线路层的下表面时，图案化绝缘层可避免相邻的焊球因回焊而产生短路的现象。如此一来，本发明的封装结构可具有较佳的电性效能与较佳的结构可靠度。再者，由于本发明是先以金属基材做为载体，通过电镀法(plating)或减成法来(subtractive process)形成图案化线路层，且待芯片进行完封装后，再将金属基材及种子层移除。因此，相较于现有具有核心介电层的封装结构而言，本发明的封装结构因可具有较薄的封装厚度。此外，本发明可通过图案化光致抗蚀剂层来控制图案化线路层的线宽与厚度，以可制作出所需的微细线路层。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (9)

1.一种封装结构的制作方法，包括：
提供一金属基材，该金属基材具有第一表面，且该第一表面上已形成有一第一种子层；
形成一图案化绝缘层于该第一种子层上，其中该图案化绝缘层暴露出部分该第一种子层；
形成一图案化线路层于该图案化绝缘层所暴露出的部分该第一种子层上，其中该图案化线路层覆盖部分该图案化绝缘层，而形成该图案化线路层的步骤包括：
形成一第二种子层于该图案化绝缘层上，其中该第二种子层包覆该图案化绝缘层；
形成一图案化光致抗蚀剂层于部分该第一种子层与部分该第二种子层上以及该金属基材相对于该第一表面的第二表面上，其中该图案化光致抗蚀剂层暴露出部分该第一种子层与部分该第二种子层；
以该图案化光致抗蚀剂层为一电镀罩幕，以电镀该图案化线路层于该图案化光致抗蚀剂层所暴露出的部分该第一种子层与部分该第二种子层上；以及
移除该图案化光致抗蚀剂层与部分该第二种子层，以暴露出部分该图案化绝缘层与该金属基材的该第二表面；
进行一芯片接合制作工艺，以电连接一芯片至该图案化线路层上；
形成一封装胶体，以包覆该芯片与该图案化线路层，且覆盖部分该图案化绝缘层；
移除该金属基材与该第一种子层，以暴露出该图案化绝缘层的底面与该图案化线路层的下表面；以及
形成多个焊球于该图案化线路层的该下表面上。
2.如权利要求1所述的封装结构的制作方法，还包括：
于移除该图案化光致抗蚀剂层与部分该第二种子层之前，形成一表面处理层于该图案化线路层上。
3.如权利要求1所述的封装结构的制作方法，其中形成该图案化线路层的步骤，包括：
形成一金属层于该第一种子层上，其中该金属层覆盖该图案化绝缘层与部分该第一种子层；
形成一图案化光致抗蚀剂层于该金属层上，其中该图案化光致抗蚀剂层暴露出部分该金属层；
以该图案化光致抗蚀剂层为一蚀刻罩幕，移除部分该金属层，以暴露出部分该图案化绝缘层，而形成该图案化线路层；以及
移除该图案化光致抗蚀剂层。
4.如权利要求3所述的封装结构的制作方法，还包括：
于移除该图案化光致抗蚀剂层之后，形成一表面处理层于该图案化线路层上。
5.如权利要求1所述的封装结构的制作方法，其中该芯片接合制作工艺包括打线接合制作工艺或覆晶接合制作工艺。
6.一种以权利要求1所述的封装结构的制作方法所制作的封装结构，包括：
图案化绝缘层，具有底面；
图案化线路层，配置于该图案化绝缘层上，且覆盖部分该图案化绝缘层，其中该图案化线路层的下表面与该图案化绝缘层的该底面实质上齐平；
多个焊球，配置于该图案化线路层的该下表面上；
芯片，电连接至该图案化线路层；以及
封装胶体，包覆该芯片及该图案化线路层，且覆盖部分该图案化绝缘层。
7.如权利要求6所述的封装结构，还包括表面处理层，配置于该图案化线路层上。
8.如权利要求7所述的封装结构，其中该表面处理层包括镍层、金层、银层或镍钯金层。
9.如权利要求6所述的封装结构，其中该芯片通过打线接合或覆晶接合技术与该图案化线路层电连接。
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