TW201411749A - 在載體上形成用於過渡階段測試的積層的互連結構之半導體裝置和方法 - Google Patents

在載體上形成用於過渡階段測試的積層的互連結構之半導體裝置和方法 Download PDF

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TW201411749A
TW201411749A TW102122926A TW102122926A TW201411749A TW 201411749 A TW201411749 A TW 201411749A TW 102122926 A TW102122926 A TW 102122926A TW 102122926 A TW102122926 A TW 102122926A TW 201411749 A TW201411749 A TW 201411749A
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interconnect structure
layer
semiconductor
conductive layer
conductive
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TW102122926A
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TWI562250B (en
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Yaojian Lin
Kang Chen
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Stats Chippac Ltd
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Abstract

一種半導體裝置係具有一形成在載體之上的第一互連結構。一半導體晶粒係在測試該第一互連結構已知為良好的之後被設置在該第一互連結構之上。該半導體晶粒是一已知為良好的晶粒。一例如是一凸塊或柱形凸塊之垂直的互連結構係形成在該第一互連結構之上。一離散的半導體裝置係被設置在該第一互連結構或是該第二互連結構之上。一囊封體係沉積在該半導體晶粒、第一互連結構以及垂直的互連結構之上。該囊封體的一部分係被移除以露出該垂直的互連結構。一第二互連結構係形成在該囊封體之上並且電連接至該垂直的互連結構。該第一互連結構或是該第二互連結構係包含一具有一內嵌的玻璃布、玻璃纖維布、填充物或是纖維之絕緣層。

Description

在載體上形成用於過渡階段測試的積層的互連結構之半導體裝置和方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種在載體上形成用於過渡階段測試的積層的互連結構之半導體裝置和方法。
優先權主張
本申請案係主張2012年9月14日申請的美國臨時申請案號61/701,366的利益，該申請案係被納入在此作為參考。
相關申請案交互參照
本申請案係相關於美國專利申請案序號(待決定)的代理人文件號2515.0408之名稱為“在扇出晶圓級晶片尺寸封裝中形成雙側的互連結構的半導體裝置和方法”。本申請案係進一步相關於美國專利申請案序號(待決定)的代理人文件號2515.0427之名稱為“在扇出晶圓級晶片尺寸封裝中形成雙側的互連結構的半導體裝置和方法”。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電氣構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電氣構 件，例如，發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百到數百萬個電氣構件。集積的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能，例如，信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的結構係容許其導電度能夠藉由一電場或基極電流的施加或是透過摻雜的製程來加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電氣功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體裝置能夠執行高速的計算及其它有用的功能。
半導體裝置一般是利用兩個複雜的製程，亦即，前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每個半導體晶粒通常是相同 的，並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉到從完成的晶圓單粒化(singulating)個別的半導體晶粒並且封裝該晶粒以提供結構的支撐以及環境的隔離。如同在此所用的術語“半導體晶粒”係指該字的單數與複數形兩者，並且於是可以指稱單一半導體裝置及多個半導體裝置兩者。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。此外，較小的半導體裝置具有一較小的覆蓋區，此係較小的終端產品所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之半導體晶粒的前端製程中的改良來達成。後端製程可以藉由在電互連及囊封體上的改良來產生具有較小覆蓋區的半導體裝置封裝。
一半導體晶粒可以在安裝於一例如是扇出晶圓級晶片尺寸封裝(Fo-WLCSP)的半導體封裝中之前先被測試是否已知為良好的晶粒(KGD)。該半導體封裝仍然可能會由於在該積層的(build-up)互連結構中的缺陷而失效，此係造成該KGD的損失。一具有細微的線間隔以及多層結構之大於10乘10毫米(mm)的半導體封裝尺寸是特別容易受到該積層的互連結構中的缺陷影響。越大尺寸的Fo-WLCSP亦會遭受到翹曲的缺陷。
對於在安裝一KGD於一扇出晶圓級晶片尺寸封裝(Fo-WLCSP)中之前先測試該積層的互連結構存在著需求。於是，在一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一載體，在該載體之上形成一第一互連結構，測試該第一互連結構，在測試 該第一互連結構之後設置一半導體晶粒在該第一互連結構之上，在該第一互連結構之上形成一垂直的互連結構，在該半導體晶粒、第一互連結構以及垂直的互連結構之上沉積一囊封體，以及在該囊封體之上形成一第二互連結構，並且該第二互連結構係電耦接至該垂直的互連結構。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：形成一第一已知為良好的互連結構，在該第一已知為良好的互連結構之上設置一半導體晶粒，在該半導體晶粒以及第一已知為良好的互連結構之上沉積一囊封體，以及在該囊封體之上形成一第二互連結構。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一第一互連結構，在該第一互連結構之上形成一垂直的互連結構，提供一第二互連結構，在該第二互連結構之上設置該第一互連結構，在該第一互連結構或是第二互連結構之上設置一半導體晶粒，以及在該半導體晶粒之上沉積一囊封體。
在另一實施例中，本發明是一種半導體裝置，其係包括一第一已知為良好的第一互連結構以及設置在該第一已知為良好的互連結構之上的半導體晶粒。一囊封體係沉積在該半導體晶粒以及第一已知為良好的互連結構之上。一第二互連結構係形成在該囊封體之上。
50‧‧‧電子裝置
52‧‧‧印刷電路板(PCB)
54‧‧‧信號線路
56‧‧‧接合線封裝
58‧‧‧覆晶
60‧‧‧球格陣列(BGA)
62‧‧‧凸塊晶片載體(BCC)
64‧‧‧雙排型封裝(DIP)
66‧‧‧平台柵格陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四邊扁平無引腳封裝(QFN)
72‧‧‧四邊扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導線
82‧‧‧接合線
84‧‧‧囊封體
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧底膠填充(環氧樹脂黏著材料)
94‧‧‧接合線
96、98‧‧‧接觸墊
100‧‧‧模製化合物(囊封體)
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧中間載體
108‧‧‧主動區
110、112‧‧‧凸塊
114‧‧‧信號線
116‧‧‧模製化合物(囊封體)
120‧‧‧晶圓
122‧‧‧主體基板材料
124‧‧‧半導體晶粒(構件)
126‧‧‧切割道
128‧‧‧背表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣(保護)層
136‧‧‧絕緣(保護)層
138‧‧‧球(凸塊)
139‧‧‧鋸刀(雷射切割工具)
140‧‧‧載體(臨時的基板)
142‧‧‧介面層(雙面帶)
144‧‧‧絕緣(保護)層
146‧‧‧導電層
148‧‧‧絕緣(保護)層
149‧‧‧雷射
150‧‧‧導電層(重新分配層(RDL))
152‧‧‧絕緣(保護)層
154‧‧‧雷射
156‧‧‧積層的互連結構
158‧‧‧底膠填充材料
160‧‧‧離散的半導體裝置
162‧‧‧導電膏
1643D‧‧‧互連結構
166‧‧‧內部的導電合金凸塊
168‧‧‧保護層
170‧‧‧囊封體(模製化合物)
172‧‧‧研磨機
178‧‧‧絕緣(保護)層
180‧‧‧導電層(RDL)
182‧‧‧絕緣(保護)層
184‧‧‧雷射
186‧‧‧積層的互連結構
188‧‧‧球(凸塊)
190‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
200‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
202‧‧‧柱形凸塊
204‧‧‧半導體晶粒
208‧‧‧背表面
210‧‧‧主動表面
212‧‧‧導電層
214‧‧‧絕緣(保護)層
216‧‧‧絕緣(保護)層
220‧‧‧晶粒附接膜(DAF)
222‧‧‧離散的半導體裝置
224‧‧‧導電膏
226‧‧‧3D互連結構
228‧‧‧內部的導電的合金凸塊
230‧‧‧保護層
234‧‧‧囊封體(模製化合物)
236‧‧‧研磨機
240‧‧‧絕緣(保護)層
242‧‧‧導電層(RDL)
244‧‧‧絕緣(保護)層
246‧‧‧雷射
248‧‧‧積層的互連結構
250‧‧‧球(凸塊)
252‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
260‧‧‧積層的互連結構
262‧‧‧核心積層基板
263‧‧‧導電的貫孔
264‧‧‧導電層(RDL)
266‧‧‧絕緣(保護)層
270‧‧‧離散的半導體裝置
272‧‧‧導電膏
274‧‧‧球(凸塊)
276‧‧‧導電層(RDL)
278‧‧‧絕緣(保護)層
280‧‧‧囊封體(模製化合物)
282‧‧‧雷射
284‧‧‧球(凸塊)
286‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
290‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
300‧‧‧扇出晶圓級晶片尺寸封裝(Fo-WLCSP)
301‧‧‧載體(臨時的基板)
302‧‧‧積層的互連結構
304‧‧‧絕緣層
306‧‧‧導電層
308‧‧‧絕緣層
310‧‧‧導電層
312‧‧‧絕緣層
314‧‧‧載體(臨時的基板)
316‧‧‧離散的半導體裝置
318‧‧‧導電膏
320‧‧‧球(凸塊)
322‧‧‧囊封體(模製化合物)
324‧‧‧球(凸塊)
330‧‧‧半導體晶粒
338‧‧‧背表面
340‧‧‧主動表面
346‧‧‧凸塊
348‧‧‧接觸墊
350‧‧‧PoP
圖1係描繪一具有不同類型的封裝安裝到其表面的印刷電路板(PCB)；圖2a-2c係描繪安裝到該PCB之代表性的半導體封裝的進一步細節； 圖3a-3c係描繪一具有複數個藉由切割道分開的半導體晶粒之半導體晶圓；圖4a-4i係描繪一在載體之上形成用於在過渡階段的測試之頂端及底部積層的互連結構的製程；圖5係描繪一Fo-WLCSP，其中一柱形凸塊係設置在該頂端及底部積層的互連結構之間；圖6a-6f係描繪另一在載體之上形成用於在過渡階段的測試之頂端及底部積層的互連結構的製程；圖7a-7d係描繪一第一積層的互連結構安裝到一第二積層的互連結構；圖8係描繪一具有頂端及底部積層的互連結構以及一安裝到該頂端積層的互連結構的半導體晶粒之Fo-WLCSP；圖9a-9b係描繪另一類型的第一積層的互連結構安裝到一第二積層的互連結構；以及圖10係描繪包含該Fo-WLCSP的PoP，其中凸塊係設置在該頂端及底部積層的互連結構之間。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由所附的申請專利範圍及其由以下的揭露內容及圖式所支持的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每個晶粒係包含電連接以形成功能電路的主動及被動電氣構件。例如是電晶體及二極體的主動電氣構件係具有控制電流的流動之能力。例如是電容器、電感器及電阻器的被動電氣構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係修改主動元件中的半導體材料的導電度，其係藉由響應於一電場或基極電流來動態地改變該半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該技術部分是由被沉積的材料類型來決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒並且接著為了結構的支撐及環境的隔離來封裝該半導體晶粒。為了單粒化該半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單 粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用焊料凸塊、柱形凸塊、導電膏、或是接合線來做成。一囊封體或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電氣隔離。該完成的封裝係接著被插入一電氣系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1係描繪具有複數個安裝於其表面上之半導體封裝的晶片載體基板或PCB 52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖1中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡或其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其它半導體晶粒或電氣構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖1中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電性互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成 在PCB 52的一表面之上或是在層內。信號線路54係提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給該些半導體封裝的每一個。
在某些實施例中，一半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電性地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電性地安裝到PCB上。
為了說明之目的，包含接合線封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第二層級的封裝類型的任意組合來配置的半導體封裝的任何組合及其它電子構件都可連接至PCB 52。在某些實施例中，電子裝置50係包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低，從而降低消費者成本。
圖2a-2c係展示範例的半導體封裝。圖2a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電 路的主動區，該些類比或數位電路係被實施為形成在晶粒內之主動元件、被動元件、導電層及介電層並且根據該晶粒的電設計而電互連。例如，該電路可包含形成在半導體晶粒74的主動區內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著材料而被安裝到一中間載體78。該封裝主體係包含一種例如是聚合物或陶瓷的絕緣囊封體。導線80及接合線82係在半導體晶粒74及PCB 52之間提供電互連。囊封體84係為了環境保護而沉積在該封裝之上，以防止濕氣及微粒進入該封裝且污染晶粒74或接合線82。
圖2b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安裝在載體90之上。接合線94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或囊封體100係沉積在半導體晶粒88及接合線94之上，以提供實體支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖2c中，半導體晶粒58係以覆晶型第一層級的封裝面向下安裝到中間載體106。半導體晶粒58的主動區108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動元 件、被動元件、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區108內之其它電路元件。半導體晶粒58係透過凸塊110電性及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝而利用凸塊112以電性及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112而電連接至PCB 52中的導電信號線路54。一種模製化合物或囊封體116係沉積在半導體晶粒58及載體106之上以提供實體支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動元件到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳遞距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
圖3a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或矽碳化物的主體基板材料122以供結構支撐的半導體晶圓120。如上所述，複數個半導體晶粒或構件124係形成在晶圓120上，且藉由非主動的晶粒間的晶圓區域或切割道126加以分開。切割道126係提供切割區域以單粒化半導體晶圓120成為個別的半導體晶粒124。
圖3b係展示半導體晶圓120的一部份的橫截面圖。每個半導體晶粒124係具有一背表面128以及包含類比或數位電路的主動表面130，該些類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能來電互連的主動元件、被動元件、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在主動表面130內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶 體或是其它信號處理電路。半導體晶粒124亦可包含整合被動裝置(IPD)，例如電感器、電容器及電阻器，以供RF信號處理使用。在一實施例中，半導體晶粒124是一覆晶型裝置。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在主動表面130之上。導電層132可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層132係運作為接觸墊，該些接觸墊係電連接至主動表面130上的電路。如同圖3b中所示，導電層132可形成為接觸墊，該些接觸墊係和半導體晶粒124的邊緣相隔一第一距離而並排地加以設置。或者是，導電層132可形成為接觸墊，該些接觸墊是以多個列加以偏置，使得一第一列的接觸墊係和該晶粒的邊緣相隔一第一距離地加以設置，並且一和該第一列交錯的第二列的接觸墊係和該晶粒的邊緣相隔一第二距離地加以設置。
一絕緣或保護層134係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或是熱氧化而形成在主動表面130及導電層132之上。該絕緣層134係包含一或多個層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)或是其它具有類似絕緣及結構的性質之材料。絕緣層134的一部分係藉由雷射直接剝蝕(LDA)或是一蝕刻製程，透過一圖案化的光阻層來加以移除以露出導電層132。
一絕緣或保護層136係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結或是熱氧化來加以形成在導電層132及絕緣層134之上。該絕緣層136係包含一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3，或是其它具有類似絕緣及結構的性質之材料。絕緣層136的一部分係藉由LDA 或是蝕刻製程，透過一圖案化的光阻層來加以移除以露出導電層132。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程以沉積在導電層132之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、鉛(Pb)、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層132。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊以形成球或凸塊138。在某些應用中，凸塊138係被回焊第二次以改善至導電層132的電性接觸。在一實施例中，凸塊138係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層132。凸塊138係代表一種可被形成在導電層132之上的互連結構的類型。該互連結構亦可以使用柱形凸塊、微凸塊或是其它電互連。
在圖3c中，半導體晶圓120係利用一鋸刀或是雷射切割工具139，透過切割道126而被單粒化成為個別的半導體晶粒124。
圖4a-4i係相關於圖1及2a-2c來描繪一在載體之上形成用於在過渡階段的測試之頂端及底部積層的互連結構的製程。圖4a係展示包含例如是矽、聚合物、鈹氧化物、玻璃或是其它適當的低成本剛性材料之犧牲或是可重複使用的基底材料以用於結構的支撐之載體或是臨時的基板140的一部分的一橫截面圖。一介面層或是雙面帶142係形成在載體140之上以作為一暫時的黏著接合膜、蝕刻停止層或是熱釋放層。載體140可以部分地加以雷射開槽，以用於在後續的積層的互連結構及封裝製程中之應力釋放。載體140係具有充分的尺寸以在積層的互連形成期間容納多個半 導體晶粒。
一絕緣或保護層144係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在載體140的介面層142之上。該絕緣層144係包含一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、鉿氧化物(HfO2)、苯環丁烯(BCB)、聚醯亞胺(PI)、聚苯並噁唑(PBO)或是其它具有類似結構及介電性質之材料。在一實施例中，絕緣層144係為了強化的彎曲強度而包含一玻璃布、玻璃纖維布、填充物或是纖維，例如E-玻璃布、T-玻璃布、Al2O3或是二氧化矽填充物。
一導電層146係利用一例如是濺鍍、電解的電鍍、無電的電鍍或是Cu箔疊層的圖案化及金屬沉積製程而形成在絕緣層144之上。導電層146可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。或者是，在一選配的Cu層形成在絕緣層144之下，絕緣層144以及導電層146係一起提供一積層在載體140上的RCC帶或是預浸材(pregreg)片。在圖案化之前，導電層146係利用選配的蝕刻薄化的製程而被圖案化。
一絕緣或保護層148係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化而形成在絕緣層144及導電層146之上。該絕緣層148係包含一或多個層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。絕緣層148的一部分係藉由利用雷射149的LDA來加以移除，以露出導電層146。或者是，絕緣層148的一部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層146。在一實施例中，為了強化的彎曲強度，絕緣層148係包含一玻璃布、玻璃纖維布、填 充物或是纖維，例如E-玻璃布、T-玻璃布、Al2O3或是二氧化矽填充物。
在圖4b中，一導電層或重新分配層(RDL)150係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在導電層146及絕緣層148之上。導電層150可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層150的一部分係電連接至導電層146。根據半導體晶粒124的設計及功能，導電層150的其它部分可以是電性共通或是電性隔離的。
一絕緣或保護層152係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在絕緣層148及導電層150之上。該絕緣層152係包含一或多個層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。絕緣層152的一部分係藉由利用雷射154的LDA來加以移除，以露出導電層150。或者是，絕緣層152的一部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層150。
絕緣層144、148及152以及導電層146及150的組合係構成一積層的互連結構156。該積層的互連結構156係在晶圓層級藉由在本過渡階段，亦即在安裝半導體晶粒124之前的開路/短路探針或是自動示波器的檢查來加以檢查及測試是否已知為良好的。漏電流可在一取樣位置處加以測試。
在圖4c中，在凸塊138被定向朝向該積層的互連結構下，來自圖3c的半導體晶粒124係利用例如是一拾放的操作而被安裝到積層的互連結構156。凸塊138係冶金且電耦接至導電層150。圖4d係展示半導體 晶粒124安裝到積層的互連結構156以作為一重組晶圓。半導體晶粒124是一在安裝到積層的互連結構156之前已經被測試的KGD。一種例如是具有填充物的環氧樹脂之底膠填充材料158係沉積在半導體晶粒124以及積層的互連結構156之間。或者是，在該晶粒的單粒化之前，底膠填充可被施加作為在半導體晶粒124上的非導電膏(NCP)或是非導電膜(NCF)。離散的半導體裝置160亦利用導電膏162而冶金且電耦接至導電層150。離散的半導體裝置160可以是一電感器、電容器、電阻器、電晶體或是二極體。
一3D互連結構164係藉由利用選配的焊料膏的植球製程而形成在導電層150之上。該3D互連結構164係包含一例如是Cu或Al之內部的導電合金凸塊166、以及例如是焊料合金SAC305、Cu、聚合物或是塑膠之保護層168。或者是，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層150之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層150。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊。在某些應用中，該凸塊係被回焊第二次，以改善至導電層150的電性接觸。該些凸塊亦可以壓縮接合或是熱壓接合到導電層150。
在圖4e中，一種囊封體或是模製化合物170係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆、或是其它適當的施用器而沉積在半導體晶粒124、積層的互連結構156以及3D 互連結構164之上。囊封體170可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體170是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。
在圖4f中，囊封體170的一部分係在一利用研磨機172的研磨操作中被移除，以平坦化該表面且降低該囊封體的厚度，並且露出內部的導電凸塊166。一化學蝕刻或CMP製程亦可被利用，以消除產生自該研磨操作及平坦化囊封體170的機械性損壞。圖4g係展示在該研磨操作後的組件。在該研磨操作之後，半導體晶粒124的背表面128係維持被囊封體170所覆蓋。或者是，囊封體170的一部分係藉由LDA或鑽孔來加以移除，以露出內部的導電凸塊166。
在圖4h中，一選配的絕緣或保護層178係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在囊封體170及3D互連結構164之上。該絕緣層178係包含一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、具有或是不具有填充物或纖維的聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。絕緣層178的一部分係藉由LDA或蝕刻製程透過一圖案化的光阻層來加以移除，以露出內部的導電凸塊166。
一導電層或RDL 180係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層178及內部的導電凸塊166之上。導電層180可以是一或多個層的Al、CU、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層180的一部分係電連接至內部的導電凸 塊166。根據半導體晶粒124的設計及功能，導電層180的其它部分可以是電性共通或是電性隔離的。
一絕緣或保護層182係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化而形成在絕緣層178及導電層180之上。該絕緣層182係包含一或多個層的SiO2、Si3N4、SiaN、Ta2O5、Al2O3、具有或是不具有填充物或纖維的聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。在一實施例中，為了強化的彎曲強度，絕緣層182係包含一內嵌的玻璃布、玻璃纖維布、填充物或是纖維，例如E-玻璃布、T-玻璃布、Al2O3或是二氧化矽填充物。絕緣層182的一部分係藉由利用雷射184的LDA來加以移除，以露出導電層180。或者是，絕緣層182的一部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層180。
絕緣層178及182以及導電層180的組合係構成一積層的互連結構186。該積層的互連結構186係形成在載體140之上，但是在一和積層的互連結構156不同的時間點，亦即，在沉積囊封體170之後。該積層的互連結構186係在一過渡階段，亦即在額外裝置的集積(見於圖10)之前先被檢查及測試是否已知為良好的。
在圖4i中，載體140及介面層142係藉由化學蝕刻、機械式剝離、化學機械平坦化(CMP)、機械式研磨、熱釋放、UV光、雷射掃描或是濕式剝除來加以移除，以露出絕緣層144。一背面研磨帶或是支撐載體可以在移除載體140之前先被施加至絕緣層182。絕緣層144的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層 146。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層146之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層146。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊188。在某些應用中，凸塊188係被回焊第二次，以改善至導電層146的電性接觸。在一實施例中，凸塊188係被形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該些凸塊亦可以壓縮接合或是熱壓接合到導電層146。凸塊188係代表一種可形成在導電層146之上的互連結構的類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
該重組晶圓或面板係被單粒化成為個別的扇出晶圓級晶片尺寸封裝(Fo-WLCSP 190)單元。內嵌在Fo-WLCSP 190中的半導體晶粒124係透過凸塊138而電連接至積層的互連結構156及凸塊188。該積層的互連結構156係在一過渡階段，亦即在安裝半導體晶粒124之前藉由開路/短路探針或是自動示波器的檢查來加以檢查及測試是否已知為良好的。半導體晶粒124係進一步透過內部的導電凸塊166而電連接至積層的互連結構186。該些積層的互連結構156及186係在不同的時間點，相關囊封體170之相對的表面而形成在載體140之上。該積層的互連結構186係在額外的裝置集積之前先被檢查及測試是否已知為良好的。
類似於圖4i，圖5係展示Fo-WLCSP 200的一實施例，其中內嵌的半導體晶粒124及柱形凸塊202係設置在囊封體170內以用於在積層的互連結構156以及積層的互連結構186之間的垂直互連。
圖6a-6f係從圖4b繼續以描繪另一實施例，其係包含如同從一類似於圖3a的半導體晶圓被單粒化並且具有一背表面208以及主動表面210的半導體晶粒204，該主動表面210係包含類比或數位電路，該些類比或數位電路係實施為形成在該晶粒內並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個形成在主動表面210內之電晶體、二極體以及其它電路元件以實施類比電路或數位電路，例如DSP、ASIC、記憶體或是其它的信號處理電路。半導體晶粒204亦可包含例如是電感器、電容器及電阻器的IPD，以用於RF信號處理。
在圖6a中，一導電層212係利用PVD、CVD、電解的電鍍、無電的電鍍製程或是其它適當的金屬沉積製程以形成在主動表面210之上。導電層212可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層212係運作為電連接至主動表面210上的電路的接觸墊。
一絕緣或保護層214係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在主動表面210及導電層212之上。該絕緣層214係包含一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。絕緣層214的一部分係藉由LDA來加以移除，以露出導電層212。
一絕緣或保護層216係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在絕緣層214及導電層212之上。該絕緣層216係包含一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。該絕緣層216係保護半導體晶粒204。或者是，絕緣層214及216可以是具有厚度大於15微米(μm)之相同的層。
在背表面208被定向朝向該積層的互連結構之下，帶有晶粒附接膜(DAF)220的半導體晶粒204係利用一拾放的操作而被安裝到積層的互連結構156。圖6b係展示半導體晶粒204和DAF 220一起被安裝到積層的互連結構156以作為一重組晶圓。半導體晶粒204是一在安裝到積層的互連結構156之前已經被測試的KGD。離散的半導體裝置222亦利用導電膏224而冶金且電耦接至導電層150。離散的半導體裝置222可以是一電感器、電容器、電阻器、電晶體或是二極體。
一3D互連結構226係形成在導電層150之上。該3D互連結構226係包含一例如是Cu或Al之內部的導電的合金凸塊228、以及例如是焊料合金SAC305、Cu、聚合物或是塑膠的保護層230。或者是，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層150之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層150。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊。在某 些應用中，該些凸塊係被回焊第二次以改善至導電層150的電性接觸。該些凸塊亦可以壓縮接合或是熱壓接合到導電層150。
在圖6c中，一種囊封體或是模製化合物234係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆、或是其它適當的施用器而沉積在半導體晶粒204、積層的互連結構156以及3D互連結構226之上。囊封體234可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體234是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。
在圖6d中，囊封體234的一部分係在一利用研磨機236的研磨操作中加以移除，以平坦化該表面且降低該囊封體的厚度，並且露出絕緣層216及內部的導電凸塊228。一化學蝕刻或CMP製程亦可被利用，以消除產生自該研磨操作及平坦化囊封體234的機械性損壞。或者是，囊封體234的一部分係藉由LDA或鑽孔來加以移除，以露出內部的導電凸塊228。該絕緣層216係藉由濕式化學剝除或是LDA來加以剝除，以露出導電層212。
在圖6e中，一絕緣或保護層240係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在囊封體234及3D互連結構226之上。該絕緣層240係包含一或多個層的具有或是不具有填充物或纖維的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。絕緣層216及240的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層212 及內部的導電凸塊228。
一導電層或是RDL 242係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在絕緣層240及內部的導電凸塊228之上。導電層242可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層242的一部分係電連接至內部的導電凸塊228。導電層242的另一部分係電連接至導電層212。根據半導體晶粒204的設計及功能，導電層242的其它部分可以是電性共通或是電性隔離的。
一絕緣或保護層244係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在絕緣層240及導電層242之上。該絕緣層244係包含一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或是其它具有類似絕緣及結構的性質之材料。在一實施例中，為了強化的彎曲強度，絕緣層244係包含一內嵌的玻璃布、玻璃纖維布、填充物或是纖維。絕緣層244的一部分係藉由利用雷射246的LDA來加以移除，以露出導電層242。或者是，絕緣層244的一部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層242。
絕緣層240及244以及導電層242的組合係構成一積層的互連結構248。該積層的互連結構248係形成在載體140之上，但是在一和積層的互連結構156不同的時間點，亦即在沉積囊封體234之後。該積層的互連結構248係在一過渡階段，亦即在額外的裝置集積(見於圖10)之前先被檢查及測試是否已知為良好的。
在圖6f中，載體140及介面層142係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱釋放、UV光、雷射掃描或是濕式剝除來加 以移除，以露出絕緣層144。一背面研磨帶或支撐載體可在移除載體140之前先被施加至絕緣層244。絕緣層144的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層146。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層146之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層146。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊250。在某些應用中，凸塊250係被回焊第二次，以改善至導電層146的電性接觸。在一實施例中，凸塊250係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層146。凸塊250係代表一種可被形成在導電層146之上的互連結構的類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
該重組晶圓或是面板係被單粒化成為個別的Fo-WLCSP 252單元。內嵌在Fo-WLCSP 252中的半導體晶粒204係電連接至積層的互連結構248。該積層的互連結構248係在額外的裝置集積之前先被檢查及測試是否已知為良好的。半導體晶粒204係透過內部的導電凸塊228進一步電連接至積層的互連結構156。該些積層的互連結構156及248係在不同的時間點，相關囊封體234之相對的表面而形成在載體140之上。該積層的互連結構156係在一過渡階段，亦即在安裝半導體晶粒204之前，藉由開路/短路探針 或是自動示波器的檢查來加以檢查及測試是否已知為良好的。
圖7a-7d係從圖4c繼續來描繪另一實施例，積層的互連結構260係包含一核心積層基板262。在圖7a中，複數個穿孔的貫孔係利用雷射鑽孔、機械鑽孔或是深反應性離子蝕刻(DRIE)穿過基板262來加以形成。該些貫孔係利用電解的電鍍、無電的電鍍製程或是其它適當的沉積製程而被填入Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)或是其它適當的導電材料，以形成導電的貫孔263。或者是，Cu係藉由無電及電解的Cu電鍍而沉積在該些穿孔的貫孔的側壁上，並且該些貫孔係被填入Cu膏或是具有填充物的樹脂。
一導電層或是RDL 264係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在基板262以及導電的貫孔263之上。導電層264可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層264的一部分係電連接至導電的貫孔263。根據半導體晶粒124或204的設計及功能，導電層264的其它部分可以是電性共通或是電性隔離的。
一絕緣或保護層266係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在基板262及導電層264之上。該絕緣層266係包含一或多個層的具有或是不具有填充物或纖維之SiO2、Si3N4、SiaN、Ta2O5、Al2O3、聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。絕緣層266的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層264。離散的半導體裝置270係利用導電膏272而冶金且電耦接至導電層264。離散的半導體裝置270可 以是一電感器、電容器、電阻器、電晶體或是二極體。
一導電層或是RDL 276係利用一例如是濺鍍、電解的電鍍以及無電的電鍍之圖案化及金屬沉積製程以形成在基板262及導電的貫孔263之上。導電層276可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag或是其它適當的導電材料。導電層276的一部分係電連接至導電的貫孔263。根據半導體晶粒204的設計及功能，導電層276的其它部分可以是電性共通或是電性隔離的。
一絕緣或保護層278係利用PVD、CVD、印刷、疊層、旋轉塗覆、噴霧塗覆、燒結或是熱氧化以形成在基板262及導電層276之上。該絕緣層278係包含一或多個層的具有/不具有填充物或纖維之SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚合物介電質光阻、或是其它具有類似絕緣及結構的性質之材料。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層264之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層264。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊274。在某些應用中，凸塊274係被回焊第二次，以改善至導電層264的電性接觸。在一實施例中，凸塊274係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該些凸塊亦可以壓縮接合或是熱壓接合到導電層264。凸塊274係代表一種可被形成在導電層264之上的互連結構的 類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
離散的半導體裝置270係利用導電膏272而冶金且電耦接至導電層264。離散的半導體裝置270可以是一電感器、電容器、電阻器、電晶體或是二極體。
在凸塊274被定向朝向積層的互連結構156之下，帶有核心基板262之積層的互連結構260係利用一拾放的操作，以一重組晶圓或面板型式而被安裝到積層的互連結構156。圖7b係展示在凸塊274被接合到導電層150之下，帶有核心基板262之積層的互連結構260安裝到積層的互連結構156。
在圖7c中，一種囊封體或是模製化合物280係利用一在真空及高壓固化下的膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆、或是其它適當的施用器而沉積在半導體晶粒124之上以及在積層的互連結構156及260之間的凸塊274周圍。囊封體280可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體280是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。囊封體280可以包覆成型或是溢流在絕緣層278的表面上。
絕緣層278以及囊封體280之選配的包覆成型部分的一部分係藉由利用雷射282的LDA來加以移除，以露出導電層276。或者是，絕緣層278的一部分係藉由一蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層276。
在圖7d中，載體140及選配的介面層142係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱釋放、UV光、雷射掃描或是濕式剝除來加以移除，以露出絕緣層144。在移除載體140之前，一背面研磨帶或是支撐載體可被施加至絕緣層244。絕緣層144的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層146。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層146之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層146。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊284。在某些應用中，凸塊284係被回焊第二次，以改善至導電層146的電性接觸。在一實施例中，凸塊284係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層146。凸塊284係代表一種可被形成在導電層146之上的互連結構的類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
該重組晶圓或是面板係被單粒化成為個別的扇出晶圓級晶片尺寸封裝(Fo-WLCSP)286單元。內嵌在Fo-WLCSP 286中的半導體晶粒124係透過凸塊138而電連接至積層的互連結構156及凸塊284。該積層的互連結構156係在一過渡階段，亦即在安裝半導體晶粒124之前，藉由開路/短路探針或是自動示波器的檢查來加以檢查及測試是否已知為良好的。 半導體晶粒124係進一步透過凸塊274而電連接至積層的互連結構260。該些積層的互連結構156及260係在不同的時間點，相關囊封體280之相對的表面來加以形成。該積層的互連結構260係在額外的裝置集積之前先被檢查及測試是否已知為良好的。
類似於圖7d，圖8係展示Fo-WLCSP 290的一實施例，其中內嵌的半導體晶粒124係安裝到積層的互連結構260。
類似於圖7d，圖9a-9b係展示Fo-WLCSP 300的一實施例，其中積層的互連結構156係形成在載體或是臨時的基板301之上，該載體或是臨時的基板301係包含例如是矽、聚合物、鈹氧化物、玻璃或是其它適當的低成本剛性材料之犧牲或是可重複使用的基底材料，以用於結構的支撐。一包含絕緣層304、導電層306、絕緣層308、導電層310及絕緣層312之積層的互連結構302係形成在載體或是臨時的基板314之上，該載體或是臨時的基板314係包含例如是矽、聚合物、鈹氧化物、玻璃或是其它適當的低成本剛性材料之犧牲或是可重複使用的基底材料，以用於結構的支撐。在一實施例中，為了強化的彎曲強度，絕緣層312係包含一內嵌的玻璃布、玻璃纖維布、填充物或是纖維，例如E-玻璃布、T-玻璃布、Al2O3或是二氧化矽填充物。離散的半導體裝置316係利用導電膏318而冶金且電耦接至導電層306。離散的半導體裝置316可以是一電感器、電容器、電阻器、電晶體或是二極體。
在圖9a中，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層306之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、 Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層306。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊320。在某些應用中，凸塊320係被回焊第二次，以改善至導電層306的電性接觸。在一實施例中，凸塊320係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層306。凸塊320係代表一種可被形成在導電層306之上的互連結構的類型。該互連結構亦可以使用柱形凸塊、微凸塊或是其它電互連。
在凸塊320被定向朝向積層的互連結構156之下，積層的互連結構302係以一重組晶圓或是面板型式，利用一拾放的操作而被安裝到積層的互連結構156。圖9b係展示積層的互連結構260係利用凸塊320被接合到導電層150而安裝到積層的互連結構156。一種囊封體或是模製化合物322係利用一膏印刷、壓縮模製、轉移模製、液體囊封體模製、真空疊層、旋轉塗覆、或是其它適當的施用器而沉積在半導體晶粒124之上並且在積層的互連結構156及302之間的凸塊320周圍。囊封體322可以是聚合物複合材料，例如具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封體322是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。
載體314係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱釋放、UV光、雷射掃描或是濕式剝除來加以移除。絕緣層312的一部分係藉由LDA或是蝕刻製程透過一圖案化的光阻層來加以移除，以露出導電層310。
載體301係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱釋放、UV光、雷射掃描或是濕式剝除來加以移除。一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或是網版印刷製程而沉積在導電層146之上。該凸塊材料可以是具有一選配的助熔溶劑之Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。該凸塊材料係利用一適當的安裝或是接合製程而被接合到導電層146。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊324。在某些應用中，凸塊324係被回焊第二次，以改善至導電層146的電性接觸。在一實施例中，凸塊324係形成在一具有一潤濕層、阻障層及黏著劑層的UBM之上。該凸塊亦可以壓縮接合或是熱壓接合到導電層146。凸塊324係代表一種可被形成在導電層146之上的互連結構的類型。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊或是其它電互連。
該重組晶圓或是面板係被單粒化成為個別的Fo-WLCSP 300單元。內嵌在Fo-WLCSP 300中的半導體晶粒124係透過凸塊138而電連接至積層的互連結構156及凸塊324。該積層的互連結構156係在一過渡階段，亦即在安裝半導體晶粒124之前，藉由開路/短路探針或是自動示波器的檢查來加以被檢查及測試是否已知為良好的。半導體晶粒124係進一步透過凸塊320而電連接至積層的互連結構302。該些積層的互連結構156及302係在不同的時間點，相關囊封體322之相對的表面來加以形成。該積層的互連結構302係在額外的裝置集積之前先被檢查及測試是否已知為良好的。
圖10係描繪一種PoP配置，其係具有如同從一類似於圖3a 的半導體晶圓被單粒化並且具有一背表面338及主動表面340的半導體晶粒330，該主動表面340係包含類比或數位電路，該些類比或數位電路係被實施為形成在該晶粒之內並且根據該晶粒的電性設計及功能電互連的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個形成在主動表面340內之電晶體、二極體以及其它電路元件以實施類比電路或數位電路，例如DSP、ASIC、記憶體或是其它信號處理電路。半導體晶粒330亦可包含例如是電感器、電容器及電阻器的IPD，以用於RF信號處理。
複數個凸塊346係形成在半導體晶粒330的接觸墊348上。半導體晶粒330係利用凸塊346冶金並且電連接至導電層180而被安裝到Fo-WLCSP 190，以成為PoP 350。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於該些實施例的修改及調適可以在不脫離如以下的申請專利範圍中所闡述之本發明的範疇下加以完成。
124‧‧‧半導體晶粒(構件)
128‧‧‧背表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣(保護)層
136‧‧‧絕緣(保護)層
138‧‧‧球(凸塊)
139‧‧‧鋸刀(雷射切割工具)
144‧‧‧絕緣(保護)層
146‧‧‧導電層
148‧‧‧絕緣(保護)層
150‧‧‧導電層(重新分配層(RDL))
152‧‧‧絕緣(保護)層
156‧‧‧積層的互連結構
158‧‧‧底膠填充材料
160‧‧‧離散的半導體裝置
162‧‧‧導電膏
166‧‧‧內部的導電合金凸塊
168‧‧‧保護層
170‧‧‧囊封體(模製化合物)
178‧‧‧絕緣(保護)層
180‧‧‧導電層(RDL)
182‧‧‧絕緣(保護)層
186‧‧‧積層的互連結構
188‧‧‧球(凸塊)
190‧‧‧Fo-WLCSP

Claims (15)

  1. 一種製造一半導體裝置之方法，其係包括：提供一載體；在該載體之上形成一第一互連結構；測試該第一互連結構；在測試該第一互連結構之後設置一半導體晶粒在該第一互連結構之上；在該第一互連結構之上形成一垂直的互連結構；在該半導體晶粒、第一互連結構以及垂直的互連結構之上沉積一囊封體；以及在該囊封體之上形成一第二互連結構，並且該第二互連結構係電耦接至該垂直的互連結構。
  2. 如申請專利範圍第1項之方法，其進一步包含在該第一互連結構或是該第二互連結構之上設置一離散的半導體裝置。
  3. 如申請專利範圍第1項之方法，其進一步包含移除該囊封體的一部分以露出該垂直的互連結構。
  4. 如申請專利範圍第1項之方法，其中該第一互連結構或是第二互連結構係包含一具有一內嵌的玻璃布、玻璃纖維布、填充物或是纖維之絕緣層。
  5. 一種製造一半導體裝置之方法，其係包括：形成一第一已知為良好的互連結構；在該第一已知為良好的互連結構之上設置一半導體晶粒；在該半導體晶粒以及第一已知為良好的互連結構之上沉積一囊封體； 以及在該囊封體之上形成一第二互連結構。
  6. 如申請專利範圍第5項之方法，其進一步包含形成一電耦接至該第一已知為良好的互連結構以及該第二互連結構之垂直的互連結構。
  7. 如申請專利範圍第5項之方法，其進一步包含移除該囊封體的一部分以露出該垂直的互連結構。
  8. 如申請專利範圍第5項之方法，其進一步包含在該第一互連結構或是該第二互連結構之上設置一離散的半導體裝置。
  9. 如申請專利範圍第5項之方法，其中該第一已知為良好的互連結構或是第二互連結構係包含一具有一內嵌的玻璃布、玻璃纖維布、填充物或是纖維之絕緣層。
  10. 一種半導體裝置，其係包括：一第一已知為良好的第一互連結構；一設置在該第一已知為良好的互連結構之上的半導體晶粒；一沉積在該半導體晶粒以及第一已知為良好的互連結構之上的囊封體；以及一形成在該囊封體之上的第二互連結構。
  11. 如申請專利範圍第10項之半導體裝置，其進一步包含一電耦接至該第一互連結構以及第二互連結構之垂直的互連結構。
  12. 如申請專利範圍第10項之半導體裝置，其中該半導體晶粒是一已知為良好的晶粒。
  13. 如申請專利範圍第10項之半導體裝置，其進一步包含一設置在該第 一已知為良好的互連結構或是該第二互連結構之上的離散的半導體裝置。
  14. 如申請專利範圍第10項之半導體裝置，其中該第一已知為良好的互連結構或是該第二互連結構係包含一具有一內嵌的玻璃布、玻璃纖維布、填充物或是纖維之絕緣層。
  15. 如申請專利範圍第10項之半導體裝置，其中該垂直的互連結構係包含一凸塊或是柱形凸塊。
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