TWI733948B - 半導體裝置及形成具有嵌入式電感或封裝的整合式系統級封裝模組之方法 - Google Patents

半導體裝置及形成具有嵌入式電感或封裝的整合式系統級封裝模組之方法 Download PDF

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TWI733948B
TWI733948B TW106139939A TW106139939A TWI733948B TW I733948 B TWI733948 B TW I733948B TW 106139939 A TW106139939 A TW 106139939A TW 106139939 A TW106139939 A TW 106139939A TW I733948 B TWI733948 B TW I733948B
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substrate
semiconductor
package
opening
sip module
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TW106139939A
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TW201834084A (zh
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梁悳景
白蕓在
朴利洙
金五漢
李勳擇
李喜秀
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新加坡商星科金朋有限公司
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Abstract

一種半導體裝置係具有一基板，其中一第一開口以及第二開口係在該基板中加以形成。一第一半導體構件係被設置在該基板上。該基板係被設置在一載體上。一第二半導體構件係被設置在該基板的該第一開口中的該載體上。一第三半導體構件係被設置在該第二開口中。在某些實施例中，該第三半導體構件是一半導體封裝。一第一屏蔽層可被形成在該半導體封裝之上。一密封劑係被沉積在該基板、第一半導體構件、以及第二半導體構件之上。一屏蔽層可被形成在該密封劑之上。

Description

半導體裝置及形成具有嵌入式電感或封裝的整合式系統級封裝模組之方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種半導體裝置以及形成具有嵌入式電感、封裝或兩者之整合式系統級封裝(SiP)模組之方法。
國內優先權的主張
本申請案係主張2016年12月7日申請的美國臨時申請案號62/431,165的益處，該美國臨時申請案係被納入在此作為參考。
半導體裝置係常見於現代的電子產品中。半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、光電的發電、以及產生用於電視顯示器的視覺影像。半導體裝置係見於通訊、電力轉換、網路、電腦、娛樂、以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體封裝通常是由數個主動半導體構件、離散的被動構 件、以及整合的被動裝置(IPD)所做成的，其係一起被封裝成為單一封裝的系統，有時是以一系統級封裝(SiP)模組著稱的。相較於傳統的半導體封裝，SiP模組係提供較高的密度以及強化的電性功能。
SiP模組的主動及被動構件通常是被安裝到一用於結構的支撐及電互連的基板。該基板以及構件係為了環境的保護而被密封。在該封裝的頂表面之密封劑一般係被平坦化以做成一方塊形的封裝。因為該頂表面是橫跨該些裝置而為平坦的，因此該密封劑表面必須是至少和該SiP模組內之最高的構件一樣高的。當較高的構件被使用時，則橫跨該整個裝置，甚至是在較矮的構件之上係需要更多的密封劑。密封劑係被浪費在較矮的構件之上，因而半導體裝置係被做成實際上大於所必須者。因此，對於在較高的構件被使用時，形成、具有降低的高度之SiP模組及方法係存在著需求。
根據本發明之一特點，一種製造一半導體裝置之方法係包括：提供一基板；在該基板中形成一第一開口；在該基板上設置一第一半導體構件；在一載體上設置該基板；在該基板的該第一開口中的該載體上設置一第二半導體構件；以及在該基板、第一半導體構件、以及第二半導體構件之上沉積一密封劑。該方法進一步包含：在該基板中形成一第二開口；以及在該第二開口中設置一第三半導體構件。在該方法中，該第三半導體構件是一半導體封裝。該方法進一步包含在該半導體封裝之上形成一屏蔽層。該方法進一步包含在該密封劑之上形成一屏蔽層。在該方法中，從該密封劑的一頂表面至該基板的一頂表面的一距離係小於該第二半導體 構件的一高度。
根據本發明的另一特點，一種製造一半導體裝置之方法係包括：提供一基板；在該基板之上設置一第一半導體構件；相鄰該基板來設置一第二半導體構件；以及在該基板、第一半導體構件、以及第二半導體構件之上沉積一密封劑。該方法進一步包含：在該基板中形成一開口；以及在該開口中設置該第二半導體構件。該方法進一步包含在該基板的一高度之內設置該第二半導體構件。在該方法中，該第二半導體構件的一高度係大於該基板的一高度。
根據本發明的另一特點，一種半導體裝置係包括：一基板；一被設置在該基板之上的第一半導體構件；以及一相鄰該基板而被設置的第二半導體構件，其中該第二半導體構件係延伸至在該基板的一頂表面之上的一高度。在該半導體裝置中，該第二半導體構件的一高度係大於該第一半導體構件的一高度。該半導體裝置進一步包含一相鄰該基板而被設置的半導體封裝。在該半導體裝置中，該第二半導體構件係被設置在該基板的一開口之內。該半導體裝置進一步包含一相對於該第一半導體構件而被疊層在該基板上的帶，其中該第二半導體構件係被設置在該帶上。
100:半導體晶圓
102:基底基板材料
104:半導體晶粒
106:切割道
108:非主動表面
110:主動表面
112:導電層
114:凸塊
150:基板
152:切割道
153:絕緣材料
154:導電層
156:導電層
158:導電貫孔
160:開口
162:離散的裝置
166:焊料膏
170:帶
174:離散的裝置
176:互連結構
180:密封劑
182:面板
184:載體
186:介面層(雙面帶)
190:凸塊
192:鋸刀(雷射切割工具、水切割工具)
196:SiP模組
200:PCB單元
204:導電層
204a:導電層的一部分
206:導電層
220:SiP模組
230:SiP模組
232:基板
240:SiP模組
242:基板
250:SiP模組
252:基板
260:SiP模組
262:屏蔽層
300:基板
302:切割道
304、304a:導電層
306:導電層
308:導電貫孔
310:開口
312:開口
320:帶
330:半導體封裝
332:基板
334:密封劑
340:密封劑
344、344a:凸塊
350:SiP模組
360:SiP模組
362:封裝
370:SiP模組
380:SiP模組
382:基板
384:開口
390:SiP模組
392:屏蔽層
400:SiP模組
402:屏蔽層
502:PCB(基板)
504:導電層(信號線路)
505:電子裝置
506:接合導線封裝
508:覆晶
510:球格陣列(BGA)
512:凸塊晶片載體(BCC)
516:平台柵格陣列(LGA)
518:多晶片的模組(MCM)
520:四邊扁平無引腳封裝(QFN)
524:嵌入式晶圓層級球格陣列(eWLB)
526:晶圓級晶片尺寸封裝(WLCSP)
圖1a-1c係描繪一半導體晶圓，其中複數個半導體晶粒係藉由切割道來加以分開；圖2a-2i係描繪一種形成具有一嵌入式電感的一SiP模組的製程；圖3係描繪該具有一嵌入式電感的SiP模組； 圖4a-4d係描繪利用PCB單元來形成該SiP模組；圖5a-5d係描繪該SiP模組的替代實施例；圖6a-6d係描繪一種形成具有一嵌入式電感以及一嵌入式半導體封裝兩者的一SiP模組的製程；圖7係描繪該具有一嵌入式電感以及一嵌入式半導體封裝兩者的SiP模組；圖8a-8c係描繪該SiP模組的替代實施例；圖9a-9c係描繪用於該SiP模組的電磁干擾(EMI)屏蔽選項；以及圖10a-10b係描繪一印刷電路板(PCB)，其中一SiP模組係被安裝到該PCB的一表面。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
如同在此所用的術語"半導體晶粒"係指該些字詞的單數及複數形兩者，並且於是可以指稱單一半導體裝置以及多個半導體裝置兩者。如同在此所用的術語"半導體構件"或單純是"構件"係指被形成在半導體晶粒中的主動裝置、利用半導體晶粒所形成的封裝、離散的主動或被動裝置、整合的主動或被動電路、或是任何其它主動或被動電性部件。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每一個晶粒係包含電連接以形成功能電路的主動及被動電性構件。例如是電晶體及二極體的主動電性構件係具有控制電流流動的能力。例如是電容器、電感器及電阻器的被動電性構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒，並且為了結構的支撐、電互連以及環境的隔離來封裝該半導體晶粒。為了單粒化該些半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來加以劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用導電層、凸塊、柱形凸塊、導電膏、或是引線接合來做成。一密封劑或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電性隔離。該完成的封裝係接著被插入一電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a係展示一具有一種例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體材料的基底基板材料102的半導體晶圓100。複數個半導體晶粒或構件104係被形成在晶圓100上，半導體晶粒104係藉由一非主動的晶粒間的晶圓區域或切割道106來加以分開。切割道106係提供切割區域以將半導體晶圓100 單粒化成為個別的半導體晶粒104。在一實施例中，半導體晶圓100係具有一100-450毫米(mm)的寬度或直徑。
圖1b係展示半導體晶圓100的一部分的橫截面圖。每一個半導體晶粒104係具有一背表面或非主動表面108以及一包含類比或數位電路的主動表面110，該類比或數位電路係被實施為形成在該晶粒內或是之上並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。該些電路可包含一或多個電晶體、二極體、以及其它的電路元件，其係被形成在主動表面110內以實施類比電路或數位電路，其例如是一數位信號處理器(DSP)、特殊應用積體電路(ASIC)、記憶體、或是其它的信號處理電路。半導體晶粒104亦可包含例如是電感器、電容器及電阻器之IPD，其係被形成在該半導體晶粒的表面之上的互連層中或是上面，以用於RF信號處理或是其它目的。在某些實施例中，半導體晶粒104係包含多個主動表面，其中電路係被形成在每一個主動表面之中或是之上。
一導電層112係利用PVD、CVD、電解的電鍍、無電的電鍍、或是其它適當的金屬沉積製程而被形成在主動表面110之上。導電層112可以是一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層112係運作為電連接至主動表面110的電路的接觸墊。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程來沉積在導電層112之上。該凸塊材料可以是具有一選配的助熔溶劑的Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料、或是其之一組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的 焊料、或是無鉛的焊料。該凸塊材料係利用一適當的附接或是接合製程而被接合到導電層112。在某些實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊114。在一實施例中，凸塊114係被形成在具有一潤濕層、一阻障層、以及一黏著層的凸塊下金屬化(UBM)之上。凸塊114亦可被壓縮接合或是熱壓接合到導電層112。凸塊114係代表可被形成在導電層112之上的一種類型的互連結構。該些互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊、或是其它的電互連。
在圖1c中，半導體晶圓100係利用一鋸刀或雷射切割工具118，透過切割道106而被單粒化成為個別的半導體晶粒104。該些個別的半導體晶粒104可以在單粒化之前或是之後加以檢查及電性測試，以用於已知良好的晶粒(KGD)的識別。
圖2a-2i係描繪一種形成SiP模組的製程，該些SiP模組係包含半導體晶粒104以及嵌入式電感。圖2a係展示基板150的橫截面圖，其係包含藉由切割道152分開的複數個用於SiP模組的形成的區域。儘管只有兩個用於形成SiP模組的區域被展示，但是基板150在其它實施例中是大許多的，其係具有空間以並行地形成數百個或是數千個SiP模組。基板150係由絕緣材料153所形成的，其中導電層154及156係被形成在該絕緣層的兩個主要的表面上。在一實施例中，絕緣材料153是一模製基板。在某些實施例中，基板150係利用和複數個導電層交錯的複數個絕緣層來加以形成，此係容許有更複雜的信號繞線。導電層154及156的部分是電性共通或是電性隔離的，其係根據被形成的SiP模組的設計及功能而定。
導電層154及156可以是一或多層的Al、Cu、Sn、Ni、Au、 Ag、或是其它適當的導電材料。導電貫孔158係延伸穿過絕緣材料153，以將導電層154的部分電連接至導電層156的部分。導電層154及156係提供橫跨基板150的水平的電互連，而導電貫孔158係提供穿過基板150的垂直的電互連。在一實施例中，導電貫孔158係藉由蝕刻、鑽孔、雷射剝蝕、或是其它適當的製程來提供一穿過絕緣材料153的開口，並且接著沉積或是電鍍導電材料到該開口中來加以形成。在某些實施例中，用於導電貫孔158的導電材料係沉積到絕緣材料153的開口中，以作為形成導電層154或156的部分。
基板150亦可以是任何適當的積層中介體、PCB、晶圓形式、帶式中介體、引線架、內嵌式線路基板(ETS)、或是其它類型的基板。基板150可包含具有酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯、以及其它強化纖維或織物的一組合之一或多個疊層的聚四氟乙烯(PTFE)預浸物(預浸料)、FR-4、FR-1、CEM-1、或是CEM-3。絕緣材料153係包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、阻焊劑、聚醯亞胺、苯環丁烯(BCB)、聚苯並噁唑(PBO)、以及其它具有類似絕緣及結構的性質之材料。基板150亦可以是一種多層的撓性的積層、陶瓷、銅箔基板、玻璃、或是包含一主動表面的半導體晶圓，該主動表面係包含一或多個電晶體、二極體、以及其它的電路元件以實施類比或數位電路。
基板150係在其中電感、或是其它較高的構件將被設置在該些SiP模組的覆蓋區之內的位置處包含孔洞或開口160。開口160係利用一鋸刀、雷射切割工具、水切割工具、一蝕刻製程、或是其它用於形成一穿 過一基板的開口的適當的機構，而穿過基板150來加以形成。在其它實施例中，基板150係以一種留下穿過該基板的開口160的方式來加以形成，而不須在該基板被製造之後分開地形成一開口。
圖2b係從圖2a的頂端來描繪基板150的平面圖。導電層154係包含複數個接觸墊，其係用於根據需要來表面安裝半導體晶粒以及離散的構件以實施一給定的電性功能。導電層154可包含任意所要的數量、形狀及佈局的接觸墊。在某些實施例中，導電層154及導電層156亦包含導電線路以將複數個接觸墊彼此電連接。開口160係在其中較高的構件將被置放的位置處，穿過基板150來加以形成。基板150可以在將半導體晶粒以及其它構件安裝在該基板上之前，在圖2a及2b中可見的目前的階段加以測試。
在圖2c中，半導體晶粒104以及離散的裝置162係被表面安裝到導電層154之上。在某些實施例中，基板150係被設置在一用於半導體晶粒104以及離散的裝置162的安裝的載體上。半導體晶粒104可以在安裝到基板150上之前先被測試是否為KGD，以避免在良好的基板裝置區域上利用到不良的晶粒。此外，基板150的區域可以在安裝構件之前先加以測試，因而該基板的具有製造缺陷的區域可被拋棄，而不會在一不良的基板上浪費KGD。在某些實施例中，不良或空白的半導體晶粒104係被設置在基板150的不良的區域上，以保持橫跨該基板的重量分布均勻，並且有助於控制翹曲。
圖2c係展示基板150的每一個裝置區域係具有兩個離散的裝置162，其可以是電感器、電容器、電阻器、或是其它被動電路構件。離 散的裝置162亦可以是具有主動功能的裝置，例如是功率電晶體、暫態電壓抑制的二極體、等等。在其它實施例中，主動及被動裝置的任意組合可以根據需要而被設置在基板150上，以實施一最終的SiP模組所要的功能。在一實施例中，離散的裝置162係實施一帶通濾波器、或是其它射頻(RF)信號處理網路。在另一實施例中，離散的裝置162係濾波至半導體晶粒104的一電源信號。離散的裝置162可以實施任何所要的電性功能。在某些實施例中，離散的裝置162係結合一被設置在開口160之內的構件來運作。
離散的裝置162係透過焊料或焊料膏166來機械式地接合及電連接至導電層154。在一實施例中，焊料膏166係被印刷到基板150之上，和實體接觸的離散的裝置162一起加以回焊，並且接著加以去焊。半導體晶粒104係透過導電的凸塊114來機械式地接合及電連接至導電層154。在某些實施例中，凸塊114及焊料膏166係同時被回焊，以在單一步驟中表面安裝所有的構件。
在圖2d中，一帶170係相對於半導體晶粒104及離散的裝置162而被疊層在基板150的底表面上。帶170可包含一種黏著材料，以將構件保持在適當的地方。帶170係延伸橫跨開口160，以支撐被設置在該開口之內的構件。帶170係運作為一載體，以和基板150形成SiP子模組。在某些實施例中，具有帶170的基板150係被設置在另一載體上，以用於進一步的處理。在其它實施例中，另一種類型的具有一黏著介面層的載體係被使用來取代帶170。
在圖2e中，離散的裝置174係被設置在基板150的開口160之內的帶170上。離散的裝置174係高於半導體晶粒104以及離散的裝置 162。離散的裝置174係被設置在開口160之內，而不是如同離散的裝置162地在基板150上，以降低離散的裝置174在最終的封裝之內的高度。離散的裝置174係被描繪為電感，因為電感通常是在SiP模組中之最高的構件。然而，除了電感以外的其它構件係根據需要而被設置在開口160中，以降低任意構件的高度。在某些實施例中，多個較高的離散的裝置係被設置在每一個SiP模組的單一開口160之內。在一實施例中，每一個SiP模組係包含複數個穿過基板150而被形成的開口160。
離散的裝置174係在該些離散的裝置上包含互連結構176。離散的裝置174係在互連結構176接觸帶170之下，被設置在開口160中。當帶170之後被移除時，互連結構176係和導電層156的接觸墊一起被露出，以用於後續的電互連。在一實施例中，互連結構176是類似於導電層156的接觸墊。在另一實施例中，互連結構176是類似於凸塊114的焊料凸塊、或是類似於焊料膏166的焊料膏。
在圖2f中，一密封劑或模製化合物180係利用一膏印刷、壓縮模製、轉移模製、液體密封劑模製、真空疊層、旋轉塗覆、或是其它適當的施用器，而沉積在基板150、半導體晶粒104、以及離散的裝置162及174之上。密封劑180可以是例如環氧樹脂、環氧丙烯酸酯的聚合物複合材料、或是具有或不具有填充物的聚合物。密封劑180是非導電的，提供結構的支撐，並且在環境上保護該半導體裝置免於外部的元素及污染物。密封劑180係流動在導電的凸塊114之間的半導體晶粒104之下、在焊料膏166之間的離散的裝置162之下、以及在互連結構176之間的離散的裝置174之下，以完全地填入在基板150與該些半導體晶粒及離散的裝 置之間的空間。在其它實施例中，一個別的底膠填充係被使用於某些或全部的構件。
被覆蓋密封劑180的基板150係形成一面板182。使得該較高的離散的裝置174在基板150的一開口160之內係降低在面板182中的最高的構件的高度，因此降低覆蓋所有的構件所需的密封劑180的最小的厚度。在某些實施例中，密封劑180係被沉積成超過所必需的厚，並且加以背面研磨來降低面板182的一厚度。背面研磨係利用化學機械式平坦化(CMP)、一蝕刻製程、雷射直接剝蝕(LDA)、或是其它適當的薄化程序來加以執行。
在圖2g中，面板182係加以翻轉，並且在基板150被定向成背對該載體下被設置在載體184上。一介面層或雙面帶186係被形成在載體184之上，以作為一暫時的黏著接合膜、蝕刻停止層、或是熱釋放層。帶170係利用一熱釋放、紫外線釋放、機械式剝離、或是適合用於所用的帶的類型的其它移除製程而被移除。
在圖2h中，導電的凸塊190係被形成在面板182上，而在導電層156及互連結構176之上。凸塊190係類似於在半導體晶粒104上的凸塊114，並且可以是焊料凸塊、柱形凸塊、導電柱、或是其它適當的互連結構。凸塊190可以被回焊或是壓縮接合到導電層156之上。在其中互連結構176係包含焊料凸塊的實施例中，互連結構176可以和對應的凸塊190一起被回焊，以形成單一連續主體的焊料。
在圖2i中，面板182係利用鋸刀、雷射切割工具、或是水切割工具192，在切割道152之處穿過基板150及密封劑180而被單粒化成 為複數個SiP模組196。在某些實施例中，面板182係穿過開口160來加以單粒化。
圖3係描繪一完成的SiP模組196，其係利用熱釋放、UV釋放、機械式分離、或是其它適當的手段以從載體184來加以移除。凸塊190係被配置以耦接至一電子裝置的一PCB或是其它基板，以將SiP模組196的功能整合到該電子裝置中。半導體晶粒104以及離散的裝置162係透過導電層154、導電貫孔158、導電層156、以及導電的凸塊190來電耦接至該下面的PCB。在某些實施例中，半導體晶粒104係透過導電層154或156來耦接至離散的裝置162。SiP模組196係在單一容易整合的封裝中提供複數個構件，每一個構件都可以供該較大的電子裝置使用。
離散的裝置174是一相對高的構件。離散的裝置174係被設置在基板150的開口160之內，以降低SiP模組196的整體高度。移除在離散的裝置174之下的基板150係容許該較高的構件能夠位在一比離散的裝置162更低的平面上。因此，在SiP模組196中的最高的構件的頂端、以及因此的SiP模組的整體頂表面係低於若離散的裝置174是被設置在基板150上的情形。
在某些實施例中，密封劑180在基板150之上的高度係小於離散的裝置174的高度，使得若該離散的裝置被設置在該基板上，而且該密封劑高度維持相同的話，則離散的裝置174將不能夠容納到該密封劑中。離散的裝置174係被設置在基板150的一高度之內，換言之，離散的裝置174的垂直範圍的一部分係垂直地位在基板150的頂表面與底表面之間。離散的裝置174係佔用和基板150相同的垂直的空間，因為離散的裝置174 並未在基板150的覆蓋區之內。而是，離散的裝置174係相鄰基板150的一開口、或是在該開口之內。
增加穿過基板150的開口160係產生一具有相同構件的SiP模組，但是相對於一在該基板上具有所有的構件的裝置，其係具有一縮小的尺寸。該封裝高度被降低是因為該些較高的電感係被附接在該封裝的底部處，而不是在該基板上。納入有SiP模組196的電子裝置可以被做成較小的，此係為現今的電子裝置市場中的一項重要的考量。此外，將該電感設置在開口160中，而不是在基板150上，此係將該電感與其它構件分離，因而改善該電感的可靠度。
圖4a-4d係描繪對於每一個SiP模組利用個別的PCB單元200來形成SiP模組，而不是在所有一起被形成的SiP模組之間共同的一帶式基板150。圖4a係用橫截面來描繪單一PCB單元200，而圖4b係描繪一平面圖。PCB單元200係類似於基板150，但是被切割至用於單一SiP模組所必要的尺寸。在某些實施例中，PCB單元200係用和在以上的基板150完全相同的方式來加以形成，但是其係被單粒化為個別的PCB單元，而不是具有穿過該基板而被形成的開口160。
圖4c係描繪被安裝到PCB單元200之上的半導體晶粒104以及離散的裝置162的平面圖。PCB單元200以及離散的裝置174係被設置在帶170上。圖4c係描繪在一類似圖2e的狀態中的製程，但是其中每一個SiP模組有一個別的PCB單元200。該些單元係如上所論述地被封入、單粒化、以及形成凸塊，以形成在圖4d中的一SiP模組220。SiP模組220係類似於SiP模組196，其係藉由將較高的離散的裝置174設置在PCB單 元200的覆蓋區之外，來在裝置高度上提供一類似的益處。
圖5a係描繪利用基板232所形成的SiP模組230。基板232係類似於基板150，但是每一個裝置係包含兩個開口160。兩個開口160係容許兩個分開設置的離散的裝置174能夠在該基板覆蓋區的外部被使用。儘管圖5a係描繪在該裝置的邊緣的兩個開口160，但是開口160在其它實施例中係位在SiP模組之內的更為中心處。
圖5b係描繪具有基板242的SiP模組240。基板242係在半導體晶粒104以及離散的裝置162之間包含具有離散的裝置174的開口160。在另一實施例中，多個離散的裝置174係被設置在單一較大的開口之內。在一實施例中，一類似於PCB單元200的PCB單元係被使用，而不是一具有開口的帶式基板。離散的裝置174的任何適當的數量及位置都被思及。
圖5c係描繪具有基板252的SiP模組250。基板252係被配置以使得所有被安裝的構件都是被動的離散的裝置162，因而沒有主動裝置。SiP模組250並沒有主動功能，而是僅提供一組所要的被動構件以用於整合到一較大的系統中。將較高的離散的裝置174設置在開口160之內係降低SiP模組250的整體封裝高度。
圖5d係描繪具有被形成在該封裝之上的屏蔽層262的SiP模組260。SiP模組260係類似於SiP模組196，但是其係利用一容許屏蔽層262能夠被電鍍在封裝之上的製程來加以形成。在一實施例中，面板182係在圖2i中的單粒化之後被翻轉並且轉移到另一載體，並且屏蔽層262係被濺鍍在該些經單粒化的封裝之上。屏蔽層262係選配地透過導電層204 的一部分204a來電耦接至一下面的基板的一接地節點，該部分204a係被繞線至基板150的邊緣以接觸該屏蔽層。屏蔽層262亦可透過導電層206來耦接至一接地節點。屏蔽層262可以連接至一在SiP模組260之內的基板、一內嵌在該SiP模組之內的半導體封裝、或是一較大的電子裝置的一下面的基板之一接地線。
圖6a-6d係描繪形成具有一嵌入式電感以及一嵌入式子封裝的一SiP模組。圖6a係展示具有切割道302的基板300的橫截面，而圖6b係描繪一平面圖。基板300係實質類似於以上的基板150。類似於導電層154及156以及貫孔158，導電層304以及導電層306係透過導電貫孔308來電耦接至彼此。基板300係包含一對穿過該基板而被形成的開口310及312，其係分別類似於以上的開口160。在某些實施例中，針對於每一個裝置係使用一個別的PCB單元，而不是針對於一整片的裝置使用一較大的基板300。
穿過基板300的開口310是一類似於開口160的尺寸，以容納一類似的電感或是其它離散的裝置174。開口310係被配置以安裝一將被納入到該SiP模組中的子封裝。在該舉例說明的實施例中，開口312係大於開口310。該些開口可以是任意相關的尺寸以容納針對於一SiP模組所選的特定部件、或是單一開口可被利用於多個構件。
在圖6c中，基板300係被設置在帶320上，該帶320係類似於以上的帶170。如同在以上利用導電層154，離散的裝置162係被安裝到導電層304之上。如同在以上利用開口160，離散的裝置174係被安裝在開口310中。一半導體封裝330係被設置在開口312之內的帶320上。半 導體封裝330係包含被設置在一基板332上的電性構件(例如，半導體晶粒104以及離散的裝置162)之任意所期望的組合。為了製造封裝330，基板332通常是被提供為一片，該片係具有被設置於其上的用於複數個封裝330的構件，其係接著利用密封劑334來加以模製，並且被單粒化為個別的封裝。
半導體封裝330可以事先加以製造，並且和該SiP模組整體分開地加以測試是否為一已知良好的封裝。在某些實施例中，半導體封裝330係包含一待被納入到該SiP模組中的具有功能的系統，例如是一RF模組、顯示模組、或是其它有用的模組。
在其它實施例中，其它的封裝類型係藉由被設置在開口312中而被納入到一SiP模組中。基板332可以被另一種類型的基板所取代，例如是一半導體基板、多層的基板、或是一引線架。封裝330的構件可以藉由焊料凸塊、柱形凸塊、焊料膏、接合線、或是其它適當的互連結構來耦接至該基板。封裝330的某些實施例並不使用一基板，例如是如同在以下的圖8a中所描繪者。任何適當的半導體封裝都可被設置在一適當製作尺寸的開口312之內，以用於納入到該SiP模組中。
在圖6d中，密封劑340係沉積在封裝330、離散的裝置162、以及離散的裝置174之上。密封劑340係類似於以上的密封劑180，並且類似地加以沉積。帶320係被移除，凸塊344係被加上，並且複數個個別的SiP模組350係藉由利用一鋸刀、雷射切割工具、水切割工具、或是其它適當的手段，穿過切割道302而被切割來加以產生。基板332以及基板300都包含類似的導電層306，其係具有被露出用於凸塊接合的接觸墊。基板332及300的導電層306係實質共面的，因為兩者都被設置成接觸帶320以 用於封入。一凸塊接合製程係將凸塊施加到基板332及300兩者。凸塊344是一種可被使用的可行的互連結構。在其它實施例中，柱形凸塊、銅柱、或是其它適當的互連結構係被使用。
圖7是描繪一經單粒化的SiP模組350。SiP模組350係包含一嵌入式半導體封裝330以及在基板300的開口之內的離散的裝置174。SiP模組350的高度係藉由將該些較高的構件330及174設置在基板300的開口之內，而不是在該基板上來加以降低。封裝330以及離散的裝置174係具有高度是大於離散的裝置162的高度。將封裝330以及離散的裝置174設置在基板300的開口之內係降低那些構件的頂端，以容許有一整體較薄的封裝。將某些功能嵌入為一子封裝係藉由容許各種功能的晶粒或模組能夠被施加來增加設計的彈性。具有分開的子封裝的模組亦容許該些模組能夠在納入到SiP模組350中之前先被測試。在某些實施例中，一子封裝係在不亦使得離散的裝置174被內嵌在該基板中之下，被使用在一SiP模組中。
圖8a-8c係描繪用於具有嵌入式封裝的SiP模組的替代的配置。在圖8a中，SiP模組360係使得封裝330被封裝362所取代。封裝362是一藉由在無基板下，將構件嵌入在密封劑334中所形成的封裝。在該些構件上的互連結構(例如，凸塊114以及焊料膏166)係仍然從密封劑334被露出，以用於凸塊344的附接。在一實施例中，構件係被拾放在一黏著帶上，以將該些構件保持在適當的地方以用於封入。在該些構件上的互連結構係在模製期間接觸該帶，使得移除該帶係露出該些互連結構。密封劑340以及基板300係被單粒化以產生個別的封裝362，以用於納入到SiP模組360中。
圖8b係描繪只具有被動構件的SiP模組370。封裝370只包含被動的離散的裝置162，例如是電感器、電容器及電阻器。封裝370的構件可以執行一特定的功能，例如是一帶通濾波器。該些構件可以是離散的被動裝置、或是整合的被動裝置，其係利用在基板332上或是之中的金屬層來加以形成。以上或是以下所論述的任意類型的子封裝都可以在只有被動裝置、只有主動裝置、或是具有主動及被動裝置的一組合之下加以利用。
圖8c係描繪具有複數個在基板382的開口之內的嵌入式封裝的SiP模組380。封裝362係如同在圖8a中地被設置在開口310中。封裝330係和離散的裝置174一起被設置在一加大的開口384中。嵌入式封裝的數量、位置、類型、以及功能並不限於所揭露的實施例，並且可以根據需要而不同地加以配置。
圖9a-9c係描繪用於該些具有嵌入式封裝的SiP模組的屏蔽選項。在圖9a中，SiP模組390係包含一屏蔽層392，其係以一種類似在以上的屏蔽層262的方式來施加的。屏蔽層392係被濺鍍或是電鍍在該整個SiP模組390之上。屏蔽層392係選配地透過導電層304a或導電層306的一部分、以及導電的凸塊344a來耦接至一下面的基板的一接地節點。在其它實施例中，屏蔽層392係耦接至基板332的一接地節點。
圖9b係描繪SiP模組400，其中屏蔽層402係被形成在子封裝330之上。屏蔽層402係以一種類似屏蔽層262及292的方式而被施加，但是其係在該子封裝的層級被施加。屏蔽層402係選配地透過導電層304a來耦接至一接地節點。在具有多個子封裝的裝置中，該些子封裝的每 一個都可包含一屏蔽層、或是只有一部分的子封裝可以具有屏蔽。圖9c係描繪具有在該SiP模組層級的屏蔽層392以及在該子封裝層級的屏蔽層402的一實施例。在某些實施例中，在基板332或300中的導電層304或306係將屏蔽層392或402耦接至一接地節點。
圖10a-10b係描繪將上述的SiP模組納入到一電子裝置中。圖10a係描繪來自圖3的SiP模組196被安裝到一PCB或是其它基板502之上以作為一電子裝置的部分的部分橫截面。凸塊190係被回焊到導電層504之上，以實體附接及電連接SiP模組196至PCB 502。上述的SiP模組的任一者都可以類似地被安裝到PCB 502之上。在其它實施例中，熱壓或是其它適當的附接及連接的方法係被使用。在某些實施例中，一黏著或底膠填充層係在SiP模組196以及PCB 502之間被使用。
半導體晶粒104係透過凸塊114、基板150、以及凸塊190來電耦接至導電層504。離散的裝置162係透過焊料膏166、基板150、以及凸塊190來耦接至導電層504。在某些實施例中，基板150係將半導體晶粒104以及離散的裝置162彼此耦接。在其它實施例中，導電層504係將半導體晶粒104以及離散的裝置162彼此耦接。若對於該電子裝置而言為所要的話，則半導體晶粒104以及離散的裝置162係透過導電層504來耦接至離散的裝置174。
圖10b係描繪包含PCB 502的電子裝置505，其中包含SiP模組196的複數個半導體封裝係被安裝在該PCB的一表面之上。電子裝置505可以根據應用而具有一種類型的半導體封裝、或是多種類型的半導體封裝。
電子裝置505可以是一獨立的系統，其係利用該些半導體封裝以執行一或多個電性功能。或者是，電子裝置505可以是一較大的系統的一子構件。例如，電子裝置505可以是一平板電腦、行動電話、數位相機、通訊系統、或是其它電子裝置的部分。電子裝置505亦可以是被插入到一電腦中的一顯示卡、網路介面卡、或是其它的信號處理卡。該些半導體封裝可包含微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散的主動或被動裝置、或是其它半導體晶粒或電性構件。
在圖10b中，PCB 502係提供一個一般的基板，以用於被安裝在該PCB之上的半導體封裝的結構上的支撐及電互連。導電的信號線路504係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或是其它適當的金屬沉積製程而被形成在PCB 502的一表面之上、或是在PCB 502的層之內。信號線路504係提供用於在該些半導體封裝、所安裝的構件、以及其它外部的系統或構件的每一個之間的電性通訊。線路504亦視需要地提供電源及接地連接至該些半導體封裝的每一個。
在某些實施例中，一種半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於機械式及電性地附接該半導體晶粒至一中間的基板的技術。第二層級的封裝係牽涉到機械式及電性地附接該中間的基板至該PCB 502。在其它實施例中，一種半導體裝置可以只有該第一層級的封裝，其中該晶粒係直接機械式及電性地被安裝至該PCB 502。
為了說明之目的，包含接合導線封裝506及覆晶508的數種類型的第一層級的封裝係被展示在PCB 502上。此外，數種類型的第二層級的封裝，其包含球格陣列(BGA)510、凸塊晶片載體(BCC)512、平台柵格 陣列(LGA)516、多晶片的模組(MCM)518、四邊扁平無引腳封裝(QFN)520、嵌入式晶圓層級球格陣列(eWLB)524、以及晶圓級晶片尺寸封裝(WLCSP)526係和SiP模組196一起被展示安裝在PCB 502。在一實施例中，eWLB 524是一扇出晶圓層級的封裝(Fo-WLP)，並且WLCSP 526是一扇入晶圓層級的封裝(Fi-WLP)。導電線路504係電耦接被設置在基板502上的各種封裝至SiP模組196的半導體晶粒104、離散的裝置162、以及離散的裝置174。
根據系統需求，利用第一及第二層級的封裝類型的任意組合來加以配置的半導體封裝以及其它的電子構件的任意組合可以連接至PCB 502。在某些實施例中，電子裝置505係包含單一附接的半導體封裝，而其它實施例係需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可以將預製的構件納入到電子裝置及系統內。因為該些半導體封裝係包含複雜的功能，所以電子裝置可以利用較不昂貴的構件以及一精簡的製程來加以製造。所產生的裝置是較不可能失效，而且製造起來是較不昂貴的，此係產生較低的成本給消費者。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於那些實施例可以做成修改及調適，而不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇。
104‧‧‧半導體晶粒
112‧‧‧導電層
114‧‧‧凸塊
162‧‧‧離散的裝置
174‧‧‧離散的裝置
300‧‧‧基板
304‧‧‧導電層
306‧‧‧導電層
308‧‧‧導電貫孔
330‧‧‧半導體封裝
332‧‧‧基板
334‧‧‧密封劑
340‧‧‧密封劑
344‧‧‧凸塊
350‧‧‧SiP模組

Claims (15)

  1. 一種製造半導體裝置之方法，其係包括：提供基板；在該基板中形成第一開口；在該基板上設置第一半導體構件；在載體上設置該基板；在該基板的該第一開口中的該載體上設置包括互連結構的第二半導體構件；在該基板、該第一半導體構件以及該第二半導體構件之上沉積密封劑；以及在沉積該密封劑之後，移除該載體以露出該基板和該第二半導體構件的該互連結構。
  2. 如申請專利範圍第1項之方法，其進一步包含：在該基板中形成第二開口；以及在該第二開口中設置第三半導體構件。
  3. 如申請專利範圍第2項之方法，其中該第三半導體構件是半導體封裝。
  4. 如申請專利範圍第3項之方法，其進一步包含在該半導體封裝之上形成屏蔽層。
  5. 如申請專利範圍第1項之方法，其進一步包含在該密封劑之上形成屏蔽層。
  6. 如申請專利範圍第1項之方法，其中從該密封劑的頂表面至該基板的 頂表面的距離係小於該第二半導體構件的高度。
  7. 一種製造半導體裝置之方法，其係包括：提供基板；在該基板之上設置第一半導體構件；相鄰該基板來設置包括互連結構的第二半導體構件；以及在該基板、該第一半導體構件以及該第二半導體構件之上沉積密封劑，其中該第二半導體構件的該互連結構是從該密封劑露出。
  8. 如申請專利範圍第7項之方法，其進一步包含：在該基板中形成開口；以及在該開口中設置該第二半導體構件。
  9. 如申請專利範圍第7項之方法，其進一步包含在該基板的高度之內設置該第二半導體構件。
  10. 如申請專利範圍第9項之方法，其中該第二半導體構件的高度係大於該基板的高度。
  11. 一種半導體裝置，其係包括：基板；第一半導體構件，其係被設置在該基板之上；包括互連結構的第二半導體構件，其係相鄰該基板而被設置，其中該第二半導體構件係延伸至在該基板的頂表面之上的高度；以及密封劑，其係被沉積在該基板、該第一半導體構件以及該第二半導體構件之上，其中該第二半導體構件的該互連結構是從該密封劑露出。
  12. 如申請專利範圍第11項之半導體裝置，其中該第二半導體構件的高 度係大於該第一半導體構件的高度。
  13. 如申請專利範圍第11項之半導體裝置，其進一步包含相鄰該基板而被設置的半導體封裝。
  14. 如申請專利範圍第11項之半導體裝置，其中該第二半導體構件係被設置在該基板的開口之內。
  15. 如申請專利範圍第11項之半導體裝置，其進一步包含相對於該第一半導體構件而被疊層在該基板上的帶，其中該第二半導體構件係被設置在該帶上。
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