TWI719248B - 半導體裝置與形成具有從囊封物延伸出的電性構件端子的系統級封裝的方法 - Google Patents

半導體裝置與形成具有從囊封物延伸出的電性構件端子的系統級封裝的方法 Download PDF

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TWI719248B
TWI719248B TW106129759A TW106129759A TWI719248B TW I719248 B TWI719248 B TW I719248B TW 106129759 A TW106129759 A TW 106129759A TW 106129759 A TW106129759 A TW 106129759A TW I719248 B TWI719248 B TW I719248B
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electrical component
carrier
adhesive layer
semiconductor
encapsulant
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TW106129759A
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TW201826404A (zh
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鄭珍熙
金五漢
尹仁相
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新加坡商星科金朋有限公司
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Abstract

一種半導體裝置係具有一載體，一黏著層係被形成在該載體之上。對準標記係被設置以用於將該電性構件拾放在該載體或是黏著層上。一電性構件係藉由將該電性構件的端子壓入該黏著層中而被設置在該黏著層上。該電性構件可以是一半導體晶粒、離散的構件、電子模組、以及半導體封裝。一引線架係被設置在該黏著層之上。一屏蔽層係被形成在該電性構件之上。一囊封物係被沉積在該電性構件之上。該載體以及黏著層係被移除，使得該電性構件的該些端子係從該囊封物延伸出以用於電互連。一基板係包含複數個導電線路。該半導體裝置係被設置在該基板上，其中該電性構件的該些端子係接觸該些導電線路。

Description

半導體裝置與形成具有從囊封物延伸出的電性構件端子的系統級封裝的方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種半導體裝置以及形成一具有從一囊封物延伸出的電性構件端子的SIP之方法。
半導體裝置係常見於現代的電子產品中。半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、光電的、以及產生用於電視顯示器的視覺影像。半導體裝置係見於通訊、電力轉換、網路、電腦、娛樂、以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
多個半導體晶粒以及離散的電性構件可以整合到一系統級封裝(SIP)模組中，以得到在一小空間內的較高的密度以及擴大的電性功能。該些半導體晶粒以及離散的構件係被安裝到一用於結構的支撐及電互連的模組基板。一囊封物(encapsulant)係被沉積在該些半導體晶粒、離散的 構件、以及模組基板之上。該SIP模組基板係被實際安裝並且電連接至下一層級的集積中的一板。該些半導體晶粒以及離散的構件係透過在下面的模組基板來電互連至該板。
由於該下面的模組基板係變成更薄的，因此一載體通常是所需的，以在該製程期間適當地傳輸該模組基板並且避免損壞任何的構件。安裝該些半導體晶粒以及離散的構件至該模組基板係牽涉到焊料膏印刷、構件附接、回焊、以及其它複雜且昂貴的步驟。該模組基板以及相關的處理係佔有總封裝成本的一相當大的部分。一不具有模組基板的SIP設計將會是較不昂貴而且較容易製造的。
本發明的一特點係提供一種製造一半導體裝置之方法，其係包括：提供一載體；在該載體之上形成一黏著層；藉由將該電性構件的端子壓入該黏著層中以在該黏著層上設置一電性構件；在該電性構件之上沉積一囊封物；以及移除該載體以讓該電性構件的該些端子從該囊封物延伸出，以用於電互連。
本發明的另一特點係提供一種製造一半導體裝置之方法，其係包括：提供一載體；在該載體上設置一電性構件；在該電性構件之上沉積一囊封物；以及移除該載體以讓該電性構件的端子從該囊封物延伸出以用於電互連。
本發明的又一特點係提供一種半導體裝置，其係包括：一載體；一被形成在該載體之上的黏著層；一被設置在該黏著層上的電性構件，其中該電性構件的端子係延伸到該黏著層中；以及一被沉積在該電性構件 之上的囊封物。
100:半導體晶圓
102:基底基板材料
104、104a、104b:半導體晶粒(構件)
106:切割道
108:非主動表面(背表面)
110:主動表面
112:導電層
114、114a、114b:凸塊
118:鋸刀(雷射切割工具)
120:臨時的基板(載體)
122:黏著層
124:表面
128:引線架
129:引線架
130:電性構件
131:對準標記
132、132a、132b:離散的電子構件
134:離散的電子構件
136、136a、136b:電互連端子
138:電互連端子
140:屏蔽層
142:囊封物(模製化合物)
144:系統級封裝(SIP)
150:PCB(基板)
152、152a、152b、152c:導電線路
160:屏蔽層
162:互連接合材料
200:電子裝置
202:印刷電路板(PCB)
204:信號線路
206:接合導線封裝
208:覆晶
210:球格陣列(BGA)
212:凸塊晶片載體(BCC)
216:平台柵格陣列(LGA)
218:多晶片的模組(MCM)
220:四邊扁平無引腳封裝(QFN)
222:四邊扁平封裝
224:內嵌的晶圓層級球格陣列(eWLB)
226:晶圓級晶片尺寸封裝(WLCSP)
F:力
圖1a-1c係描繪一半導體晶圓，其中複數個半導體晶粒係藉由一切割道來加以分開；圖2a-2i係描繪形成一SIP的一製程，其中電性構件的端子係從一囊封物延伸出；圖3係描繪該SIP被安裝到一PCB以用於電互連；圖4係描繪一被形成在該SIP之上的屏蔽層；圖5係描繪一被形成在該引線架之上的互連接合材料、以及從該囊封物延伸出的電性構件的端子；以及圖6係描繪該PCB，其中不同類型的封裝係被安裝到該PCB的一表面。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。如同在此所用的術語"半導體晶粒"係指該些字詞的單數及複數形，並且於是可以指稱單一半導體裝置以及多個半導體裝置兩者。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製 造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每一個晶粒係包含電連接以形成功能電路的主動及被動電性構件。例如是電晶體及二極體的主動電性構件係具有控制電流流動的能力。例如是電容器、電感器及電阻器的被動電性構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒，並且為了結構的支撐、電互連以及環境的隔離來封裝該半導體晶粒。為了單粒化該些半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用導電層、凸塊、柱形凸塊、導電膏、或是引線接合來做成。一囊封物或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電性隔離。該完成的封裝係接著被插入一電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a係展示一具有一種基底基板材料102的半導體晶圓100，例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體材料。複數個半導體晶粒或構件104係被形成在晶圓100上，半導體晶粒104係藉由一非主動的晶粒間的晶圓區域或切割道106來加以分開。切割道106係提供切割區域以將半導體晶圓100單粒化成為個別的半導體晶粒104。在一實施例中，半導體晶圓100係具有一 100-450毫米(mm)的寬度或直徑。
圖1b係展示半導體晶圓100的一部分的橫截面圖。每一個半導體晶粒104係具有一背表面或非主動表面108以及一包含類比或數位電路的主動表面110，該類比或數位電路係被實施為形成在該晶粒內並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。例如，該電路係包含一或多個電晶體、二極體、以及其它電路元件，其係被形成在主動表面110內以實施類比電路或數位電路，其例如是數位信號處理器(DSP)、特殊應用積體電路(ASIC)、記憶體、或是其它的信號處理電路。半導體晶粒104亦可包含例如是電感器、電容器及電阻器之IPD，以用於RF信號處理。
一導電層112係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適當的金屬沉積製程而被形成在主動表面110之上。導電層112可以是一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層112係運作為電連接至在主動表面110上的電路的接觸墊。
一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程而被沉積在導電層112之上。該凸塊材料可以是具有一選配的助熔溶劑的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的附接或是接合製程而被接合到導電層112。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成球或凸塊114。在一實施例中，凸塊114係被形成在一凸塊 下金屬化(UBM)之上，其係具有一潤濕層、阻障層、以及黏著層。凸塊114亦可被壓縮接合或是熱壓接合到導電層112。凸塊114係代表一種類型的可被形成在導電層112之上的互連結構。該互連結構亦可以使用接合線、導電膏、柱形凸塊、微凸塊、或是其它電互連。
在圖1c中，半導體晶圓100係利用一鋸刀或是雷射切割工具118，穿過切割道106而被單粒化成為個別的半導體晶粒104。該些個別的半導體晶粒104可以在單粒化之後加以檢查及電性測試，以用於KGD的識別。
圖2a-2i係描繪一形成一SIP的製程，其中電性構件的端子係從一囊封物延伸出。圖2a係展示臨時的基板或是載體120的橫截面圖，其係包含犧牲基底材料，例如是塑膠、聚合物、鈹氧化物、玻璃、或是其它適當的低成本的剛性材料以用於結構的支撐。在一實施例中，載體120係由具有酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯、以及其它強化纖維或織物的一組合的聚四氟乙烯預浸物(預浸料)、FR-4、FR-1、CEM-1、或是CEM-3的一或多個疊層的層所做成的。一黏著層122係被形成在載體120的表面124之上。黏著層122可以是一矽黏著劑、丙烯酸酯黏著劑、或是聚醯亞胺基膜。引線架128係被設置在載體120上的黏著層122之上。圖2b係展示引線架128是利用黏著層122來附接至載體120。
在圖2c中，電性構件130係利用對準標記的一拾放操作而被設置在載體120上的黏著層122之上，並且接著利用該黏著層來附接至該載體。尤其，電性構件130係利用如同在圖2d中所示的獨特的對準標記131(例如是基準標記)，而被對準到在載體120上的特定位置。對準標記131 係沿著單元及框架輪廓而被指定，以作為該導引框架設計的部分。
圖2e係展示一替代實施例，其中引線架129係被實施為一被設置在載體120周圍的環。引線架129可以是由Cu所做成的。
回到圖2d，每一個電性構件130係利用力F而被壓入黏著層122中，以將電性構件130的電互連至少部分地嵌入到黏著層122中。當載體120及黏著層122係在之後被移除時，構件130的電互連將會從該囊封物延伸出。電性構件130係包含如同從圖1a-1c中的半導體基板100被單粒化的半導體晶粒104，其中主動表面110以及凸塊114係被定向朝向黏著層122。電性構件130進一步包含離散的電子構件132及134(例如是一電感器、電容器、電阻器、二極體、或是功率電晶體)，其中離散的電子構件132的電互連端子136以及離散的電子構件134的電互連端子138係被定向朝向黏著層122。其它半導體或電性構件130可包含一電子模組以及半導體封裝。
圖2f係展示電性構件130被附接至在載體120上的黏著層122，其中凸塊114以及電互連端子136及138係延伸到該黏著層中。在一實施例中，半導體晶粒104a係被安裝到黏著層122，其中凸塊114係至少部分地被嵌入到該黏著層之中。離散的電子構件132a係被安裝到黏著層122，其中電互連端子136係至少部分地被嵌入到該黏著層之中。離散的電子構件132b係被安裝到黏著層122，其中電互連端子136係至少部分地被嵌入到該黏著層之中。半導體晶粒104b係被安裝到黏著層122，其中凸塊114係至少部分地被嵌入到該黏著層之中。離散的電子構件134係被安裝到黏著層122，其中電互連端子138係至少部分地被嵌入到該黏著層之中。
半導體晶粒104以及離散的電子構件132及134可包含易受 EMI、RFI、諧波失真、以及裝置間的干擾影響的IPD。例如，內含在半導體晶粒104以及離散的電子構件132及134之內的IPD係提供高頻應用所需的電性特徵，例如是共振器、高通濾波器、低通濾波器、帶通濾波器、對稱的高Q值的諧振變壓器、以及調諧電容器。為了降低EMI及RFI的影響，如同在圖2g中所示，屏蔽層140可以保形地被施加在電性構件130之上。屏蔽層140可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。或者是，屏蔽層140可以是羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、金屬箔、導電樹脂、碳黑、鋁薄片、以及其它能夠降低EMI、RFI及其它裝置間的干擾的影響的金屬及合成物。屏蔽層140係電連接至一外部的接地點，以降低EMI及RFI在電性構件130上的影響。
在圖2h中，一囊封物或是模製化合物142係利用一壓縮模製、轉移模製、液體囊封物模製、真空疊層、旋轉塗覆、或是其它適當的施用器，而被沉積在電性構件130、引線架128、以及在載體120上的黏著層122之上，以形成SIP 144。在一實施例中，囊封物142係藉由壓縮模製而被沉積以施加垂直的力，其中沿著水平軸是降低的力。壓縮模製係具有在模製期間構件移動的低風險。囊封物142可以是聚合物複合材料，例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。囊封物142是非導電的，提供結構的支撐，並且在環境上保護該半導體裝置免於外部的元素及污染物。尤其，電性構件130係在囊封期間保持穩定的，而且並不移位或者是移動，因為凸塊114以及電互連端子136及138係至少部分地被嵌入到黏著層122之中。至少部分地延伸到黏著層122中的凸塊114以及電互連端子136及138係提供一穩定的錨 點，以在沉積囊封物142時將電性構件130保持在適當的地方。
在圖2i中，臨時的載體120及黏著層122係藉由化學蝕刻、機械式剝離、CMP、機械式研磨、熱烘烤、紫外線(UV)光、雷射掃描、或是濕式剝除來加以移除，此係留下SIP 144。移除載體120及黏著層122係讓凸塊114以及電互連端子136及138從囊封物142延伸出。凸塊114以及電互連端子136及138係提供一像是球格陣列的外部的封裝互連。在圖2a-2i中的形成SIP 144的製程是簡單的、低成本的、而且在無如同在該背景中所敘述的習知基板下加以達成。
圖3是展示SIP 144被安裝到PCB或是基板150，其中在該半導體封裝之內的電性構件130係藉由被形成在PCB 150上的導電線路152電性互連的。尤其，SIP 144的如同藉由在圖2a-2i中所述的製程從囊封物142延伸出的凸塊114以及電互連端子136及138係與導電線路152接觸，以用於相關該封裝的內部及外部的電互連。例如，凸塊114a係與導電線路152a接觸，以用於透過PCB 150的相關SIP 144的外部的互連。凸塊114b係與導電線路152b接觸以用於與端子136a的互連，以用於在不同的電性構件130之間，亦即在半導體晶粒104a以及離散的電子構件132a之間的互連。端子136b係與導電線路152c接觸，以用於透過PCB 150的相關SIP 144的外部的互連。
圖4是描繪一屏蔽層160係被形成在SIP 144的囊封物142以及引線架128之上。屏蔽層160可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。或者是，屏蔽層160可以是羰基鐵、不銹鋼、鎳銀、低碳鋼、矽鐵鋼、金屬箔、導電樹脂、碳黑、鋁薄片、以及其 它能夠降低EMI、RFI、以及其它裝置間的干擾的影響的金屬及合成物。屏蔽層160例如是透過引線架128而電連接至PCB 150上的一外部的接地點，以降低EMI及RFI在電性構件130上的影響。
圖5是描繪一互連接合材料162係被形成在SIP 144的凸塊114以及電互連端子136及138之上，以強化黏著並且提供可靠的互連至PCB 150。該互連接合材料162可以是焊料電鍍、焊料球體附接、或是焊料膏印刷。該互連接合材料162亦可被施加至引線架128，例如是結合圖4的屏蔽層160以將該屏蔽層連接至PCB 150。
圖6是描繪具有一晶片載體基板或是印刷電路板(PCB)202的電子構件200，其中包含SIP 144的複數個半導體封裝係安裝在PCB 202的一表面之上。電子裝置200根據應用而可以具有一種類型的半導體封裝、或是多種類型的半導體封裝。
電子裝置200可以是一獨立的系統，其係利用該些半導體封裝以執行一或多個電性功能。或者是，電子裝置200可以是一較大的系統的一子構件。例如，電子裝置200可以是一平板電腦、行動電話、數位相機、通訊系統、或是其它電子裝置的部分。電子裝置200亦可以是可被插入到一電腦中的一顯示卡、網路介面卡、或是其它的信號處理卡。該些半導體封裝可包含微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散的裝置、或是其它半導體晶粒或電性構件。對於欲被市場所接受的產品而言，小型化以及重量降低是重要的。在半導體裝置之間的距離可被縮減，以達成更高的密度。
在圖6中，PCB 202係提供一個一般的基板，以用於被安裝 在該PCB之上的半導體封裝的結構上的支撐及電互連。導電的信號線路204係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或是其它適當的金屬沉積製程而被形成在PCB 202的一表面之上、或是在PCB 202的層之內。信號線路204係提供用於在該些半導體封裝、所安裝的構件、以及其它外部的系統構件的每一個之間的電性通訊。線路204亦提供電源及接地連接至該些半導體封裝的每一個。
在某些實施例中，一種半導體裝置係具有兩個封裝層級。第一層級的封裝是一種用於機械式及電性地附接該半導體晶粒至一中間的基板的技術。第二層級的封裝係牽涉到機械式及電性地附接該中間的基板至該PCB。在其它實施例中，一種半導體裝置可以只有該第一層級的封裝，其中該晶粒係直接機械式及電性地被安裝至該PCB。為了說明之目的，包含接合導線封裝206及覆晶208的數種類型的第一層級的封裝係被展示在PCB 202上。此外，數種類型的第二層級的封裝，其包含球格陣列(BGA)210、凸塊晶片載體(BCC)212、平台柵格陣列(LGA)216、多晶片的模組(MCM)218、四邊扁平無引腳封裝(QFN)220、四邊扁平封裝222、內嵌的晶圓層級球格陣列(eWLB)224、以及晶圓級晶片尺寸封裝(WLCSP)226係被展示安裝在PCB 202之上。在一實施例中，eWLB 224是一扇出晶圓層級的封裝(Fo-WLP)，並且WLCSP 226是一扇入晶圓層級的封裝(Fi-WLP)。根據系統需求，利用第一及第二層級的封裝類型的任意組合來加以配置的半導體封裝以及其它的電子構件的任意組合可以連接至PCB 202。在某些實施例中，電子裝置200係包含單一附接的半導體封裝，而其它實施例係需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可以將預製的構件 納入到電子裝置及系統內。因為該些半導體封裝係包含複雜的功能，所以電子裝置可以利用較不昂貴的構件以及一精簡的製程來加以製造。所產生的裝置是較不可能失效，而且製造起來是較不昂貴的，此係產生較低的成本給消費者。
儘管本發明的一或多個實施例已經詳細地描述，但是本領域技術人員將會體認到對於那些實施例可以做成修改及調適，而不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇。
104a、104b‧‧‧半導體晶粒(構件)
108‧‧‧非主動表面(背表面)
110‧‧‧主動表面
114、114a、114b‧‧‧凸塊
128‧‧‧引線架
130‧‧‧電性構件
132a、132b‧‧‧離散的電子構件
134‧‧‧離散的電子構件
136、136a、136b‧‧‧電互連端子
138‧‧‧電互連端子
142‧‧‧囊封物(模製化合物)
144‧‧‧系統級封裝(SIP)
150‧‧‧PCB(基板)
152、152a、152b、152c‧‧‧導電線路

Claims (15)

  1. 一種製造半導體裝置之方法，其係包括：提供載體；在該載體之上形成黏著層；在該載體或該黏著層之上設置引線架；藉由將該電性構件的端子壓入該黏著層中以在該引線架內的該黏著層上設置電性構件；在該電性構件和該引線架之上沉積囊封物；以及移除該載體以讓該電性構件的該些端子從該囊封物延伸出，以用於電互連。
  2. 如申請專利範圍第1項之方法，其中該引線架的接觸端子從該囊封物露出。
  3. 如申請專利範圍第1項之方法，其中該電性構件係從由半導體晶粒、離散的構件、電子模組、以及半導體封裝所構成的群組加以選出。
  4. 如申請專利範圍第1項之方法，其進一步包含在該電性構件之上形成屏蔽層。
  5. 一種製造半導體裝置之方法，其係包括：提供載體；在該載體之上設置引線架；在該引線架內的該載體上設置電性構件；在該電性構件和該引線架之上沉積囊封物；以及移除該載體以讓該電性構件的端子從該囊封物延伸出，以用於電互連。
  6. 如請專利範圍第5項之方法，其進一步包含在該載體之上形成黏著層。
  7. 如申請專利範圍第6項之方法，其進一步包含將該電性構件的該些端子壓入該黏著層內。
  8. 如申請專利範圍第5項之方法，其中該引線架的接觸端子從該囊封物露出。
  9. 如申請專利範圍第5項之方法，其中該電性構件係從由半導體晶粒、離散的構件、電子模組、以及半導體封裝所構成的群組加以選出。
  10. 如申請專利範圍第5項之方法，其進一步包含在該電性構件之上形成屏蔽層。
  11. 一種半導體裝置，其係包括：載體；黏著層，其係被形成在該載體之上；引線架，其係被設置在該載體或該黏著層之上；電性構件，其係被設置在該引線架內的該黏著層上，其中該電性構件的端子係延伸到該黏著層中；以及囊封物，其係被沉積在該電性構件之上。
  12. 如申請專利範圍第11項之半導體裝置，其中該引線架的接觸端子從該囊封物露出。
  13. 如申請專利範圍第11項之半導體裝置，其中該電性構件係從由半導體晶粒、離散的構件、電子模組、以及半導體封裝所構成的群組加以選出。
  14. 如申請專利範圍第11項之半導體裝置，其進一步包含被形成在該電 性構件之上的屏蔽層。
  15. 如申請專利範圍第11項之半導體裝置，其進一步包含被設置在該載體或是黏著層上的對準標記。
TW106129759A 2016-08-31 2017-08-31 半導體裝置與形成具有從囊封物延伸出的電性構件端子的系統級封裝的方法 TWI719248B (zh)

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