TWI590399B - 半導體封裝件及其製法與其封裝基板 - Google Patents

半導體封裝件及其製法與其封裝基板 Download PDF

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TWI590399B
TWI590399B TW101111659A TW101111659A TWI590399B TW I590399 B TWI590399 B TW I590399B TW 101111659 A TW101111659 A TW 101111659A TW 101111659 A TW101111659 A TW 101111659A TW I590399 B TWI590399 B TW I590399B
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semiconductor
semiconductor component
package
component
flow guiding
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TW201342551A (zh
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黃惠暖
林畯棠
詹前峰
邱啟新
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矽品精密工業股份有限公司
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Priority to TW101111659A priority Critical patent/TWI590399B/zh
Priority to CN2012101563353A priority patent/CN103367287A/zh
Priority to US13/614,590 priority patent/US20130256915A1/en
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Description

半導體封裝件及其製法與其封裝基板
本發明係關於半導體封裝件及其製法，特別是關於一種提升可靠度之半導體封裝件及其製法與其封裝基板。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。
請參閱第1圖，係為習知半導體封裝件1之剖面示意圖。如第1圖所示，習知半導體封裝件1係包括：一具有相對之第一表面10a與第二表面10b的封裝基板10、一置放於該第一表面10a上之第一半導體元件11、一置放於該第一半導體元件11上之第二半導體元件12以及膠體16a,16b。
所述之封裝基板10之第一表面10a上具有複數導電凸塊100以結合該第一半導體元件11，而該第二表面10b上則具有複數電性接觸墊101以結合銲球17。
所述之第一半導體元件11係具有複數直通矽晶穿孔(Through Silicon Via,TSV)111。
所述之第二半導體元件12係藉由複數導電凸塊120而以覆晶方式結合並電性連接於該第一半導體元件11，且藉由該些直通矽晶穿孔211以電性連接該封裝基板20。
所述之膠體16a,16b係形成於該封裝基板10與該第一半導體元件11之間、及該第二半導體元件12與該第一半導體元件11之間，以包覆該些導電凸塊100,120。其中，設置該些導電凸塊100,120之空間高度(即上、下相鄰元件間之間距x,y)不大，故該膠體16a,16b可分別填入各半導體元件間，亦即以兩次點膠製程包覆該些導電凸塊100,120。
惟，習知半導體封裝件1中，需以兩次點膠製程才能包覆該些導電凸塊100,120，且每次經過點膠後，需再經過烘烤程序予以固化，因而造成產品生產之產能(Unit Per Hour,UPH)下降。
再者，若欲以一次點膠製程完成底膠作業以提高產能，如第1’圖所示，因該第二半導體元件12與該封裝基板10之間的間距L過大，致使膠材16無法由下往上流至該第二半導體元件12與該第一半導體元件11之間(即間距x)，故僅能包覆下方之導電凸塊100，而無法包覆上方之導電凸塊120，致使產品作廢。因此，該膠體16a,16b仍需分別填入各半導體元件底下，亦即仍需兩次點膠製程完成底膠作業，而無法以一次點膠製程完成底膠作業，故無法突破關於提升產能之技術瓶頸。
又，若堆疊之半導體元件之數量越多，將需進行更多次之點膠製程，造成產能更低，致使難以量產化。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種半導體封裝件，係包括：封裝基板，係具有置晶區；複數第一導流塊，係形成於該封裝基板之置晶區之外圍上；第一半導體元件，係置放於該置晶區上；第二半導體元件，係置放於該第一半導體元件上；以及膠體，係形成於該封裝基板與該第二半導體元件之間，以包覆該第一半導體元件及該些第一導流塊。
本發明復提供一種半導體封裝件之製法，係包括：提供一具有置晶區之封裝基板；形成複數第一導流塊於該封裝基板之置晶區之外圍上；置放第一半導體元件於該置晶區上；置放第二半導體元件於該第一半導體元件上；以及形成膠體於該封裝基板與該第二半導體元件之間，以包覆該第一半導體元件及該些第一導流塊。
前述之半導體封裝件及其製法中，該第一導流塊之高度可大於或等於該第一半導體元件之高度。
前述之半導體封裝件及其製法中，該第一半導體元件可以覆晶方式結合於該置晶區上。
前述之半導體封裝件及其製法中，該第一半導體元件可未接觸該些第一導流塊。
前述之半導體封裝件及其製法中，該第二半導體元件之結合側的面積可大於該第一半導體元件之結合側的面積。
前述之半導體封裝件及其製法中，該第二半導體元件可未接觸該些第一導流塊。
前述之半導體封裝件及其製法中，復可包括第三半導體元件與第四半導體元件，係置放於該第一與第二半導體元件之間。例如，該第一半導體元件具有結合區及複數第二導流塊，該些第二導流塊形成於該結合區之外圍，且該第三半導體元件結合於該結合區上，而該第四半導體元件則設於該第二與第三半導體元件之間。又該第四半導體元件之結合側的面積可大於該第三半導體元件之結合側的面積。另外，該膠體復可包覆該些第二導流塊、第三半導體元件及第四半導體元件。
另外，本發明又提供一種封裝基板，係包括：基板本體，係具有置晶區；以及複數第一導流塊，係形成於該置晶區之外圍上。
由上可知，本發明半導體封裝件及其製法，係藉由該些第一導流塊(及第二導流塊)作為毛細現象結構，亦即於填膠製程中，該些第一導流塊(及第二導流塊)會導引該膠體之流向，而使部分膠材流至各半導體元件間，以同時包覆所有覆晶用之導電凸塊，故相較於習知技術，本發明只需一次點膠製程即可包覆所有之導電凸塊，因而有效簡化製程，而可增加產品生產之產能。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2E圖，係為本發明之半導體封裝件2之製法之剖面示意圖。
如第2A圖所示，提供具有一置晶區A之一封裝基板20，封裝基板可以為印刷電路板、增層基板、層壓板、陶瓷基板、矽基板或玻璃基板，且形成複數擋塊第一導流塊25於該封裝基板20之置晶區A之外圍上，而形成複數預銲料200於該封裝基板20之置晶區A內。
於本實施例中，該封裝基板20具有相對之第一表面20a(如圖所示之上表面)與第二表面20b(如圖所示之下表面)，且該置晶區A係定義位於該第一表面20a上，而該第二表面20b則具有複數電性接觸墊201，以結合如電路板之電子裝置(圖略)。
再者，該第一導流塊25不限於金屬材質，可為銲料、電鍍金屬塊、膠體或其他可達成相同功效之材質，例如：係可利用網版印刷、植球、電鍍等方式形成預銲錫材料(pre-solder)以作為該些第一導流塊25與預銲料200，但該些第一導流塊25不作為導電路徑。
又，該些第一導流塊25係為球狀；於其它實施例中，該些第一導流塊25’亦可為柱狀，如第2A’圖所示。
另外，該些第一導流塊25a,25b,25c,25d係可以各種環狀分佈之形式環設於該置晶區A之外圍，如第3A至3D圖所示，並無特別限制。
如第2B圖所示，接續第2A圖之製程，將一第一半導體元件21以覆晶方式結合並電性連接於該些預銲料200。
於本實施例中，該第一導流塊25之高度h大於或等於該第一半導體元件21之高度t，且該第一半導體元件21未接觸該些第一導流塊25。
再者，該第一半導體元件21係為中介片(Interposer)，其具有複數直通矽晶穿孔(Through Silicon Via,TSV)211以電性連接該些預銲料200。
如第2C圖所示，將一第二半導體元件22藉由複數導電凸塊220以覆晶方式結合並電性連接於該第一半導體元件21。
於本實施例中，該第二半導體元件22亦未接觸該些第一導流塊25，且該第二半導體元件22之結合側的面積S大於該第一半導體元件21之結合側的面積W，使該些第一導流塊25位於該第二半導體元件22下方。
再者，該第二半導體元件22可為晶片，其藉由該些導電凸塊220電性連接該些直通矽晶穿孔211以電性連接該封裝基板20。
另外，於其它實施例中，該第一半導體元件21亦可先堆疊於該第二半導體元件22上，再一併置放於該封裝基板20上。
如第2D及2E圖所示，進行一次填膠製程，係形成膠體26於該封裝基板20與該第二半導體元件22之間，以完全包覆該第一半導體元件21、該些預銲料200及該些第一導流塊25，亦即該第一半導體元件21、該些預銲料200及該些第一導流塊25不外露，使該膠體26確實保護該第一半導體元件21、該些預銲料200及該些第一導流塊25，俾完成該半導體封裝件2之製作。
本發明之製法藉由該些第一導流塊25之設計，使該第一導流塊25與第二半導體元件22之間的間距e小於或等於該第二半導體元件22與該第一半導體元件21之間的間距z，以於填膠製程中產生毛細現象，亦即該些第一導流塊25會導引該膠體26之流向，而使部分膠材向上流至該第一半導體元件21與該第二半導體元件22之間，以同時包覆位於下方與上方之該些導電凸塊220與預銲料200，故只需一次點膠製程即可包覆該些導電凸塊220、該第一半導體元件21及該些第一導流塊25，因而有效簡化製程，以增加產品生產之產能(UPH)。
再者，該第一導流塊25與第一半導體元件21之間的距離k不宜過大，如第2D圖所示，以於適當的距離k時，該膠體26才能藉由該些第一導流塊25所產生之毛細現象而流入該第一半導體元件21與該第二半導體元件22之間，以有效包覆上方之導電凸塊220。
於本實施例中，復形成複數銲球27於該封裝基板20之第二表面20b之電性接觸墊201上，以結合一電路板(圖略)。
於另一實施例中，該半導體封裝件2’係可堆疊更多半導體元件。如第2E’圖所示，該第一半導體元件21’具有一結合區B及複數第二導流塊210，該些第二導流塊210係形成於該結合區B之外圍，且將一第三半導體元件23藉由複數導電凸塊230以覆晶方式結合並電性連接於該結合區B。又將一第四半導體元件24藉由複數導電凸塊240以覆晶方式結合並電性連接於該第三半導體元件23，而該第二半導體元件22則以覆晶方式結合並電性連接於該第四半導體元件24。其中，該些第一導流塊25’之高度高於該第四半導體元件24之位置，且該第四半導體元件24之結合側的面積r大於該第三半導體元件23之結合側的面積d，而該膠體26復包覆該些第二導流塊210、導電凸塊230,240、第三半導體元件23及第四半導體元件24。
本發明於堆疊更多半導體元件時，除了該些第一導流塊25’作為毛細現象結構以外，可藉由該些第二導流塊210作為毛細現象結構，以輔助導引膠材之流動方向，因而亦只需一次點膠製程即可包覆所有之導電凸塊220,230,240，故更能凸顯增加產能之效果。
本發明提供一種半導體封裝件2,2’，係包括：具有置晶區A之封裝基板20、形成於該置晶區A外圍之複數第一導流塊25,25’、置放於該置晶區A上之第一半導體元件21、置放於該第一半導體元件21上之第二半導體元件22以及膠體26。
所述之封裝基板20復具有複數預銲料200，其形成於該置晶區A內。
所述之第一導流塊25,25’之高度h大於或等於該第一半導體元件21之高度t。
所述之第一半導體元件21係以覆晶方式結合於該置晶區A上，且該第一半導體元件21並未接觸該些第一導流塊25,25’。
所述之第二半導體元件22係未接觸該些第一導流塊25,25’，且該第二半導體元件22之結合側的面積S大於該第一半導體元件21之結合側的面積W。
所述之膠體26係形成於該封裝基板20與該第二半導體元件22之間，以包覆該第一半導體元件21及該些第一導流塊25,25’。
於另一實施例中，所述之半導體封裝件2’復包括第三半導體元件23與第四半導體元件24，係置放於該第一與第二半導體元件21,22之間。
所述之第一半導體元件21’復具有結合區B及複數第二導流塊210，且該些第二導流塊210形成於該結合區B之外圍。
所述之第三半導體元件23係結合於該結合區B上。
所述之第四半導體元件24係設於該第二與第三半導體元件22,23之間，且該第四半導體元件24之結合側的面積r大於該第三半導體元件23之結合側的面積d，又該第一導流塊25’之高度大於或等於該第四半導體元件24之高度。
所述之膠體26復包覆該些第二導流塊210、第三半導體元件23及第四半導體元件24。
綜上所述，本發明之半導體封裝件及其製法，主要藉由毛細現象結構(即第一導流塊25,25’與第二導流塊210)之設計，以於填膠製程中導引膠體之流向，而可同時包覆各層之導電凸塊，故只需一次點膠製程即可包覆所有導電凸塊，因而有效達到增加產能之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2’．．．半導體封裝件
10,20．．．封裝基板
10a,20a．．．第一表面
10b,20b．．．第二表面
100,120,220,230,240．．．導電凸塊
101,201．．．電性接觸墊
11,21,21’．．．第一半導體元件
111,211．．．直通矽晶穿孔
12,22．．．第二半導體元件
16．．．膠材
16a,16b,26．．．膠體
17,27．．．銲球
200．．．預銲料
210．．．第二導流塊
23．．．第三半導體元件
24．．．第四半導體元件
25,25’,25a,25b,25c,25d．．．第一導流塊
A．．．置晶區
B．．．結合區
h,t．．．高度
L,e,x,y,z．．．間距
k．．．距離
S,W,r,d．．．面積
第1及1’圖係為習知半導體封裝件之剖面示意圖；
第2A至2E圖係為本發明半導體封裝件之製法之剖面示意圖；其中，第2A’圖係為第2A圖之另一實施例，第2E’圖係為第2E圖之另一實施例；以及
第3A至3D圖係為本發明半導體封裝件之不同實施例之上視示意圖。
2．．．半導體封裝件
20．．．封裝基板
200．．．預銲料
201．．．電性接觸墊
21．．．第一半導體元件
22．．．第二半導體元件
220．．．導電凸塊
25．．．第一導流塊
26．．．膠體
27．．．銲球
A．．．置晶區
e．．．間距

Claims (19)

  1. 一種半導體封裝件，係包括：封裝基板，係具有置晶區；複數第一導流塊，係形成於該封裝基板之置晶區之外圍上；第一半導體元件，係置放於該置晶區上；第二半導體元件，係覆晶接置於該第一半導體元件上，且該第二半導體元件並未接觸該些第一導流塊，其中，該第一導流塊與該第二半導體元件之間的間距小於該第二半導體元件與該第一半導體元件之間的間距；以及膠體，係形成於該封裝基板與該第二半導體元件之間，以包覆該第一半導體元件及該些第一導流塊。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一導流塊之高度大於或等於該第一半導體元件之高度。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一半導體元件係以覆晶方式結合於該置晶區上。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一半導體元件並未接觸該些第一導流塊。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該第二半導體元件之結合側的面積大於該第一半導體元件之結合側的面積。
  6. 如申請專利範圍第1項所述之半導體封裝件，復包括 第三半導體元件與第四半導體元件，係置放於該第一與第二半導體元件之間。
  7. 如申請專利範圍第6項所述之半導體封裝件，其中，該第一半導體元件具有結合區及複數第二導流塊，該些第二導流塊形成於該結合區之外圍，且該第三半導體元件結合於該結合區上，而該第四半導體元件則設於該第二與第三半導體元件之間。
  8. 如申請專利範圍第6項所述之半導體封裝件，其中，該第四半導體元件之結合側的面積大於該第三半導體元件之結合側的面積。
  9. 如申請專利範圍第6項所述之半導體封裝件，其中，該膠體復包覆該些第二導流塊、第三半導體元件及第四半導體元件。
  10. 一種半導體封裝件之製法，係包括：提供一具有置晶區之封裝基板，該封裝基板於該置晶區之外圍上具有複數第一導流塊；置放第一半導體元件於該置晶區上；覆晶接置第二半導體元件於該第一半導體元件上，且該第二半導體元件並未接觸該些第一導流塊，其中，該第一導流塊與該第二半導體元件之間的間距小於該第二半導體元件與該第一半導體元件之間的間距；以及形成膠體於該封裝基板與該第二半導體元件之間，以包覆該第一半導體元件及該些第一導流塊。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該第一導流塊之高度大於或等於該第一半導體元件之高度。
  12. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該第一半導體元件係以覆晶方式結合於該置晶區上。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該第一半導體元件並未接觸該些第一導流塊。
  14. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該第二半導體元件之結合側的面積大於該第一半導體元件之結合側的面積。
  15. 如申請專利範圍第10項所述之半導體封裝件之製法，復包括置放第三半導體元件與第四半導體元件於該第一與第二半導體元件之間。
  16. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該第一半導體元件具有結合區及複數第二導流塊，該些第二導流塊形成於該結合區之外圍，且該第三半導體元件結合於該結合區上，而該第四半導體元件則設於該第二與第三半導體元件之間。
  17. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該第四半導體元件之結合側的面積大於該第三半導體元件之結合側的面積。
  18. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該膠體復包覆該些第二導流塊、第三半導體元 件及第四半導體元件。
  19. 一種封裝基板，係包括：基板本體，係具有置晶區；以及複數第一導流塊，係形成於該置晶區之外圍上，以使後續置於該基板本體上的第一半導體元件及覆晶接置於該第一半導體元件上的第二半導體元件不接觸該些第一導流塊，其中，該第一導流塊與該第二半導體元件之間的間距小於該第二半導體元件與該第一半導體元件之間的間距。
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