CN112670195A - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

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Publication number
CN112670195A
CN112670195A CN202010894054.2A CN202010894054A CN112670195A CN 112670195 A CN112670195 A CN 112670195A CN 202010894054 A CN202010894054 A CN 202010894054A CN 112670195 A CN112670195 A CN 112670195A
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China
Prior art keywords
protective layer
semiconductor die
passivation layer
conductive
forming
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CN202010894054.2A
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English (en)
Inventor
林孟良
蔡柏豪
庄博尧
吴逸文
翁得期
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112670195A publication Critical patent/CN112670195A/zh
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Abstract

本公开涉及封装结构及其形成方法，此方法包含设置半导体晶粒于重布线结构的第一表面之上。此方法还包含形成第一保护层以围绕半导体晶粒的一部分。此方法还包含设置装置元件于重布线结构的第二表面之上。重布线结构介于装置元件与半导体晶粒之间。此外，此方法包含形成第二保护层以围绕装置元件的一部分。第二保护层比第一保护层厚，且第二保护层与第一保护层具有不同的热膨胀系数。

Description

封装结构及其形成方法
技术领域
本发明实施例涉及一种封装结构及其形成方法，且特别涉及具有扇出 (fan-out)部件的封装结构及其形成方法。
背景技术
半导体集成电路(integrated circuit，IC)产业已经经历了快速的增长。 半导体制造工艺的持续进步已经导致具有更精细部件和/或更高整合度的半 导体装置。功能密度(即，每单位芯片(chip)面积的互连装置的数量)已 普遍增加，同时特征尺寸(即，可使用制造工艺产生的最小组件)已减小。 这种微缩过程通常可通过提高生产效率和降低相关成本来提供益处。
芯片封装不仅为半导体装置提供免于受到环境污染的保护，而且还为 封装于其中的半导体装置提供连接接口(connection interface)。已经开发出 利用较小面积或较低高度的较小封装结构来封装半导体装置。
已经开发了新的封装技术以进一步提高半导体晶粒(die)的密度和功 能。这些相对新颖的半导体晶粒封装技术面临了些制造挑战。
发明内容
本发明实施例提供封装结构的形成方法，此方法包含设置半导体晶粒 于重布线结构的第一表面之上。此方法还包含形成第一保护层以围绕半导 体晶粒的至少一部分。此方法还包含设置装置元件于重布线结构的第二表 面之上。重布线结构介于装置元件与半导体晶粒之间。此外，此方法也包 含形成第二保护层以围绕装置元件的至少一部分。第二保护层比第一保护 层厚，且第二保护层与第一保护层具有不同的热膨胀系数。
本发明实施例提供封装结构的形成方法，此方法包含设置装置元件于 重布线结构的第一表面之上。此方法也包含形成第一保护层以围绕装置元 件的至少一部分。此方法也包含设置半导体晶粒于重布线结构的第二表面 之上。重布线结构介于装置元件与半导体晶粒之间。此外，此方法也包含 形成第二保护层以围绕半导体晶粒的至少一部分。第二保护层比第一保护 层薄，且第二保护层与第一保护层由不同材料形成。
本发明实施例提供封装结构，此封装结构包含重布线结构。此封装结 构也包含位于重布线结构的相对表面之上的半导体晶粒和装置元件。此封 装结构也包含至少部分围绕半导体晶粒的第一保护层。此外，此封装结构 也包含至少部分围绕装置元件的第二保护层。
附图说明
通过以下的详细描述配合说明书附图，可以更加理解本发明实施例的 内容。需强调的是，根据产业上的标准惯例，许多部件(feature)仅用于说 明目的，并未按照比例绘制。事实上，为了能清楚地讨论，各种部件的尺 寸可能被任意地增加或减少。
图1A-图1R是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。
图2A-图2B是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。
图3A-图3B是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。
图4是根据一些实施例的封装结构的剖面示意图。
图5A-图5E是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。
图6是根据一些实施例的封装结构的剖面示意图。
图7A-图7L是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。
图8A-图8B是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。
图9是根据一些实施例显示形成封装结构的工艺的一个中间阶段的上 视布局示意图。
图10是根据一些实施例的封装结构的剖面示意图。
附图标记说明：
100：承载基板
101：胶带
102：重布线结构
104：绝缘层
105：导电部件
106a：导电部件
106b：导电部件
108：导电部件
110：导电凸块
110S：表面
112：装置元件
114：导电结构
116：半导体晶粒
118：导电部件
120：加强元件
120’：加强元件
122：供应器
124：含有聚合物材料
126：保护层
128：粘着层
130：承载基板
132：能量束
134：焊料元件
136A：装置元件
136B：装置元件
136C：装置元件
138a：电极
138b：电极
140：保护层
142：框架载体
144：焊料元件
145：导电凸块
148：导电垫
146：板子
344：焊料元件
346：导电凸块
520：加强元件
520S：表面
700：承载基板
701：胶带
702：重布线结构
704：绝缘层
706a：导电部件
706b：导电部件
708：导电部件
710：焊料元件
712A：装置元件
712B：装置元件
712C：装置元件
714a：电极
714b：电极
716：保护层
718：粘着层
720：承载基板
722：导电凸块
722S：表面
724：装置元件
726：焊料元件
728：半导体晶粒
730：导电部件
732：加强元件
734：供应器
736聚合物材料
738：保护层
740：焊料元件
742：导电凸块
744：框架载体
h1：厚度
h1’：厚度
h2：厚度
h2’：厚度
h3：厚度
h3’：厚度
W1：宽度
W2：宽度
具体实施方式
以下内容提供了多个不同的实施例或范例，用于实现本发明实施例的 不同部件。组件和配置的具体范例描述如下，以简化本发明实施例。当然， 这些仅仅是范例，并非用以限定本发明实施例。举例来说，叙述中若提及 第一部件形成于第二部件或之上，可能包含形成第一和第二部件直接接触 的实施例，也可能包含额外的部件设置于第一和第二部件之间，使得第一 和第二部件不直接接触的实施例。另外，本发明实施例可能在许多范例中重复元件符号及/或字母。这些重复是为了简化和清楚的目的，他们本身并 非代表所讨论各种实施例及/或配置之间有特定的关系。
此外，此处可能使用空间上的相关用语，例如“在…之下”、“在…下 方”、“下方的”、“在…上方”、“上方的”和其他类似的用语可用于此，以 便描述如图所示的一元件或部件与其他元件或部件之间的关系。此空间上 的相关用语除了包含附图示出的方位外，也包含使用或操作中的装置的不 同方位。当装置被转至其他方位时(旋转90度或其他方位)，则在此所使 用的空间相对描述可同样依旋转后的方位来解读。
在叙述中，用语“大致上(substantially)”，例如“大致上平坦”或“大 致上共平面”等，将被本领域中的通常知识者所理解。在一些实施例中， 大致上将形容词移除。在适用的情况下，用语“大致上”也可包含具有“完 整地(entirely)”、“完全地(completely)”、“所有地(all)”等情况的实施 例。在适用的情况下，用语“大致上”也可涉及90％或更多，例如95％或 更多，尤其是99％或更多，或包含100％的情况。再者，用语“大致平行” 或“大致垂直”被解读为不排除与特定排列的微小偏差，并且可包含，例 如高达10°的偏差。用语“大致上”不排除“完全地”，例如，“大致上不含 (substantially free)”Y的组成，可以是完全地不含Y。
例如“大约(about)”的用语，与特定距离或尺寸连用时，被解读为不 排除与特定距离或尺寸的微小偏差，并且可包含，例如高达10°的偏差。用 语“大约”与数值x的关系可以表示x±5或10％。
本文公开一些实施例。在这些实施例所提及的阶段之前、期间、或之 后可提供额外的步骤。对于不同的实施例，可以置换或删减所述的一些阶 段。可增加额外的部件至封装结构。对于不同的实施例，可以置换或删减 以下所述的一些部件。尽管一些实施例是以特定顺序进行的步骤来讨论， 但这些步骤可以其他符合逻辑的顺序来进行。
本文的实施例可涉及三维(3D)封装或三维集成电路(3D-IC)装置。 也可包含其他部件或工艺。举例而言，可以包含测试结构，以帮助3D封装 或3D-IC装置进行验证测试。可以包含测试结构，例如，形成于重布线 (redistribution)层或基板上的测试垫(testingpad)，其使3D封装或3D-IC 能进行测试、探针(probe)或探针卡(probe card)得以使用等等。可对中 间结构和最终结构进行验证测试。另外，本文公开的结构和方法可与测试 方法(testing methodology)结合使用，这整合识别良好晶粒(good die)的 中间验证，以提高良率并降低成本。
图1A-图1R是根据一些实施例显示形成封装结构的工艺的各种阶段的 剖面示意图。根据一些实施例，如图1A所示，在承载基板100之上形成重 布线结构102。承载基板100可以是玻璃基板、半导体基板、或其他适合基 板。
在一些实施例中，在形成重布线结构102之前，形成胶带(adhesive tape) 101于承载基板100之上。在一些实施例中，胶带101对于能量束照射敏感。 在一些实施例中，胶带101是包含或由光热转换(light-to-heat conversion， LTHC)材料形成的释放层(releaselayer)。举例而言，使用激光照射胶带 101。照射可使重布线结构102与承载基板100分离。
重布线结构102用于绕线(routing)，这使具有扇出(fan-out)部件的 封装结构得以形成。在一些实施例中，重布线结构102包含多个绝缘层104 和多个导电部件，例如导电部件105、106a和106b。导电部件105、106a 和106b被绝缘层104围绕。导电部件105、106a和106b可包含导线 (conductive line)、导孔(conductive via)、及/或导电垫。
重布线结构102也包含用于保持或接收其他元件的导电部件108。在一 些实施例中，导电部件108暴露于绝缘层104的最顶面处，或者自绝缘层 104的最顶面突出。导电部件108可用于保持或接收一或多个半导体晶粒及 /或一或多个无源元件。导电部件108也可用于保持或接收导电部件，例如 导电柱(pillar)、及/或导电凸块(bump)。
绝缘层104可包含或由一或多个聚合物(polymer)材料形成。聚合物 材料可包含聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide， PI)、环氧基树脂(epoxy-based resin)、一或多其他适合聚合物材料、或前 述的组合。在一些实施例中，聚合物材料具有光敏感性。因此，使用光刻 (photolithography)工艺以形成具有期望图案的开口于绝缘层104中。
在一些实施例中，其中一些或全部的绝缘层104可包含或由聚合物材 料以外的介电材料形成。介电材料可以包含氧化硅、碳化硅、氮化硅、氮 氧化硅、一或多个其他适合材料、或前述的组合。
导电部件105、106a、106b和108可包含在水平方向上提供电连接的 导线、以及在垂直方向上提供电连接的导孔。在一些实施例中，一些导孔 彼此堆叠。较高导孔与较低导孔大致对准。在一些实施例中，一些导孔是 错开的导孔。较高导孔与较低导孔不对准。
导电部件105、106a、106b和108可包含或由铜、铝、金、钴、钛、 镍、银、石墨烯、一或多其他适合导电材料、或前述的组合。在一些实施 例中，导电部件105、106a、106b和108包含多个子层。举例而言，导电 部件105、106a、106b和108中的每一个含有多个子层，这些子层包含钛/ 铜(Ti/Cu)、钛/镍/铜(Ti/Ni/Cu)、钛铜钛(Ti/Cu/Ti)、铝/钛/镍/银(Al/Ti/Ni/Ag)、 其他适合子层、或前述的组合。
重布线结构102的形成可涉及多道沉积或涂布(coating)工艺、多道 图案化工艺、及/或多道平坦化工艺。
可使用沉积或涂布工艺，以形成绝缘层及/或导电层。沉积或涂布工艺 可包含旋转涂布(spin-on coating)工艺、电镀(electroplating)工艺、无电 (electroless)工艺、化学气相沉积(chemical vapor deposition，CVD)工艺、 物理气相沉积(physical vapordeposition，PVD)工艺、原子层沉积(atomic layer deposition，ALD)工艺、一或多其他适用工艺、或前述的组合。
可使用图案化工艺，将形成的绝缘层及/或形成的导电层图案化。图案 化工艺可包含光刻工艺、能量束钻孔工艺(例如，激光束钻孔工艺、离子 束钻孔工艺、或电子束钻孔工艺)、蚀刻工艺、机械钻孔工艺、一或多其他 适用工艺、或前述的组合。
可使用平坦化工艺，提供形成的绝缘层及/或形成的导电层具有平坦的 顶面，以利于后续工艺。平坦化工艺可提供机械研磨(mechanical grinding) 工艺、化学机械研磨(chemical mechanical polish，CMP)工艺、干式研磨 工艺、一或多其他适用工艺、或前述的组合。
根据一些实施例，如图1B所示，形成导电凸块110和装置元件112于 一些导电部件108之上。在一些实施例中，导电凸块110是含锡焊料凸块 (tin-containing solderbump)。含锡焊料凸块可进一步包含铜、银、金、铝、 铅、一或多其他适合材料、或前述的组合。在一些其他实施例中，导电凸 块110是无铅的(lead-free)。在一些其他实施例中，导电凸块110是含锡 焊球(solder ball)。
在一些实施例中，通过导电结构114将装置元件112接合至导电部件 108。导电结构114可包含焊料凸块、导电柱、一多其他适合接合结构、或 前述的组合。装置元件112可包含一或多个无源元件，例如电阻器(resistor)、 电容器(capacitor)、电感器(inductor)、一或多其他适合元件、或前述的 组合。在一些其他实施例中，装置元件112包含存储器装置。在一些实施 例中，装置元件112包含电极，电极通过导电结构114接合至重布线结构102的垫区(pad region，即一些导电部件108)。
在一些实施例中，在形成或堆叠导电凸块110和装置元件112之前， 分散助焊材料(flux material)至导电部件108上。在一些实施例中，接着 进行热回流(thermal reflow)步骤，以固定导电凸块110和装置元件112 至重布线结构102。
根据一些实施例，如图1C所示，堆叠半导体晶粒(die)116于重布线 结构102之上。半导体晶粒116可包含应用处理器、电源管理集成电路、 存储器装置、一或多其他适合电路、或前述的组合。在一些实施例中，每 一个装置元件112可以比半导体晶粒116薄。
在一些实施例中，半导体晶粒116通过半导体晶粒116的导电部件118 接合至一些导电部件108上。导电部件118可包含导电柱、焊料元件、一 或多其他适合接合结构、或前述的组合。举例而言，每一个导电部件118 包含金属柱和含锡焊料元件的组合。在一些实施例中，形成底部填充 (underfill)材料以围绕并保护导电部件118和导电结构114。在一些其他 实施例中，未形成底部填充材料。
根据一些实施例，如图1D所示，形成加强(stiffener)元件120于重 布线结构102之上。可使用加强元件120，以在后续形成工艺期间控制及/ 或降低封装结构的翘曲(warpage)。在一些实施例中，加强元件120是围绕 半导体晶粒116和导电凸块110的加强环(stiffener ring)。
图9是根据一些实施例显示形成封装结构的工艺的一个中间阶段的上 视布局示意图。在一些实施例中，图9显示加强元件120与邻近的其他元 件的上视布局示意图。在一些实施例中，加强元件120连续围绕导电凸块 110、装置元件112、以及半导体晶粒116，如图9所示。
加强元件120可包含或由绝缘材料(例如，聚合物材料)、半导体材料、 金属材料、一或多其他适合材料、或前述的组合形成。在一些实施例中， 加强元件120由与模制化合物(molding compound)材料或底部填充材料相 似的聚合物材料形成，例如环氧基树脂(epoxy-based resin)。在一些情况下， 可使用点胶作业(dispensing operation)形成加强元件120。
根据一些实施例，如图1D所示，使用供应器122分散含有聚合物材料 124至重布线结构102上。供应器122可以绕着半导体晶粒116和导电凸块110移动，同时分散含有聚合物材料124。结果，分散的含有聚合物材料124 形成加强元件120。在一些实施例中，加强元件120是围绕半导体晶粒116 和导电凸块110的加强环。
在其他一些实施例中，加强元件120由半导体材料(例如，硅)或金 属材料(例如，铝)形成。在一些实施例中，加强元件120是半导体框架 或金属框架。可使用胶粘(glue)材料，将半导体框架或金属框架贴附至重 布线结构102。
根据一些实施例，如图1E所示，形成保护层126于重布线结构102之 上，以围绕且保护半导体晶粒116。保护层126可进一步覆盖且保护装置元 件112、导电凸块110、以及加强元件120。
在一些实施例中，保护层126包含或由绝缘材料形成，例如模制材料。 模制材料可包含聚合物材料，例如具有一或多个填充物散布于其内的环氧 基树脂。填充物可包含绝缘颗粒，绝缘纤维、一或多其他元件、或前述的 组合。举例而言，填充物包含氧化硅(silica)颗粒、含碳颗粒、含碳纤维、 或前述的组合。
在一些实施例中，导入或射出模制材料(例如，液体模制材料)至重 布线结构102上。在一些实施例中，接着使用热工艺以固化(cure)液体模 制材料，并且将其转变为保护层126。
根据一些实施例，如图1F所示，平坦化保护层126以降低保护层126 的厚度。在一些实施例中，平坦化保护层126以暴露出半导体晶粒116。在 一些实施例中，在平坦化保护层126期间，部分移除导电凸块110的上部。 结果，形成导电凸块110的表面110S，如图1F所示。在一些实施例中，表 面110S是大致平坦的表面。在一些实施例中，表面110S与保护层126的 顶面大致齐平。可使用机械研磨工艺，化学机械研磨(CMP)工艺、干式 研磨工艺、一或多其他适用工艺、或前述的组合，进行保护层126的平坦 化。
如图1F所示，在平坦化工艺之后，保护层126具有厚度h1，而半导体 晶粒116具有厚度h2。厚度h1大致等于厚度h2。
根据一些实施例，如图1G所示，使用粘着层128，将承载基板130贴 附至图1F所示的结构。承载基板130可以是玻璃基板、半导体基板、或其 他适合基板。粘着层128的材料可以是与胶带101不同的材料的胶带。
根据一些实施例，如图1H所示，上下翻转图1G所示的结构，并且以 能量束132照射此结构。能量束132可以是激光、紫外光、或其他适合能 量束。在以能量束132照射之后，胶带101的粘着性可能会被破坏或降低。 如前所述，胶带101与胶带128由不同材料形成。举例而言，粘着层128 由光热转换(LTHC)材料以外的粘着材料形成。粘着层128即使在能量束132照射之后仍可保持粘着。
根据一些实施例，如图1I所示，移除胶带101和承载基板100，以暴 露出重布线结构102。根据一些实施例，之后，部分移除绝缘层104以暴露 出导电部件105，如图1J所示。举例而言，使用平坦化工艺或蚀刻工艺， 移除绝缘层104的最顶层。
根据一些实施例，如图1K所示，形成焊料元件134于导电部件105上。 焊料元件134可以包含或由含锡的焊料材料形成。举例而言，焊料元件134 是焊膏(solder paste)。含锡焊料材料可进一步包含铜、银、金、铝、铅、 一或多其他适合材料、或前述的组合。在一些其他实施例中，焊料元件134 是无铅的。可使用印刷工艺(printing process)、点胶工艺(dispensing process)、 涂敷工艺(application process)、电镀工艺(electroplatingprocess)、无电镀 制工艺(electroless plating process)、一或多其他适用工艺、或前述的组合， 形成焊料元件134。
根据一些实施例，如图1L所示，通过焊料元件134，将装置元件136A、 136B和136C接合至导电元件105。在一些实施例中，装置元件136A、136B 和136C的每一个包含一或多个无源元件，例如电阻器、电容器、电感器、 一或多其他适合元件、或前述的组合。在一些其他实施例中，装置元件136A、 136B和136C中的一个或一些包含存储器装置。在一些实施例中，装置元 件136A、136B和136C的每一个包含电极138a和138b。在一些实施例中， 通过焊料元件134，将装置元件136A、136B和136C的电极138a和138b 接合至重布线结构102的垫区(例如，导电部件105)。
装置元件136A、136B和136C可具有不同厚度。在一些实施例中，装 置元件136A、136B和136C比半导体晶粒116厚。在一些实施例中，半导 体晶粒116比装置元件136A、136B或136C宽。
根据一些实施例，如图1M所示，形成保护层140于重布线结构102 之上，以围绕且覆盖装置元件136A、136B和136C。在一些实施例中，保 护层140与保护层126由不同材料形成。在一些实施例中，保护层140包 含或由绝缘材料形成，例如模制材料。模制材料可包含聚合物材料，例如 具有一或多个填充物散布于其内的环氧基树脂。填充物可包含绝缘颗粒， 绝缘纤维、一或多其他元件、或前述的组合。举例而言，填充物包含氧化 硅颗粒、含碳颗粒、含碳纤维、或前述的组合。
在一些实施例中，导入或射出模制材料(例如，液体模制材料)至重 布线结构102上。在一些实施例中，接着使用热工艺以固化(cure)液体模 制材料，并且将其转变为保护层140。可接着进行平坦化工艺，以提供保护 层140具有大致平坦的顶面。
如图1M所示，保护层140具有厚度h3。在一些实施例中，厚度h3大 于保护层126的厚度h1。由于半导体晶粒116比装置元件136A、136B、136C 薄，比保护层140薄的保护层126足以围绕且保护半导体晶粒116。通过较 薄的保护层126，进一步降低封装结构的总厚度，这达到生产较薄且较小的 封装结构的要求。
在一些实施例中，保护层126和140具有不同的热膨胀系数。在一些 实施例中，保护层126的热膨胀系数比保护层140的热膨胀系数高。具有 较高的热膨胀系数的较薄保护层126可补偿具有较低的热膨胀系数的较厚 保护层140的膨胀。因此，可以降低封装结构在后续制造工艺期间或之后 发生的翘曲。改善封装结构的品质和可靠性。
低于保护层126的玻璃传换温度(glass transition temperature，Tg)时， 保护层126可具有第一热膨胀系数(CET1)。低于保护层126的玻璃传换温 度时，保护层126可具有第二热膨胀系数(CET2)。相似地，低于或高于保 护层140的玻璃传换温度时，保护层140也可分别具有第一热膨胀系数 (CET1’)和第二热膨胀系数(CET2’)。
在一些实施例中，保护层140的第一热膨胀系数(CET1’)对保护层 126的第一热膨胀系数(CET1)的比值(CTE1’/CTE1)范围在约0.8至约 0.95。在一些实施例中，保护层140的第二热膨胀系数(CET2’)对保护层 126的第二热膨胀系数(CET2)的比值(CTE1’/CTE1)范围在约0.1至约0.7。
如前所述，保护层126和保护层140各自可包含散布于基于聚合物材 料的填充物。在一些实施例中，填充物在保护层140中的重量百分比高于 填充物在保护层126中的重量百分比。在一些实施例中，通过调整保护层 126与140内的填充物的数量、尺寸、及/或材料，可微调相应的热膨胀系 数。也可调整基于聚合物材料的链长、官能基、及/或平均分子量来微调相 应的热膨胀系数。
根据一些实施例，如图1N所示，上下翻转如图1M所示的结构，并将 其贴附至框架载体(frame carrier)142。之后，移除承载基板130，以暴露 出粘着层128。
根据一些实施例，如图1O所示，移除粘着层128，以暴露出导电凸块 110的表面110S和保护层126。可使用回蚀刻工艺移除粘着层128。回蚀刻 工艺中使用的蚀刻剂也可蚀刻保护层126，以降低保护层126的厚度。结果， 部分的导电凸块110自保护层126的顶面突出。在一些实施例中，部分的 半导体晶粒116也自保护层126的顶面突出。在一些实施例中，回蚀刻工 艺是干式蚀刻工艺。
如图1O所示，些许薄化保护层126至厚度h1’。半导体晶粒116的厚 度h2比厚度h1’厚。厚度h1’对厚度h2的比值(h1’/h2)可范围在约0.8至约 0.95。
然而，本发明实施例并非限制于此。可对本发明实施例进行许多变化 及/或修改。在一些其他实施例中，用于移除粘着层128的回蚀刻工艺是湿 式蚀刻工艺。在一些实施例中，保护层126大致上未被湿式蚀刻工艺回蚀 刻。在这些情况下，半导体晶粒116可以与保护层126大致上一样厚。在 一些实施例中，半导体晶粒116、保护层126、与导电凸块110的顶面彼此 大致齐平。
根据一些实施例，如图1P所示，形成焊料元件144于导电凸块110之 上，导电凸块110于承载基板130和粘着层128移除之后暴露出来。在一 些实施例中，形成焊料元件144于导电凸块110的表面110S正上方。
焊料元件144可以由含锡焊料材料形成。含锡焊料材料可进一步包含 铜、银、金、铝、铅、一或多其他适合材料、或前述的组合。在一些其他 实施例中，焊料元件144是无铅的。在一些实施例中，使用热回流工艺将 焊料元件144与其下方的导电凸块110回流。结果，形成导电凸块145。
在一些实施例中，每一个导电凸块145具有被保护层126围绕的下部， 如图1P所示。每一个导电凸块145具有自保护层126的顶面突出的上部。 在一些实施例中，导电凸块145的上部的侧壁表面向外弯曲。在一些实施 例中，导电凸块145的上部延伸横跨导电凸块145上部与下部之间的界面 的边缘。在一些实施例中，导电凸块145具有葫芦状(gourd-like)轮廓， 如图1P所示。
之后，使用切割(saw)步骤，将图1P所示的结构切割为彼此分开的 多个封装结构。图1Q显示所得到的封装结构中的一个的剖面示意图，此封 装结构从框架载体142取出。
根据一些实施例，如图1R所示，将封装结构接合至板子146上。可使 用热回流工艺形成导电凸块145与板子146的导电垫148之间的接合。板 子146可以是印刷电路板(printed circuit board)、介层板(interposer board)、 或其他适合基板。
可以对本发明实施例进行许多变化和修改。图2A-图2B是根据一些实 施例显示形成封装结构的工艺的各种阶段的剖面示意图。如图2A所示，与 图1F所示的实施例相似，平坦化保护层126。平坦化工艺降低保护层126 的厚度至厚度h1。平坦化工艺也部分移除导电凸块110。然而，部分的保护 层126留在半导体晶粒116之上。在这些情况下，具有厚度h2’的半导体晶 粒116被保护层126覆盖而未暴露出来。
根据一些实施例，之后，进行与第1G-1Q所述的实施例的相似步骤， 以形成封装结构，如图2B所示。
可以对本发明实施例进行许多变化和修改。图3A-图3B是根据一些实 施例显示形成封装结构的工艺的各种阶段的剖面示意图。
如图3A所示，接收或形成一结构，其与图1O所示的结构相似。根据 一些实施例，之后，将焊料元件344分散或设置于导电凸块110的表面110S 上。焊料元件344的材料可以相同或相似于焊料元件144的材料。每一个 焊料元件344可具有较小体积。如图3A所示，焊料元件344具有宽度W2， 而导电凸块110的表面110S具有宽度W1。在一些实施例中，宽度W1比宽度W2宽。在一些实施例中，焊料元件344是含锡焊膏。通过控制焊膏的分 配量，可相应地微调焊料元件344的尺寸。
根据一些实施例，之后，使用热回流工艺，以回流焊料元件344与导 电凸块110。结果，形成导电凸块346。在这些情况下，导电凸块346具有 球状轮廓。之后，相似于图1Q所述的实施例，使用切割步骤以形成彼此分 开的多个封装结构。图3B显示这些封装结构中的一个的剖面示意图，此封 装结构从框架载体142取出。
在一些实施例中，使用加强元件120，以在制造工艺期间或之后，进一 步降低或控制封装结构的翘曲。然而，本发明实施例不限于此。可以对本 发明实施例进行许多变化和修改。图4是根据一些实施例的封装结构的剖 面示意图。在一些实施例中，不形成加强元件120。
可以对本发明实施例进行许多变化和修改。图5A-图5E是根据一些实 施例显示形成封装结构的工艺的各种阶段的剖面示意图。
如图5A所示，接收或形成一结构，其与图1C所示的结构相似。根据 一些实施例，之后，相似于图1D所示的实施例，形成加强元件520，如图 5B所示。在一些实施例中，不相似于加强元件120，形成加强元件520以 具有较大高度。举例而言，加强元件520的顶端的水平比装置元件112的 顶面高。在一些实施例中，加强元件520围绕半导体晶粒116、导电凸块110、以及装置元件112。
根据一些实施例，如图5C所示，相似于图1E所示的实施例，形成保 护层126以覆盖半导体晶粒116、导电凸块110、以及加强元件520。
根据一些实施例，之后，相似于图1F所示的实施例，平坦化保护层126， 如图5D所示。在平坦化期间，部分移除导电凸块110，以形成表面110S。 也部分移除加强元件520，以形成表面520S。在一些实施中，表面520S是 大致上平坦的。在一些实施例中，表面520S齐平于导电凸块110的表面110S 及/或保护层126的顶面。
根据一些实施例，之后，进行相似于第1G-1Q所示的工艺步骤。结果， 制得封装结构，如图5E所示。
可以对本发明实施例进行许多变化和修改。图6是根据一些实施例的 封装结构的剖面示意图。在一些实施例中，形成保护层140以具有厚度h3’。 厚度h3’大于保护层126的厚度h1’。在一些实施例中，保护层140形成为比 装置元件136A、136B和136C中的一个(或多个)来的薄。举例而言，装 置元件136B比保护层140高。装置元件136B自保护层140的顶面突出， 如图6所示。
可以对本发明实施例进行许多变化和修改。图7A-图7L是根据一些实 施例显示形成封装结构的工艺的各种阶段的剖面示意图。
根据一些实施例，如图7A所示，形成重布线结构702于胶带701上， 胶带701贴附于承载基板700上。相似于图1A所示的重布线结构102，重 布线结构702包含多个绝缘层704以及多个导电部件706a、706b、以及708。 重布线结构702的材料和形成方法可相同或相似于重布线结构102的材料 和形成方法。
根据一些实施例，如图7B所示，形成焊料元件710于暴露出来的导电 部件708之上。焊料元件710的材料和形成方法可相同或相似于图1K所示 的焊料元件134的材料和形成方法。
根据一些实施例，如图7C所示，相似于图1L所示的实施例，堆叠装 置元件712A、712B和712C于重布线结构702之上。装置元件712A、712B 和712C可相似于装置元件136A、136B和136C。装置元件712A、712B 和712C的每一个具有电极714a和714b。可通过焊料元件710，将装置元 件712A、712B和712C接合至导电部件708。
根据一些实施例，如图7D所示，相似于图1M所示的实施例，形成保 护层716。保护层716的材料和形成方法可相同或相似于图1M所示的保护 层140的材料和形成方法。
根据一些实施例，如图7E所示，上下翻转图7D所示的结构，并通过 粘着层718将此结构贴附至承载基板720。之后，移除承载基板700和胶带 701，以暴露出重布线结构702。接着，相似于图1J所示的实施例，部分移 除绝缘层704以暴露出导电部件706a，如图7E所示。
根据一些实施例，如图7F所示，相似于图1B所示的实施例，形成导 电凸块722于一些导电部件706a之上。导电凸块722的材料和形成方法可 相同或相似于图1B所示的导电凸块110的材料和形成方法。通过焊料元件 726，将装置元件724接合至一些导电部件706a上。装置元件724可相似 于装置元件112。
根据一些实施例，如图7G所示，相似于图1C所示的实施例，通过半 导体晶粒728的导电部件730，将半导体晶粒728接合至一些导电部件706a 上。半导体晶粒728可相似于半导体晶粒116。
根据一些实施例，如图7H所示，相似于图1D所示的实施例，形成加 强元件732于重布线结构702之上。加强元件732的材料和形成方法可相 同或相似于图1D所示的加强元件120的材料和形成方法。在一些实施例中， 使用供应器734分散含有聚合物材料736至重布线结构702上，以形成加 强元件732。可替代地，在一些其他实施例中，加强元件732是一个预先形 成的框架，并且可使用胶粘(glue)材料，将加强元件732贴附至重布线结 构702。
根据一些实施例，如图7I所示，形成保护层738以围绕半导体晶粒728。 保护层738的材料和形成方法可相同或相似于图1E所示的保护层126的材 料和形成方法。
在一些实施例中，接着使用平坦化工艺，以提供保护层738具有大致 平坦的顶面。在一些实施例中，在平坦化工艺期间，部分移除导电凸块722。 结果，形成导电凸块722的表面722S。在一些实施例中，表面722S是大致 平坦的。在一些实施例中，表面722S与保护层738的顶面大致齐平。
根据一些实施例，如图7J所示，相似于图3A所示的实施例，形成焊 料元件740于导电凸块722的表面722S。之后，使用热回流工艺，以回流 焊料元件740与导电凸块722。根据一些实施例，结果，形成导电凸块742， 如图7K所示。
在一些实施例中，每一个焊料元件740形成以具有较大体积。在这些 情况下，在热回流工艺之后，每一个所得到的导电凸块742可具有相似于 图1P所示的实施例的葫芦状轮廓。
根据一些实施例，如图7L所示，上下翻转图7K所示的结构，并且将 此结构贴附至框架载体744上。之后，移除粘着层718和承载基板720，以 暴露出保护层716。之后，可使用切割工艺，以形成彼此分开的多个封装结 构。可接着将这些封装结构接合至其他元件，例如印刷电路板或介层板。
可以对本发明实施例进行许多变化和修改。图8A-图8B是根据一些实 施例显示形成封装结构的工艺的各种阶段的剖面示意图。
如图8A所示，接收或形成一结构，此结构与图7I所示的结构相似。 然而，平坦化保护层738，以暴露出并且部分移除导电凸块722，但未暴露 出半导体晶粒728。在这些情况下，保护层738覆盖半导体晶粒728。
根据一些实施例，之后，进行相似于图7J-图7L所示的工艺步骤。如 此，得到图8B所示的结构。之后，可使用切割工艺，以形成彼此分开的多 个封装结构。可接着将这些封装结构接合至其他元件，例如印刷电路板或 介层板。
可以对本发明实施例进行许多变化和修改。图10是根据一些实施例的 封装结构的剖面示意图。在一些实施例中，形成加强元件120于重布线结 构102放置半导体晶粒116的表面上。在一些实施例中，可形成另一个加 强元件120’于重布线结构102的相对的另一表面上。加强元件120’的材料 与形成方法可相同或相似于加强元件120’的材料与形成方法。可形成加强 元件120’在设置装置元件136A、136B和136C之后，且在形成保护层140 之前。可以对本发明实施例进行许多变化和修改。在一些其他实施例中， 形成加强元件120’，并且不形成加强元件120。
本发明实施例形成封装结构，此封装结构具有不对称的保护层位于重 布线结构的相对表面。其中一个保护层是较薄的，且用于保护较薄的元件， 例如半导体晶粒。另一个保护层是较厚的，且用于保护较厚的元件，例如 具有无源元件的表面安装装置(surfacemounted device)。通过使用较薄的 保护层，可降低封装结构的总厚度。将较薄的保护层设计为具有比较厚的 保护层高的热膨胀系数。具有较高热膨胀系数的较薄的保护层可补偿具有 较低热膨胀系数的较厚的保护层的膨胀。因此，可以降低封装结构在后续 制造工艺期间或之后发生的翘曲。显著改善封装结构的品质和可靠性。
根据一些实施例，提供封装结构的形成方法。此方法包含设置半导体 晶粒于重布线结构的第一表面之上。此方法还包含形成第一保护层以围绕 半导体晶粒的至少一部分。此方法还包含设置装置元件于重布线结构的第 二表面之上。重布线结构介于装置元件与半导体晶粒之间。此外，此方法 还包含形成第二保护层以围绕装置元件的至少一部分。第二保护层比第一 保护层厚，且第二保护层与第一保护层具有不同的热膨胀系数。在一些实施例中，第一保护层的热膨胀系数比第二保护层的热膨胀系数高。在一些 实施例中，此方法还包含在形成第一保护层之前，形成导电凸块于第一表 面之上。在一些实施例中，第一保护层覆盖导电凸块和半导体晶粒，此方 法还包含平坦化第一保护层以暴露出半导体晶粒。在一些实施例中，在平 坦化第一保护层期间，部分移除导电凸块。在一些实施例中，此方法还包 含回蚀刻第一保护层，使得导电凸块的一部分自第一保护层的一顶面突出。 在一些实施例中，此方法还包含在形成第二保护层之后，形成焊料元件于 导电凸块正上方。在一些实施例中，此方法还包含在形成第一保护层之前， 形成加强环于重布线结构的第一表面之上。在一些实施例中，加强环围绕 半导体晶粒和导电凸块。在一些实施例中，此方法还包含在形成第一保护 层之前，设置无源元件于重布线结构的第一表面之上。无源元件比半导体 晶粒薄，且装置元件比半导体晶粒厚。
根据一些实施例，提供封装结构的形成方法。此方法包含设置装置元 件于重布线结构的第一表面之上。此方法也包含形成第一保护层以围绕装 置元件的至少一部分。此方法也包含设置半导体晶粒于重布线结构的第二 表面之上。重布线结构介于装置元件与半导体晶粒之间。此外，此方法也 包含形成第二保护层以围绕半导体晶粒的至少一部分。第二保护层比第一 保护层薄，且第二保护层与第一保护层由不同材料形成。在一些实施例中， 第二保护层的热膨胀系数比第一保护层的热膨胀系数高。在一些实施例中， 此方法也包含在设置半导体晶粒之前，形成导电凸块于重布线结构的第二 表面之上。在一些实施例中，此方法也包含在形成第二保护层之前，形成 加强环于第二表面之上，以围绕半导体晶粒和导电凸块。在一些实施例中， 第二保护层围绕导电凸块的侧壁且未覆盖导电凸块的顶面，且此方法也包 含形成焊料元件于导电凸块的顶面上。
根据一些实施例，提供封装结构。此封装结构包含重布线结构。此封 装结构也包含位于重布线结构的相对表面之上的半导体晶粒和装置元件。 此封装结构也包含至少部分围绕半导体晶粒的第一保护层。此外，此封装 结构也包含至少部分围绕装置元件的第二保护层。第二保护层比第一保护 层厚，且第二保护层与第一保护层具有不同的热膨胀系数。在一些实施例 中，装置元件比半导体晶粒厚。在一些实施例中，此封装结构也包含位于重布线结构之上的导电凸块。第一保护层围绕导电凸块的下部。在一些实 施例中，导电凸块的上部自第一保护层的顶面突出，且导电凸块的上部具 有向外弯曲的侧壁表面。在一些实施例中，第一保护层的热膨胀系数比第 二保护层的热膨胀系数高。
以上概述数个实施例的部件，以便在本发明所属技术领域中技术人员 可以更加理解本发明实施例的观点。在本发明所属技术领域中技术人员应 理解，他们能轻易地以本发明实施例为基础，设计或修改其他工艺和结构， 以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域 中技术人员也应理解，此类等效的结构并无悖离本发明的精神与范围，且 他们能在不违背本发明的精神和范围下，做各式各样的改变、取代和替换。 因此，本发明的保护范围当视权利要求所界定为准。

Claims (10)

1.一种封装结构的形成方法，包括：
设置一半导体晶粒于一重布线结构的一第一表面之上；
形成一第一保护层以围绕该半导体晶粒的至少一部分；
设置一装置元件于该重布线结构的一第二表面之上，其中该重布线结构介于该装置元件与该半导体晶粒之间；以及
形成一第二保护层以围绕该装置元件的至少一部分，其中该第二保护层比该第一保护层厚，且该第二保护层与该第一保护层具有不同的热膨胀系数。
2.如权利要求1所述的封装结构的形成方法，其中该第一保护层的热膨胀系数比该第二保护层的热膨胀系数高。
3.如权利要求1所述的封装结构的形成方法，还包括：在形成该第一保护层之前，形成一导电凸块于该第一表面之上。
4.如权利要求3所述的封装结构的形成方法，其中该第一保护层覆盖该导电凸块和该半导体晶粒，且该方法还包括：
平坦化该第一保护层以暴露出该半导体晶粒。
5.如权利要求4所述的封装结构的形成方法，其中在平坦化该第一保护层期间，部分移除该导电凸块。
6.如权利要求3所述的封装结构的形成方法，还包括：在形成该第一保护层之前，形成一加强环于该重布线结构的该第一表面之上。
7.一种封装结构的形成方法，包括：
设置一装置元件于一重布线结构的一第一表面之上；
形成一第一保护层以围绕该装置元件的至少一部分；
设置一半导体晶粒于该重布线结构的一第二表面之上，其中该重布线结构介于该装置元件与该半导体晶粒之间；以及
形成一第二保护层以围绕该半导体晶粒的至少一部分，其中该第二保护层比该第一保护层薄，且该第二保护层与该第一保护层由不同材料形成。
8.一种封装结构，包括：
一重布线结构；
一半导体晶粒和一装置元件，位于该重布线结构的相对表面之上；
一第一保护层，至少部分围绕该半导体晶粒；以及
一第二保护层，至少部分围绕该装置元件，其中该第二保护层比该第一保护层厚，且该第二保护层与该第一保护层具有不同的热膨胀系数。
9.如权利要求8所述的封装结构，其中该装置元件比该半导体晶粒厚。
10.如权利要求8所述的封装结构，还包括：一导电凸块，位于该重布线结构之上，其中该第一保护层围绕该导电凸块的一下部。
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