CN106206488B - 内建散热座的散热增益型面朝面半导体组体及制作方法 - Google Patents

内建散热座的散热增益型面朝面半导体组体及制作方法 Download PDF

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CN106206488B
CN106206488B CN201610365386.5A CN201610365386A CN106206488B CN 106206488 B CN106206488 B CN 106206488B CN 201610365386 A CN201610365386 A CN 201610365386A CN 106206488 B CN106206488 B CN 106206488B
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semiconductor element
circuit
routing circuit
layer
secondary route
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CN106206488A (zh
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林文强
王家忠
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Yuqiao Semiconductor Co Ltd
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Yuqiao Semiconductor Co Ltd
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Abstract

本发明提出一种面朝面半导体组体。第一及第二半导体元件面朝面地接置于第一路由电路的两相反侧上，并通过第一路由电路电性连接至互连板。该互连板具有散热座及第二路由电路，该散热座可提供第二半导体元件散热的途径，而形成于散热座上的第二路由电路则电性耦接至第一路由电路。由此，第一路由电路可对第一及第二半导体元件提供初级的扇出路由，而第二路由电路则对第一路由电路提供进一步的扇出线路结构。

Description

内建散热座的散热增益型面朝面半导体组体及制作方法
技术领域
本发明涉及一种面朝面半导体组体及其制作方法，尤指一种将半导体元件面朝面地接置于第一路由电路上的面朝面半导体组体，其中半导体元件还可通过第一路由电路而电性连接至散热座上的第二路由电路。
背景技术
多媒体装置的市场趋势倾向于更迅速且更薄型化的设计需求。其中一种方法是以面朝面(face-to-face)方式以互连两芯片，俾使两芯片间具有最短的路由距离。由于迭置的芯片间可直接相互传输，以降低延迟，故可大幅改善组体的信号完整度，并节省额外的耗能。因此，面朝面半导体组体可展现三维集成电路堆叠(3D IC stacking)几乎所有的优点，且无需于堆叠芯片中形成成本高昂的硅穿孔(Through-Silicon Via)。如美国专利申请案号2014/0210107即揭露了具有面朝面设置结构的堆叠式芯片组体。然，由于其底部芯片未受到保护，且底部芯片的厚度又必须比用于外部连接的焊球薄，故该组体可靠度不佳且无法实际应用上。美国专利案号8,008,121、8,519,537及8,558,395则揭露各种具有中介层的组体结构，其将中介层设于面朝面设置的芯片间。虽然其无需于堆叠芯片中形成硅穿孔(TSV)，但中介层中用于提供芯片间电性路由的硅穿孔会导致工艺复杂、生产良率低及高成本。此外，由于半导体元件易于高操作温度下发生效能劣化现象，因此若面朝面的堆叠式芯片未进行适当散热，则会使元件的热环境变差，导致操作时可能出现立即失效的问题。
为了上述理由及以下所述的其他理由，目前亟需发展一种具新式的面朝面半导体组体，以达到高封装密度、较佳信号完整度及高散热性的要求。
发明内容
本发明的主要目的是提供一种面朝面半导体组体，其将顶部半导体元件及底部半导体元件面朝面地接置于第一扇出路由电路上，以缩短顶部半导体元件与底部半导体元件间的互连长度，便可确保组体具有优异的电性效能。
本发明的另一目的是提供一种面朝面半导体组体，其中第一扇出路由电路与第二扇出路由电路电性耦接，以提供阶段式的扇出路由，俾可改善生产良率并降低成本。
本发明的再一目的是提供一种面朝面半导体组体，其将底部半导体元件贴附至散热座，使底部半导体元件所产生的热可通过散热座有效散逸，俾可改善组体的热效能。
依据上述及其他目的，本发明提供一种将次组体电性耦接至散热增益型构件的散热增益型面朝面半导体组体，其中该次组体包含一第一半导体元件、一平衡层及一第一路由电路，而该散热增益型构件包含一第二半导体元件、一散热座及设置于散热座上的一第二路由电路。在一较佳实施例中，第一半导体元件电性耦接至第一路由电路的顶侧，且平衡层侧向环绕第一半导体元件；第二半导体元件通过第一凸块电性耦接至第一路由电路的底侧，因而通过该第一路由电路而与第一半导体元件相互面朝面地电性连接；第一路由电路对第一半导体元件及第二半导体元件提供初级的扇出路由及最短的互连距离；第二路由电路形成于散热座上，并通过侧向环绕第二半导体元件的第二凸块电性耦接至第一路由电路的底侧，以提供进一步的扇出路由；且散热座与第二半导体元件热性导通，使散热座对第二路由电路所侧向环绕的第二半导体元件提供散热途径。
在另一实施方式中，本发明提供一种内建散热座的散热增益型面朝面半导体组体，其包括：一次组体，其包含一第一半导体元件、一平衡层及具有第一表面及相对第二表面的一第一路由电路，其中第一半导体元件是由第一路由电路的第一表面电性耦接至第一路由电路，且具有面向第一路由电路的有源面及相对于有源面的非有源面，而平衡层侧向环绕第一半导体元件并覆盖第一路由电路的第一表面；以及一散热增益型构件，其电性耦接至该次组体，并包含一第二半导体元件、一散热座及设置于该散热座上的一第二路由电路，其中(i)第二半导体元件贴附至散热座，并被第二路由电路侧向环绕，且通过一系列第一凸块电性耦接至第一路由电路，(ii)第二路由电路通过一系列第二凸块电性耦接至第一路由电路，且(iii)第一凸块及第二凸块设置于第一路由电路的第二表面。
在又一实施方式中，本发明提供一种内建散热座的散热增益型面朝面半导体组体制作方法，其包括下述步骤：提供一次组体，其包含：(i)提供一第一路由电路，其可拆分式地接置于一牺牲载板上，(ii)将一第一半导体元件由该第一路由电路的一第一表面电性耦接至该第一路由电路，其中第一半导体元件具有面向第一路由电路的有源面及相对于有源面的非有源面，(iii)提供一平衡层，其侧向环绕该第一半导体元件且覆盖该第一路由电路的第一表面，及(iv)移除该牺牲载板，以显露该第一路由电路的相对于该第一表面的一第二表面；通过一系列第一凸块，将一第二半导体元件由该第一路由电路的第二表面，电性耦接至次组体的第一路由电路；提供一互连板，其包含一散热座及设置于散热座上的一第二路由电路；以及通过一系列第二凸块，将互连板的第二路由电路由第一路由电路的第二表面电性耦接至次组体的第一路由电路，并使第二半导体元件贴附至散热座。
在再一实施方式中，本发明提供另一种内建散热座的散热增益型面朝面半导体组体制作方法，其包括下述步骤：提供一次组体，其包含：(i)将一第一半导体元件贴附至一加强层，其中该第一半导体元件具有面向加强层的非有源面及相对于非有源面的有源面，(ii)提供一平衡层，其侧向环绕该第一半导体元件，及(iii)形成一第一路由电路于该第一半导体元件的有源面及该平衡层上，并使第一半导体元件由第一路由电路的一第一表面电性耦接至该第一路由电路；通过一系列第一凸块，将一第二半导体元件由该第一路由电路的相对于该第一表面的一第二表面，电性耦接至次组体的第一路由电路；提供一互连板，其包含一散热座及设置于散热座上的一第二路由电路；以及通过一系列第二凸块，将互连板的第二路由电路由第一路由电路的第二表面电性耦接至次组体的第一路由电路，并使第二半导体元件贴附至散热座。
除非特别描述或必须依序发生的步骤，上述步骤的顺序并无限制于以上所列，且可根据所需设计而变化或重新安排。
本发明的面朝面半导体组体及其制作方法具有许多优点。举例来说，将第一及第二半导体元件面朝面地电性耦接至第一路由电路的两相反侧，可提供第一及第二半导体元件间的最短互连距离。将次组体电性耦接至散热座上的第二路由电路是特别具有优势的，其原因在于，散热座可提供第二半导体元件散热的途径，同时可作为次组体及第二路由电路的支撑平台。此外，通过两阶段步骤以形成第一及第二半导体元件的布线基板是有利的，其原因在于，第一路由电路可提供初级的扇出路由，而第二路由电路可提供进一步的扇出路由，且当需形成多层路由电路时，此作法可避免发生严重的弯曲问题。
附图说明
参考随附图式，本发明可通过下述较佳实施例的详细叙述更加清楚明了，其中：
图1及2分别为本发明第一实施方式中，在加强层上形成定位件的剖视图及底部立体示意图；
图3及4分别为本发明第一实施方式中，将第一半导体元件贴附至图1及2加强层上的剖视图及底部立体示意图；
图5为本发明第一实施方式中，图3结构上形成平衡层的剖视图；
图6为本发明第一实施方式中，自图5结构移除平衡层底部区域的剖视图；
图7及8分别为本发明第一实施方式中，图6结构上形成初级导线的剖视图及底部立体示意图；
图9为本发明第一实施方式中，图8结构上形成第一介电层及第一盲孔的剖视图；
图10及11分别为本发明第一实施方式中，图9结构上形成第一导线的剖视图及底部立体示意图；
图12及13分别为本发明第一实施方式中，第二半导体元件通过第一凸块电性耦接至图10及11结构上的剖视图及底部立体示意图；
图14为本发明第一实施方式中，图12结构上设置第二凸块的剖视图；
图15及16分别为本发明第一实施方式中，图14的面板尺寸结构切割后的剖视图及底部立体示意图；
图17为本发明第一实施方式中，对应于图15切离单元的结构剖视图；
图18为本发明第一实施方式中，图6结构上形成第一介电层及第一盲孔的剖视图；
图19为本发明第一实施方式中，图18结构上形成第一导线的剖视图；
图20为本发明第一实施方式中，第二半导体元件电性耦接至图19结构上的剖视图；
图21为本发明第一实施方式中，图20的面板尺寸结构切割后的剖视图；
图22及23分别为本发明第一实施方式中，散热座的剖视图及顶部立体示意图；
图24为本发明第一实施方式中，图22结构上形成第二介电层、金属层及第二盲孔的剖视图；
图25为本发明第一实施方式中，图24结构上形成第二导线的剖视图；
图26为本发明第一实施方式中，图25结构上形成第三介电层、金属层及第三盲孔的剖视图；
图27及28分别为本发明第一实施方式中，图26结构上形成第三导线，以制作完成互连板的剖视图及顶部立体示意图；
图29及30分别为本发明第一实施方式中，图17结构接置于图27及28互连板上，以制作完成面朝面半导体组体的剖视图及顶部立体示意图；
图31为本发明第二实施方式中，在牺牲载板上沉积初级导线的剖视图；
图32为本发明第二实施方式中，图31结构上形成第一介电层及第一盲孔的剖视图；
图33为本发明第二实施方式中，图32结构上形成第一导线的剖视图；
图34为本发明第二实施方式中，将第一半导体元件电性耦接至图33结构上的剖视图；
图35为本发明第二实施方式中，图34结构上形成平衡层的剖视图；
图36为本发明第二实施方式中，自图35结构移除平衡层顶部区域的剖视图；
图37为本发明第二实施方式中，图36结构上设置加强层的剖视图；
图38及39分别为本发明第二实施方式中，自图37结构移除牺牲载板的剖视图及底部立体示意图；
图40及41分别为本发明第二实施方式中，将第二半导体元件电性耦接至图38及39结构的剖视图及底部立体示意图；
图42为本发明第二实施方式中，图40的面板尺寸结构切割后的剖视图；
图43为本发明第二实施方式中，对应于图42切离单元的结构剖视图；
图44为本发明第二实施方式中，图43结构接置于图27互连板上，以制作完成面朝面半导体组体的剖视图；
图45为本发明第三实施方式中，第一路由电路于牺牲载板上的剖视图；
图46为本发明第三实施方式中，图45结构上设置第一半导体元件及加强层的剖视图；
图47为本发明第三实施方式中，图46结构上形成平衡层的剖视图；
图48为本发明第三实施方式中，自图47结构移除平衡层顶部区域及牺牲载板的剖视图；
图49为本发明第三实施方式中，第二半导体元件电性耦接至图48结构的剖视图；
图50为本发明第三实施方式中，图49的面板尺寸结构切割后的剖视图；
图51为本发明第三实施方式中，对应于图50切离单元的结构剖视图；
图52为本发明第三实施方式中，图51结构接置于图27互连板上，以制作完成面朝面半导体组体的剖视图；
图53为本发明第四实施方式中，散热座上形成第二介电层的剖视图；
图54为本发明第四实施方式中，图53结构上形成第二导线的剖视图；
图55为本发明第四实施方式中，图54结构上形成第三介电层及第三盲孔的剖视图；
图56为本发明第四实施方式中，图55结构上形成第三导线，以制作完成互连板的剖视图；以及
图57为本发明第四实施方式中，面朝面构件接置于图56连板上，以制作完成面朝面半导体组体的剖视图。
【附图标记说明】
次组体 10
面朝面半导体组体 100、200、300、400
第一表面 101
第二表面 103
加强层 11
定位件 12
第一半导体元件 13
有源面 131、171
非有源面 133、173
凸块 135、185
黏着剂 14
平衡层 15
第一路由电路 16
初级导线 161
第一介电层 163
第一盲孔 164
第一导线 165
第一导电盲孔 167
第一接触垫 168
第二接触垫 169
第二半导体元件 17
第一凸块 181
第二凸块 183
牺牲载板 19
支撑板1 91
阻挡层 192
互连板 20
凹穴 205
散热座 21
凹陷部 211
金属层 22、23
第二介电层 223
第二盲孔 224
第二导线 225
第二导电盲孔 227
第三介电层 233
第三盲孔 234
第三导线 235
第三导电盲孔 237
第一端子垫 238
第二端子垫 239
第二路由电路 24
导热材料 29
切割线 L
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
在下文中，将提供一实施例以详细说明本发明的实施方式。本发明的优点以及功效将通过本发明下述内容而更为显著。在此说明所附的图式是简化过且作为例示用。图式中所示的元件数量、形状及尺寸可依据实际情况而进行修改，且元件的配置可能更为复杂。本发明中也可进行其他方面的实践或应用，且不偏离本发明所定义的精神及范畴的条件下，可进行各种变化以及调整。
[实施例1]
图1-30为本发明第一实施方式中，一种面朝面半导体组体的制作方法图，其包括一加强层11、一定位件12、一第一半导体元件13、一平衡层15、一第一路由电路16、一第二半导体元件17、一散热座21及一第二路由电路24。
图1及2分别为加强层11上具有多组定位件12的剖视图及底部立体示意图。加强层11一般是由导热材料所制成，如金属、合金、硅、陶瓷或石墨，但亦可使用其他非导热材料，如模制材料(mold compound)。加强层11的厚度范围较佳为0.1至1.0毫米。定位件12由加强层11的底部表面凸起，其厚度可为5至200微米。在本实施方式中，该加强层11具有0.5毫米厚度，而定位件12具有50微米厚度。定位件12可经由各种技术进行图案化沉积而形成，如电镀、无电电镀、蒸镀、溅镀或其组合，并同时使用光刻技术，或者通过薄膜沉积而后进行金属图案化步骤而形成。金属图案化技术包括湿蚀刻、电化学蚀刻、激光辅助蚀刻及其组合，并使用蚀刻光罩(图未示)，以定义出定位件12。就具导电性的加强层11而言，一般是通过金属(如铜)电镀方式沉积，以形成定位件12。或者，若是使用非导电的加强层11，则可使用阻焊(solder mask)或光阻材料以形成定位件12。如图2所示，每组定位件12由多个凸柱所组成，并与随后设置的半导体元件的四角相符。然而，定位件的图案不限于此，其可具有防止随后设置的半导体元件发生不必要位移的其他各种图案。举例来说，定位件12可由一连续或不连续的凸条所组成，并与随后设置的半导体元件的四侧边、两对角、或四角相符。或者，定位件12可侧向延伸至加强层11的外围边缘，并具有与随后设置的半导体元件外围边缘相符的内周围边缘。
图3及4分别为第一半导体元件13通过黏着剂14贴附至加强层11的剖视图及底部立体示意图。就具导热性的加强层11而言，该黏着剂14通常为导热黏着剂。每一第一半导体元件13(绘制成裸芯片)包含有凸块135，所述凸块135位于第一半导体元件13的有源面131，且第一半导体元件13以非有源面133朝向加强层11的方式贴附至加强层11。每组定位件12侧向对准并靠近每一第一半导体元件13的外围边缘。定位件12可控制元件置放的准确度。定位件12朝向下方向延伸超过第一半导体元件13的非有源面133，并且位于第一半导体元件13的四角外，同时在侧面方向上侧向对准第一半导体元件13的四角。由于定位件12侧向靠近且符合第一半导体元件13的四角，故其可避免第一半导体元件13在黏着剂固化时发生任何不必要的位移。定位件12与第一半导体元件13间的间隙较佳在约5至50微米的范围内。此外，第一半导体元件13的贴附步骤亦可不使用定位件12。
图5为第一半导体元件13、定位件12及加强层11上形成平衡层15的剖视图，其中该平衡层15可通过如树脂-玻璃层压、树脂-玻璃涂布或模制(molding)方式形成。该平衡层15由下方覆盖第一半导体元件13、定位件12及加强层11，并环绕、同形披覆且覆盖第一半导体元件13的侧壁，同时自第一半导体元件13侧向延伸至结构的外围边缘。
图6为第一半导体元件13的凸块135自下方显露的剖视图。可通过研磨、抛光或激光方式，将平衡层15的下部区域移除。在部分移除平衡层15后，平衡层15的底部表面与凸块135的外表面呈实质上共平面。
图7及8分别为通过金属沉积及金属图案化工艺形成初级导线161的剖视图及底部立体示意图。初级导线161通常由铜制成，其侧向延伸于平衡层15上，且电性耦接至第一半导体元件13的凸块135。
初级导线161可通过各种技术沉积为单层或多层，如电镀、无电电镀、蒸镀、溅镀或其组合。举例来说，首先通过将该结构浸入活化剂溶液中，使平衡层15与无电镀铜产生触媒反应，接着以无电电镀方式被覆一薄铜层作为晶种层，然后以电镀方式将所需厚度的第二铜层形成于晶种层上。或者，在晶种层上沉积电镀铜层前，该晶种层可通过溅镀方式形成如钛/铜的晶种层薄膜。一旦达到所需的厚度，即可使用各种技术图案化被覆层，以形成初级导线161，其包括湿蚀刻、电化学蚀刻、激光辅助蚀刻及其组合，并使用蚀刻光罩(图未示)，以定义出初级导线161。因此，初级导线161可提供X及Y方向的水平信号路由，以作为第一半导体元件13的电性连接。
图9为具有第一介电层163及第一盲孔164的剖视图，其中第一介电层163位于平衡层15及初级导线161上，而第一盲孔164在第一介电层163中。第一介电层163一般可通过层压或涂布方式沉积而成，其接触平衡层15及初级导线161，并由下方覆盖且侧向延伸于平衡层15及初级导线161上。第一介电层163通常具有50微米的厚度，且可由环氧树脂、玻璃环氧树脂、聚酰亚胺、或其类似物所制成。在沉积第一介电层163后，可通过各种技术形成第一盲孔164，其包括激光钻孔、等离子体蚀刻、及光刻技术，且通常具有50微米的直径。可使用脉冲激光提高激光钻孔效能。或者，可使用扫描激光束，并搭配金属光罩。第一盲孔164延伸穿过第一介电层163，并对准初级导线161的选定部分。
图10及11分别为第一介电层163上形成第一导线165的剖视图及底部立体示意图，其中第一导线165通过金属沉积及金属图案化工艺形成。第一导线165自初级导线161朝下延伸，并填满第一盲孔164，以形成直接接触初级导线161的第一导电盲孔167，同时侧向延伸于第一介电层163上。如图11所示，第一导线165包括有第一接触垫168及第二接触垫169。第二接触垫169的垫尺寸及垫间距大于第一接触垫168的垫尺寸及垫间距。因此，第一接触垫168可提供另一半导体元件连接用的电性接点，而第二接触垫169可提供连接下一级互连结构的电性接点。
此阶段已完成次组体10的制作，其包括一加强层11、定位件12、第一半导体元件13、一平衡层15及一第一路由电路16。在此图中，第一路由电路16包括初级导线161、第一介电层163及第一导线165。
图12及13分别为第二半导体元件17电性耦接至第一路由电路16的剖视图及底部立体示意图。所述第二半导体元件17(绘制为裸芯片)的有源面171面向第一路由电路16，并可通过热压、回焊、或热超音波接合技术，将第二半导体元件17经由第一凸块181电性耦接至第一导线165的第一接触垫168。
图14为第一路由电路16上设置第二凸块183的剖视图。第二凸块183接置于第一导线165的第二接触垫169上，其高度大于第一凸块181的高度，但小于第一凸块181与第二半导体元件17的相加高度。
图15及16分别为将图14的面板尺寸结构切割成个别单件的剖视图及底部立体示意图。如图所示，沿着切割线“L”，将面板尺寸结构单离成个别的单件，其中每一单件将第二半导体元件17电性耦接至具有切割后尺寸的次组体10。
图17为具有第二半导体元件17及次组体10的个别单件剖视图，其中该次组体10包括一加强层11、一定位件12、一第一半导体元件13、一平衡层15及一第一路由电路16。在此图中，该第一路由电路16为一多层增层电路，其包含有侧向延伸超过第一半导体元件13及第二半导体元件17外围边缘的初级导线161及第一导线165。第一半导体元件13由第一路由电路16的第一表面101电性耦接至第一路由电路16，并被加强层11及平衡层15所包覆。第二半导体元件17由第一路由电路16的第二表面103电性耦接至第一路由电路16，并通过第一路由电路16而面朝面地电性连接至第一半导体元件13。
图18-21为第二半导体元件17电性耦接至次组体10的另一制作方法剖视图。
图18为提供第一介电层163并形成第一盲孔164的剖视图，其中第一介电层163层压/涂布于第一半导体元件13及平衡层15上，而第一盲孔164形成于第一介电层163中。第一介电层163接触第一半导体元件13的凸块135及平衡层15，并由下方覆盖且侧向延伸于第一半导体元件13的凸块135及平衡层15上。第一盲孔164延伸穿过第一介电层163，并对准第一半导体元件13的凸块135。
图19为通过金属沉积及金属图案化工艺于第一介电层163上形成第一导线165的剖视图。第一导线165自第一半导体元件13的凸块135朝下延伸，并填满第一盲孔164，以形成直接接触凸块135的第一导电盲孔167，同时侧向延伸于第一介电层163上。
图20为第二半导体元件17电性耦接至第一路由电路16的剖视图。第二半导体元件17通过第一凸块181而电性耦接至第一导线165。
图21为将图20的面板尺寸结构切割成个别单件的剖视图。如图所示，沿着切割线“L”，将面板尺寸结构单离成具有第一半导体组件17及次组体10的个别单件。
图22及23分别为散热座21的剖视图及顶部立体示意图。该散热座21可由任何具有高导热率的材料制成，如铜、铝、不锈钢、硅、陶瓷、石墨或其他金属或合金材料，并形成有一凹陷部211。该散热座21的厚度范围可为0.5至2.0毫米。在此实施方式中，该散热座21的厚度为1.0毫米。
图24为具有第二介电层223/金属层22及第二盲孔224的剖视图，其中第二介电层223及金属层22由上方层压/涂布于散热座21凹陷部211外的区域，而第二盲孔224在第二介电层223/金属层22中。第二介电层223接触散热座21及金属层22，并夹置于散热座21与金属层22之间。第二介电层223可由环氧树脂、玻璃环氧树脂、聚酰亚胺、或其类似物所制成，且通常具有50微米的厚度。金属层22则通常为具有25微米厚度的铜层。第二盲孔224延伸穿过金属层22及第二介电层223，以由上方显露散热座21的选定部分。如第一盲孔164所述，第二盲孔224亦可通过各种技术形成，如激光钻孔、等离子体蚀刻、及光刻技术，且通常具有50微米的直径。
参考图25，通过金属沉积及金属图案化工艺，在第二介电层223上形成第二导线225。第二导线225自散热座21朝上延伸，并填满第二盲孔224，以形成直接接触散热座21的第二导电盲孔227，同时侧向延伸于第二介电层223上。
图26为具有第三介电层233/金属层23及第三盲孔234的剖视图，其中第三介电层233及金属层23由上方层压/涂布于第二介电层223/第二导线225上，而第三盲孔234于第三介电层233/金属层23中。第三介电层233接触第二介电层223、第二导线225及金属层23，并夹置于第二介电层223与金属层23之间及第二导线225与金属层23之间。第三介电层233可由环氧树脂、玻璃环氧树脂、聚酰亚胺、或其类似物所制成，且通常具有50微米的厚度。金属层23则通常为具有25微米厚度的铜层。第三盲孔234延伸穿过金属层23及第三介电层233，以由上方显露第二导线225的选定部分。如第一盲孔164及第二盲孔224所述，第三盲孔234亦可通过各种技术形成，如激光钻孔、等离子体蚀刻、及光刻技术，且通常具有50微米的直径。
图27及28分别为第三介电层233上形成第三导线235的剖视图及顶部立体示意图，其中第三导线235通过金属沉积及金属图案化工艺形成。第三导线235自第二导线225朝上延伸，并填满第三盲孔234，以形成直接接触第二导线225的第三导电盲孔237，同时侧向延伸于第三介电层233上。如图28所示，第三导线235包括有第一端子垫238及第二端子垫239。第一端子垫238的垫尺寸及垫间距大于第一半导体元件13及第二半导体元件17的垫尺寸及垫间距，并与第一路由电路16的第二接触垫169相符。第二端子垫239的垫尺寸及垫间距大于第一端子垫238的垫尺寸及垫间距，并与下一级互连结构(如印刷电路板)相符。
此阶段已完成互连板20的制作，其具有一凹穴205并包含有一散热座21及一第二路由电路24。在此图中，该第二路由电路24多层增层电路，其包括一第二介电层223、第二导线225、一第三介电层233及第三导线235，且电性耦接至散热座21，以作为接地连接。该凹穴205延伸穿过第二路由电路24，以由上方显露散热座21的一选定部分。
图29及30分别为图17结构接置于图27互连板20上的剖视图及顶部立体示意图。将第二半导体元件17插入互连板20的凹穴205中，并通过导热材料29(通常为导热黏着剂)，将第二半导体元件17的非有源面173贴附至互连板20的散热座21。通过与第二接触垫169及第一端子垫238接触的第二凸块183，使互连板20的第二路由电路24电性耦接至次组体10的第一路由电路16。因此，第一凸块181与第二半导体元件17的相加高度接近于凹穴205深度加上第二凸块183高度的总和。
据此，如图29及30所示，已完成的面朝面半导体组体100包括有一次组体10及将第二半导体元件17热性导通至互连板20的散热增益型构件，其中该次组体10包括一加强层11、一定位件12、一第一半导体元件13、一平衡层15及一第一路由电路16，而该互连板20包括一散热座21及一第二路由电路24。
第一半导体元件13贴附至加强层11，且定位件12位于其非有源面133周围，并与第一半导体元件13的四角相符。第一路由电路16电性耦接至第一半导体元件13，并侧向延伸超过第一半导体元件13的外围边缘，同时侧向延伸于平衡层15上，且平衡层15侧向环绕第一半导体元件13。第二半导体元件17通过第一路由电路16及与第一路由电路16接触的第一凸块181，而与第一半导体元件13以面朝面的方式相互电性连接。如此一来，第一路由电路16可提供第一半导体元件13与第二半导体元件17间的最短互连距离，并对第一半导体元件13及第二半导体元件17提供第一级的扇出路由。第二路由电路24包括有侧向延伸超过第一路由电路16外围边缘的第二导线225及第三导线235，并通过第二凸块183电性耦接至第一路由电路16，以对第一路由电路16提供第二级的扇出路由。因此，第二路由电路24通过第一凸块181、第一路由电路16及第二凸块183，电性连接至第二半导体元件17。散热座21不仅可作为第二路由电路24沉积于上的平台，其亦可对第二半导体元件17提供散热途径。
[实施例2]
图31-44为本发明第二实施方式的面朝面半导体组体制作方法图，其形成另一方式的次组体。
为了简要说明的目的，上述实施例1中任何可作相同应用的叙述皆并于此，且无须再重复相同叙述。
图31为牺牲载板19上形成初级导线161的剖视图，其中初级导线161通过金属沉积及金属图案化工艺形成。在此图中，该牺牲载板19为单层结构。该牺牲载板19通常由铜、铝、铁、镍、锡、不锈钢、硅或其他金属或合金制成，但亦可使用任何其他导电或非导电材料制成。在本实施方式中，该牺牲载板19由含铁材料所制成。
图32为具有第一介电层163及第一盲孔164的剖视图，其中第一介电层163层压/涂布于牺牲载板19及初级导线161上，而第一盲孔164在第一介电层163中。第一介电层163接触牺牲载板19及初级导线161，并由上方覆盖且侧向延伸于牺牲载板19及初级导线161上。第一盲孔164延伸穿过第一介电层163，并对准初级导线161的选定部分。
图33为第一介电层163上形成第一导线165的剖视图，其中第一导线165通过金属沉积及金属图案化工艺形成。第一导线165自初级导线161朝上延伸，并填满第一盲孔164，以形成直接接触初级导线161的第一导电盲孔167，同时侧向延伸于第一介电层163上。
此阶段已完成于牺牲载板19上形成第一路由电路16的工艺。在此图中，第一路由电路16包括初级导线161、第一介电层163及第一导线165，并在其相对的第一表面101及第二表面103处提供电性接点。
图34为第一半导体元件13由第一路由电路16的第一表面101电性耦接至第一路由电路16的剖视图。所述第一半导体元件13的有源面131面向第一路由电路16，并可通过热压、回焊、或热超音波接合技术，将第一半导体元件13经由凸块185电性耦接至第一路由电路16。
图35为第一半导体元件13及第一路由电路16上形成平衡层15的剖视图。该平衡层15由上方覆盖第一半导体元件13及第一路由电路16，且环绕、同形披覆并覆盖第一半导体元件13的侧壁。
图36为移除平衡层15上部区域后的剖视图。由此，第一半导体元件13的非有源面133由上方显露，并与平衡层15的顶部表面呈实质上共平面。
图37为加强层11贴附至第一半导体元件13上的剖视图。加强层11通过黏着剂14，贴附于第一半导体元件13的非有源面133及平衡层15的顶部表面上。
图38及39分别为移除牺牲载板19后的剖视图及底部立体示意图，其显露第一路由电路16的第二表面103。牺牲载板19可通过各种方式移除，包括使用酸性溶液(如氯化铁、硫酸铜溶液)或碱性溶液(如氨溶液)的湿蚀刻、电化学蚀刻、或在机械方式(如钻孔或端铣)后再进行化学蚀刻。在此实施方式中，由含铁材料所制成的牺牲载板19可通过化学蚀刻溶液移除，其中化学蚀刻溶液于铜与铁间具有选择性，以避免移除牺牲载板19时导致铜形成的初级导线161遭蚀刻。如图39所示，初级导线161包括有第一接触垫168及第二接触垫169。第二接触垫169的垫尺寸及垫间距大于第一接触垫168的垫尺寸及垫间距。因此，第一接触垫168可提供另一半导体元件连接用的电性接点，而第二接触垫169可提供连接下一级互连结构的电性接点。
此阶段已完成次组体10的制作，其包括一加强层11、第一半导体元件13、一平衡层15及一第一路由电路16。
图40及41分别为第二半导体元件17由第一路由电路16的第二表面103电性耦接至第一路由电路16的剖视图及底部立体示意图。所述第二半导体元件17的有源面171面向第一路由电路16，并通过第一凸块181电性耦接至初级导线161的第一接触垫168。
图42为图40的面板尺寸结构切割成个别单件的剖视图。如图所示，沿着切割线“L”，将面板尺寸结构单离成个别的单件，其中每一单件将第二半导体元件17电性耦接至具有切割后尺寸的次组体10。
图43为具有第二半导体元件17及个别次组体10的个别单件剖视图，其中该次组体10包括一加强层11、一第一半导体元件13、一平衡层15及一第一路由电路16。第一半导体元件13及第二半导体元件17以相互面朝面的方式，分别接置于第一路由电路16的相对第一表面101及第二表面103。第一路由电路16可提供第一半导体元件13与第二半导体元件17间的最短互连距离，并对第一半导体元件13及第二半导体元件17提供第一级的扇出路由。
图44为图43结构接置于图27互连板20上的剖视图。将第二半导体元件17插入互连板20的凹穴205中，并通过导热材料29(通常为导热黏着剂)，将第二半导体元件17的非有源面173贴附至互连板20的散热座21。通过与第二接触垫169及第一端子垫238接触的第二凸块183，使互连板20的第二路由电路24电性耦接至次组体10的第一路由电路16。
据此，如图44所示，已完成的面朝面半导体组体200包括一加强层11、一第一半导体元件13、一平衡层15、一第一路由电路16、一第二半导体元件17及一互连板20。
第一半导体元件13及第二半导体元件17通过覆晶接合方式，面朝面地分别接置于第一路由电路16的相对第一表面101及第二表面103。第一路由电路16不仅提供第一半导体元件13与第二半导体元件17间的最短互连距离，其亦对第一半导体元件13及第二半导体元件17提供初级的扇出路由。平衡层15覆盖第一半导体元件13的侧壁及第一路由电路16的第一表面101。加强层11贴附至第一半导体元件13及平衡层15，并提供机械支撑力，以避免次组体10发生弯翘情况。在使用具高导热率的加强层11的实施方式中，该加强层11还可对第一半导体元件13提供散热。互连板20具有一凹穴205，以容置第二半导体元件17，且包括有一散热座21及一第二路由电路24，该散热座21与第二半导体元件17热性导通，而该第二路由电路24由第一路由电路16的第二表面103电性耦接至第一路由电路16。第二路由电路24可提供进一步的扇出路由/互连，以放大第一路由电路16的垫尺寸及垫间距，俾可与下一级组体相符。
[实施例3]
图45-52为本发明第三实施方式的面朝面半导体组体制作方法图，其形成另一实施方式的次组体。
为了简要说明的目的，上述实施例中任何可作相同应用的叙述皆并于此，且无须再重复相同叙述。
图45为第一路由电路16可拆分地接置于牺牲载板19上的剖视图。在此图中，该牺牲载板19为双层结构，其包括一支撑板191及沉积于支撑板191上的一阻挡层192。该第一路由电路16与图33所示结构相同，并形成于阻挡层192上。阻挡层192可具有0.001至0.1毫米的厚度，且可为一金属层，其中该金属层可在化学移除支撑板191时抵抗化学蚀刻，并可在不影响初级导线161下移除该金属层。举例说明，当支撑板191及初级导线161由铜制成时，该阻挡层192可由锡或镍制成。此外，除了金属材料外，阻挡层192亦可为一介电层，如可剥式积层膜(peelable laminate film)。在此实施例中，支撑板191为铜板，且阻挡层192为厚度5微米的镍层。
图46为第一半导体元件13电性耦接至第一路由电路16且加强层11贴附至第一半导体元件13上的剖视图。第一半导体元件13通过凸块185电性耦接至第一路由电路16。加强层11通过黏着剂14贴附于第一半导体元件13上。
图47为加强层11及第一路由电路16上形成平衡层15的剖视图。该平衡层15由上方覆盖加强层11及第一路由电路16，且环绕、同形披覆并覆盖第一半导体元件13及加强层11的侧壁。
图48为移除平衡层15上部区域及牺牲载板19后的剖视图。加强层11由上方显露，并与平衡层15在顶部表面处呈实质上共平面。在此，可通过碱性蚀刻溶液来移除由铜制成的支撑板191，接着，可通过酸性蚀刻溶液来移除由镍制成的阻挡层192，以由下方显露第一路由电路16。在阻挡层192为可剥式积层膜(peelable laminate film)的另一实施方式中，该阻挡层192可通过机械剥离或等离子体灰化(plasma ashing)方式来移除。
此阶段已完成次组体10的制作，其包括加强层11、第一半导体元件13、一平衡层15及一第一路由电路16。
图49为第二半导体元件17电性耦接至第一路由电路16的剖视图。第二半导体元件17通过第一凸块181而电性耦接至初级导线161的第一接触垫168。
图50为将图49的面板尺寸结构切割成个别单件的剖视图。如图所示，沿着切割线“L”，将面板尺寸结构单离成个别的单件，其中每一单件将第二半导体元件17电性耦接至具有切割后尺寸的次组体10。
图51为具有第二半导体元件17及次组体10的个别单件剖视图，其中该次组体10包括一加强层11、一第一半导体元件13、一平衡层15及一第一路由电路16。第一半导体元件13及第二半导体元件17面朝面地分别接置于第一路由电路16的相对第一表面101及第二表面103。第一路由电路16提供第一半导体元件13与第二半导体元件17间的最短互连距离，且对第一半导体元件13及第二半导体元件17提供第一级的扇出路由。
图52为图51结构接置于图27互连板20上的剖视图。将第二半导体元件17插入互连板20的凹穴205中，并通过导热材料29(通常为导热黏着剂)，将第二半导体元件17的非有源面173贴附至互连板20的散热座21。通过与初级导线161及第三导线235接触的第二凸块183，使互连板20的第二路由电路24电性耦接至次组体10的第一路由电路16。
据此，如图52所示，已完成的面朝面半导体组体300包括一次组体10、一第二半导体元件17及一互连板20。该第二半导体元件17及该互连板20电性耦接至该次组体10，且互连板20侧向延伸超过次组体10的外围边缘。
次组体10包括一加强层11、一第一半导体元件13、一平衡层15及一第一路由电路16。第一半导体元件13及第二半导体元件17通过覆晶接合方式，面朝面地分别接置于第一路由电路16的相对第一表面101及第二表面103。加强层11贴附至第一半导体元件13上。平衡层15侧向环绕加强层11与第一半导体元件13的侧壁，且覆盖第一路由电路16的第一表面101。互连板20具有一凹穴205，且包含有一散热座24及一第二路由电路24。第二半导体元件17位于凹穴205中，并与散热座21热性导通。第二路由电路24通过第一路由电路16电性连接至第一半导体元件13及第二半导体元件17。
[实施例4]
图53-57为本发明第四实施方式的面朝面半导体组体制作方法图，其包括有另一实施方式的次组体。
为了简要说明的目的，上述实施例中任何可作相同应用的叙述皆并于此，且无须再重复相同叙述。
图53为第二介电层223层压/涂布于散热座21上的剖视图。第二介电层223由上方接触且覆盖散热座21的一选定部分。
图54为通过金属沉积及金属图案化工艺于第二介电层223上形成第二导线225的剖视图。第二导线225侧向延伸于第二介电层223上。
图55为具有第三介电层233及第三盲孔234的剖视图，其中第三介电层233层压/涂布于第二介电层223/第二导线225上，而第三盲孔234于第三介电层233中。第三介电层233由上方接触并覆盖第二介电层223/第二导线225。第三盲孔234延伸穿过第三介电层233，以由上方显露第二导线225的选定部分。
图56为第三介电层233上形成第三导线235的剖视图，其中第三导线235通过金属沉积及金属图案化工艺形成。第三导线235自第二导线225朝上延伸，并填满第三盲孔234，以形成直接接触第二导线225的第三导电盲孔237，同时侧向延伸于第三介电层233上。
此阶段已完成互连板20的制作，其具有一凹穴205并包含有一散热座21及一第二路由电路24。该凹穴205延伸穿过第二路由电路24，并可容置电性耦接至次组体10的第二半导体元件17。于此图中，该第二路由电路24多层增层电路，其包括一第二介电层223、第二导线225、一第三介电层233及第三导线235。
图57为一面朝面构件接置于图56互连板20上的剖视图。该面朝面构件可通过移除图35中的牺牲载板19并将面板尺寸结构切割成个别单件而获得。将第二半导体元件17插入互连板20的凹穴205中，并通过导热材料29(通常为导热黏着剂)，将第二半导体元件17的非有源面173贴附至互连板20的散热座21。通过与初级导线161及第三导线235接触的第二凸块183，使互连板20的第二路由电路24电性耦接至次组体10的第一路由电路16。
据此，如图57所示，已完成的面朝面半导体组体400包括一第一半导体元件13、一平衡层15、一第一路由电路16、一第二半导体元件17、一散热座21及一第二路由电路24。
第一路由电路16可对第一半导体元件13及第二半导体元件17提供初级扇出路由及最短互连距离。平衡层15包覆第一半导体元件13，并对第一半导体元件13及第一路由电路16提供高模数抗弯平台。散热座21提供第二半导体元件17散热的途径，并同时对次组体10及第二路由电路24提供另一高模数抗弯平台。第二路由电路24侧向延伸超过第一路由电路16的外围边缘，并电性耦接至第一路由电路16，以提供进一步的扇出路由。
上述半导体组体仅为说明范例，本发明尚可通过其他多种实施例实现。此外，上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用。接置于互连板上的次组体可包括多个第一半导体元件且可电性耦接至多个第二半导体元件，而第二半导体元件可独自使用一凹穴，或与其他晶第二半导体元件共享一凹穴。举例来说，一凹穴可容纳单一第二半导体元件，且互连板可包括排列成阵列形状的多个凹穴以容纳多个第二半导体元件。或者，单一凹穴内能放置数个第二半导体元件。同样地，次组体可独自使用一互连板，或与其他次组体共享一互连板。例如，可将单一次组体电性连接至互连板。或者，将数个次组体耦接至一互连板。举例来说，可将四枚排列成2x2阵列的次组体耦接至一互连板，并且该互连板的第二路由电路可包括额外的端子垫，以接收额外次组体接垫。
如上述实施方式所示，本发明建构出一种独特的面朝面半导体组体，其包括一第一半导体元件、一平衡层、一第一路由电路、一第二半导体元件、一选择性加强层及一互连板，且该互连板具有一散热座及位于该散热座上的一第二路由电路。为方便下文描述，在此将第一路由电路第一表面所面向的方向定义为第一方向，而第一路由电路第二表面所面向的方向定义为第二方向。
第一及第二半导体元件通过两者间的第一路由电路，以面朝面的方式相互电性连接。第一及第二半导体元件可为已封装或未封装的芯片。举例来说，第一及第二半导体元件可为裸芯片，或是晶圆级封装晶粒等。于一较佳实施方式中，可通过下述步骤制成将第一半导体元件电性耦接至第一路由电路的次组体：将第一半导体元件由第一路由电路的第一表面电性耦接至该第一路由电路，其中第一路由电路可拆分式地接置于一牺牲载板上；提供一平衡层于第一路由电路的第一表面上；以及移除牺牲载板，以显露第一路由电路的第二表面。在此，可利用现有覆晶接合工艺(如热压或回焊等)，通过凸块将第一半导体元件电性耦接至第一路由电路。同样地，第二半导体元件亦可利用现有的覆晶接合工艺，通过设置于第一路由电路第二表面处的凸块电性耦接至次组体。该牺牲载板可于形成平衡层后，通过化学蚀刻或机械剥离方式自第一路由电路移除。较佳为，该次组体以面板尺寸制备，接着再切割成个别单件。此外，可于提供平衡层前或提供平衡层后，通过黏着剂，将一加强层贴附至第一半导体元件。在散热增益型的实施方式中，较佳使用导热黏着剂，以将具导热性的加强层贴附至第一半导体元件。据此，该加强层不仅可对次组体提供机械支撑力，其亦可提供第一半导体元件散热的途径。另外，该次组体亦可通过另一工艺方式制备，其包括下述步骤：通过黏着剂，将第一半导体元件贴附至加热层(若使用具导热性的加强层，该黏着剂通常为导热黏着剂)；提供平衡层于加强层上；以及形成第一路由电路于第一半导体元件及平衡层上，并使第一半导体元件由第一路由电路的第一表面电性耦接至第一路由电路。在此工艺中，第一路由电路可直接通过增层工艺而电性耦接至第一半导体元件。此外，可提供定位件以确保第一半导体元件置放于加强层上的准确度。更具体地说，定位件由加强层的一表面凸起，而第一半导体元件利用定位件侧向对准第一半导体元件外围边缘的方式贴附至加强层上。由于定位件朝第二方向延伸超过第一半导体元件的非有源面，并且靠近第一半导体元件的外围边缘，因而可避免第一半导体元件发生不必要位移。由此，可确保第一路由电路互连至第一半导体元件时有较高的生产良率。
定位件可具有防止第一半导体元件发生不必要位移的各种图案。举例来说，定位件可包括一连续或不连续的凸条、或是凸柱阵列。或者，定位件可侧向延伸至加强层的外围边缘，且其内周围边缘与第一半导体元件的外围边缘相符。具体来说，定位件可侧向对准第一半导体元件的四侧边，以定义出与第一半导体元件形状相同或相似的区域，并且避免第一半导体元件的侧向位移。举例来说，定位件可对准并符合第一半导体元件的四侧边、两对角、或四角，以限制第一半导体元件发生侧向位移。此外，定位件(位于第一半导体元件的非有源面周围)较佳具有5至200微米的高度。
互连板侧向延伸超过次组体的外围边缘，且较佳具有延伸穿过第二路由电路的凹穴，以显露散热座的一选定部分，并用以容纳第二半导体元件。该散热座可通过导热材料贴附至第二半导体元件，以提供第二半导体元件散热的途径。第二路由电路可通过凸块(而非直接通过增层工艺)电性耦接至第一路由电路。较佳为，与第二路由电路接触的凸块高度大于与第二半导体元件接触的凸块，但小于与第二半导体元件接触的凸块高度加上第二半导体元件高度的结合高度。更具体地说，与第二半导体元件接触的凸块高度加上第二半导体元件高度的结合高度，可实质上相等于凹穴深度加上与第二路由电路接触的凸块高度。
第一及第二路由电路可为不具核心层的增层电路。此外，第一路由电路侧向延伸超过第一及第二半导体元件的外围边缘，而第二路由电路则侧向延伸超过第一路由电路的外围边缘。据此，第二路由电路的表面积可大于第一路由电路的表面积。较佳为，第一及第二路由电路为多层结构的增层电路，且各自包括至少一介电层及导线，其中导线填满介电层中的盲孔，并侧向延伸于介电层上。介电层与导线连续轮流形成，且需要的话可重复形成。
第一路由电路可对第一及第二半导体元件提供扇出路由/互连及最短互连距离。具体地说，与第一及第二半导体元件的垫尺寸及垫间距相比，第一路由电路的第二表面处导线较佳具有较大的垫尺寸及垫间距。举例来说，第一路由电路的第一表面处可包含有连接第一半导体元件的顶部导线，而第二表面处可包含有连接第二半导体元件及第二路由电路的底部导线。在此，顶部导线可通过导电盲孔或内层导线而与底部导线电性连接。于一较佳实施例中，第二表面处的底部导线具有连接芯片用的第一接触垫及连接下一级路由电路的第二接触垫，其中第一接触垫的垫尺寸及垫间距与第二半导体元件的I/O垫相符，而第二接触垫的垫尺寸及垫间距则大于第一接触垫及第一/第二半导体元件I/O垫的垫尺寸及垫间距，并与第二路由电路的第一端子垫相符。据此，第二半导体元件可电性耦接至第一接触垫，而第二路由电路则互连至第二接触垫。或者，第一路由电路可包含接触第一半导体元件的导线，其自第一半导体元件延伸，并填满介电层中的盲孔，以形成与第一半导体元件电性接触的导电盲孔，同时侧向延伸于介电层上，以提供用于连接第二半导体元件的第一接触垫及垫尺寸及垫间距大于第一/第二半导体元件的第二接触垫。
第二路由电路可提供进一步地扇出路由/互连，以放大第一路由电路的垫尺寸及垫间距。更具体地说，第二路由电路可包括一介电层及导线，其中介电层位于散热座上，而导线侧向延伸于第二路由电路的介电层上。第二路由电路的最外层导线可具有用于连接第一路由电路的第一端子垫以及用于连接下一级组体或另一电子元件的第二端子垫，其中第一端子垫的垫尺寸及垫间距与第一路由电路的第二接触垫相符，而第二端子垫的垫尺寸及垫间距则大于第一端子垫的垫尺寸及垫间距。据此，第二路由电路的第一端子垫可电性耦接至第一路由电路的第二接触垫，而第二端子垫则可容置导电接点，例如焊球，以与下一级组体或另一电子元件电性传输及机械性连接。此外，第二路由电路亦可通过直接接触散热座的导电盲孔，电性耦接至散热座，以作为接地连接。
“覆盖”一词意指于垂直及/或侧面方向上不完全以及完全覆盖。例如，在凹穴朝上的状态下，散热座于下方覆盖第二半导体元件，不论另一元件例如导热材料是否位于第二半导体元件与散热座之间。
“贴附于…上”一词包括与单一或多个元件间的接触与非接触。例如，散热座贴附于第二半导体元件的非有源面上，不论此散热座是否与第二半导体元件以一导热材料相隔。
“对准”一词意指元件间的相对位置，不论元件之间是否彼此保持距离或邻接，或一元件插入且延伸进入另一元件中。例如，当假想的水平线与定位件及第一半导体元件相交时，定位件即侧向对准于第一半导体元件，不论定位件与第一半导体元件之间是否具有其他与假想的水平线相交的元件，且不论是否具有另一与第一半导体元件相交但不与定位件相交、或与定位件相交但不与第一半导体元件相交的假想水平线。同样地，第二半导体元件对准于互连板的凹穴。
“靠近”一词意指元件间之间隙的宽度不超过最大可接受范围。如本领域公知常识，当第一半导体元件以及定位件间之间隙不够窄时，由于第一半导体元件于间隙中的侧向位移而导致的位置误差可能会超过可接受的最大误差限制。在某些情况下，一旦第一半导体元件的位置误差超过最大极限时，则不可能使用激光束对准第一半导体元件的预定位置，而导致第一半导体元件以及路由电路间的电性连接失败。根据第一半导体元件的接触垫的尺寸，于本领域的技术人员可经由试误法以确认第一半导体元件以及定位件间的间隙的最大可接受范围，以确保路由电路的导电盲孔与第一半导体元件的I/O垫对准。由此，“定位件靠近第一半导体元件的外围边缘”的用语是指第一半导体元件的外围边缘与定位件间的间隙窄到足以防止第一半导体元件的位置误差超过可接受的最大误差限制。举例来说，第一半导体元件与定位件间的间隙可约于5微米至50微米的范围内。
“电性连接”、以及“电性耦接”的词意指直接或间接电性连接。例如，第二路由电路的最外层导线(背对散热座)直接接触并且电性连接至第一凸块，而第二路由电路的最内层导线(邻近于散热座)与第一凸块保持距离，并且通过内层导线而电性连接至第一凸块。
“第一方向”及“第二方向”并非取决于半导体组体的定向，凡熟悉此项技艺的人士即可轻易了解其实际所指的方向。例如，第一路由电路的第一表面面朝第一方向，而第一路由电路的第二表面面朝第二方向，此与半导体组体是否倒置无关。因此，该第一及第二方向彼此相反且垂直于侧面方向。再者，在凹穴朝上的状态，第一方向为向上方向，第二方向为向下方向；在凹穴朝上下的状态，第一方向为向下方向，第二方向为向上方向。
本发明的半导体组体具有许多优点。举例来说，将第一及第二半导体元件面朝面地接置于第一路由电路的相对两侧上，可于第一半导体元件与第二半导体元件间提供最短的互连距离。第一路由电路可对第一及第二半导体元件提供第一级的扇出路由/互连，而第二路由电路可提供第二级的扇出路由/互连。次组体的第一路由电路可通过凸块接置于互连板的第二路由电路处，由于第二路由电路不是直接通过增层工艺电性耦接至第一路由电路，故此简化的工艺步骤可降低制作成本。散热座可提供第二半导体元件的散热、电磁屏蔽、以及湿气阻挡，并且提供次组体及第二路由电路的机械性支撑。通过此方法制备成的半导体组体为可靠度高、价格低廉、且非常适合大量制造生产。
本发明的制作方法具有高度适用性，且以独特、进步的方式结合运用各种成熟的电性及机械性连接技术。此外，本发明的制作方法不需昂贵工具即可实施。因此，相较于传统技术，此制作方法可大幅提升产量、良率、效能与成本效益。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

1.一种内建散热座的散热增益型面朝面半导体组体，其包括：
一次组体，其包含一第一半导体元件、一平衡层及具有一第一表面及一相对第二表面的一第一路由电路，其中该第一路由电路为不具核心层的增层电路，且该第一半导体元件由该第一路由电路的该第一表面电性耦接至该第一路由电路，而该平衡层侧向环绕该第一半导体元件并覆盖该第一路由电路的该第一表面；以及
一散热增益型构件，其电性耦接至该次组体，并包含一第二半导体元件、一散热座及设置于该散热座上之一第二路由电路，其中(i)该散热座侧向延伸至该第二路由电路的外围边缘，以支撑该第二路由电路，(ii)该第二路由电路的最外层导线具有第一端子垫及第二端子垫，所述第二端子垫的垫尺寸及垫间距大于所述第一端子垫的垫尺寸及垫间距，(iii)该第二半导体元件贴附至该散热座，且被该第二路由电路侧向环绕，并通过一系列第一凸块，电性耦接至该第一路由电路，(iv)该第二路由电路为不具核心层的增层电路，且该第二路由电路的所述第一端子垫通过一系列第二凸块，电性耦接至该第一路由电路，且(v)所述第一凸块及所述第二凸块设置于该第一路由电路的该第二表面。
2.如权利要求1所述的半导体组体，其特征在于，该第二半导体元件设置于被该第二路由电路侧向环绕的一凹穴中。
3.如权利要求1所述的半导体组体，其特征在于，该次组体还包含一加强层，其贴附至该第一半导体元件的一非有源面。
4.如权利要求1所述的半导体组体，其特征在于，该第一路由电路包括侧向延伸超过该第一半导体元件外围边缘的至少一导线，而该第二路由电路包括侧向延伸超过该次组体外围边缘的至少一导线。
5.一种内建散热座的散热增益型面朝面半导体组体制作方法，其包括：
提供一次组体，包含：
提供一第一路由电路，其可拆分式地接置于一牺牲载板上，其中该第一路由电路为不具核心层的增层电路；
将一第一半导体元件由该第一路由电路的一第一表面，电性耦接至该第一路由电路，其中该第一半导体元件具有面向该第一路由电路的一有源面及相对于该有源面的一非有源面；
提供一平衡层，其侧向环绕该第一半导体元件且覆盖该第一路由电路的该第一表面；及
移除该牺牲载板，以显露该第一路由电路的相对于该第一表面的一第二表面；
通过一系列第一凸块，将一第二半导体元件由该第一路由电路的该第二表面，电性耦接至该次组体的该第一路由电路；
提供一互连板，其包含一散热座及设置于该散热座上的一第二路由电路，其中该散热座侧向延伸至该第二路由电路的外围边缘，以支撑该第二路由电路，而该第二路由电路为不具核心层的增层电路，且该第二路由电路的最外层导线具有第一端子垫及第二端子垫，所述第二端子垫的垫尺寸及垫间距大于所述第一端子垫的垫尺寸及垫间距；以及
通过一系列第二凸块，将该互连板的该第二路由电路的所述第一端子垫由该第一路由电路的该第二表面，电性耦接至该次组体的该第一路由电路，并使该第二半导体元件贴附至该散热座。
6.如权利要求5所述的制作方法，其特征在于，将该第二半导体元件电性耦接至该第一路由电路的该步骤包含：使该第二半导体元件插入该互连板的一凹穴中。
7.如权利要求5所述的制作方法，其特征在于，提供该次组体的该步骤还包含：将一加强层贴附至该第一半导体元件的该非有源面。
8.如权利要求5所述的制作方法，其特征在于，该平衡层还覆盖该第一半导体元件的该非有源面。
9.一种内建散热座的散热增益型面朝面半导体组体制作方法，其包括：
提供一次组体，包含：
将一第一半导体元件贴附至一加强层，其中该第一半导体元件具有面向该加强层的一非有源面及相对于该非有源面的一有源面；
提供一平衡层，其侧向环绕该第一半导体元件；及
形成一第一路由电路于该第一半导体元件的该有源面及该平衡层上，并使该第一半导体元件由该第一路由电路的一第一表面，电性耦接至该该第一路由电路，其中该第一路由电路为不具核心层的增层电路；
通过一系列第一凸块，将一第二半导体元件由该第一路由电路的相对于该第一表面的一第二表面，电性耦接至该次组体的该第一路由电路；
提供一互连板，其包含一散热座及设置于该散热座上的一第二路由电路，其中该散热座侧向延伸至该第二路由电路的外围边缘，以支撑该第二路由电路，而该第二路由电路为不具核心层的增层电路，且该第二路由电路的最外层导线具有第一端子垫及第二端子垫，所述第二端子垫的垫尺寸及垫间距大于所述第一端子垫的垫尺寸及垫间距；以及
通过一系列第二凸块，将该互连板的该第二路由电路的所述第一端子垫由该第一路由电路的该第二表面，电性耦接至该次组体的该第一路由电路，并使该第二半导体元件贴附至该散热座。
10.如权利要求9所述的制作方法，其特征在于，将该第二半导体元件电性耦接至该第一路由电路的该步骤包含：使该第二半导体元件插入该互连板的一凹穴中。
11.如权利要求9所述的制作方法，其特征在于该次组体还包含一定位件，其由该加强层的一表面凸出，且该第一半导体元件贴附至该加强层时，该定位件侧向对准且靠近该第一半导体元件外围边缘，并延伸超过该第一半导体元件的该非有源面。
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