TW201842636A - 三維整合之散熱增益型半導體組體及其製作方法 - Google Patents

三維整合之散熱增益型半導體組體及其製作方法 Download PDF

Info

Publication number
TW201842636A
TW201842636A TW107106052A TW107106052A TW201842636A TW 201842636 A TW201842636 A TW 201842636A TW 107106052 A TW107106052 A TW 107106052A TW 107106052 A TW107106052 A TW 107106052A TW 201842636 A TW201842636 A TW 201842636A
Authority
TW
Taiwan
Prior art keywords
circuit structure
circuit
heat sink
routing
electrically coupled
Prior art date
Application number
TW107106052A
Other languages
English (en)
Other versions
TWI656615B (zh
Inventor
文強 林
王家忠
Original Assignee
鈺橋半導體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 鈺橋半導體股份有限公司 filed Critical 鈺橋半導體股份有限公司
Publication of TW201842636A publication Critical patent/TW201842636A/zh
Application granted granted Critical
Publication of TWI656615B publication Critical patent/TWI656615B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H01L2224/81207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本發明之三維整合的散熱增益型半導體組體包含有藉由接合線相互電性耦接之堆疊式半導體次組體及線路板。散熱座設置於線路結構之貫穿開口中，用以提高該堆疊式半導體次組體之散熱性。設置於散熱座上之另一線路結構不僅提供機械支撐，其亦可藉由金屬化盲孔對散熱座進行散熱及接地電連接。接合線提供次組體與線路板間之電性連接，以將組裝於次組體中之裝置互連至線路板之端子墊。

Description

三維整合之散熱增益型半導體組體及其製作方法
本發明是關於一種半導體組體及其製作方法，尤指一種三維整合之散熱增益型半導體組體及其製作方法，其將堆疊式半導體次組體打線連接並熱性導通至線路板，其中線路板具有與雙線路結構整合之散熱座。
多媒體裝置之市場趨勢係傾向於更迅速且更薄型化之設計需求。其中一種方法是以堆疊方式以互連兩裝置，俾使兩裝置間具有最短的路由距離。由於疊置之裝置間可直接相互傳輸，以降低延遲，故可大幅改善組體之信號完整度，並節省額外的耗能。然而，由於半導體裝置易於高操作溫度下發生效能劣化現象，因此若堆疊式晶片未進行適當散熱，則會使裝置的熱環境變差，導致操作時可能出現立即失效的問題。
美國專利案號8,008,121、8,519,537及8,558,395揭露各種具有中介層之組體結構，其係將中介層設於面朝面設置之晶片間。雖然其無需於堆疊晶片中形成矽穿孔(TSV)，但中介層中用於提供晶片間電性路由之矽穿孔會導致製程複雜、生產良率低及高成本。
為了上述理由及以下所述之其他理由，目前亟需發展一種三維半導體組體，以達到高封裝密度、較佳信號完整度及高散熱度之要求。
本發明之目的係提供一種散熱增益型半導體組體，其藉由複數接合線，將堆疊式半導體次組體電性連接至線路板，並使堆疊式半導體次組體與線路板內建的散熱座熱性導通。該散熱座設置於線路結構之貫穿開口中，並由額外的線路結構對散熱座提供機械支撐，且散熱座可與該額外的線路結構電性連接，並透過該額外的線路結構進行散熱，進而可改善組體的機械、熱性及電性校能。
依據上述及其他目的，本發明提供一種散熱增益型半導體組體，其藉由接合線，使堆疊式半導體次組體電性連接至線路板。該堆疊式半導體次組體包括一第一裝置、一第二裝置及一路由電路。該線路板包括一散熱座、一第一線路結構及一第二線路結構。於一較佳實施例中，第一裝置與散熱座熱性導通，且第一裝置與第二裝置間是以路由電路相隔，並藉由路由電路相互電性連接；路由電路對第一裝置及第二裝置提供初級的扇出路由及最短的互連距離；第一線路結構側向環繞散熱座及次組體的外圍邊緣，並藉由接合線電性耦接至路由電路，以提供進一步的扇出路由；第二線路結構覆蓋第一線路結構及散熱座，以提供機械支撐，且第二線路結構熱性導通至散熱座，並電性耦接至第一線路結構。
據此，本發明提供一種三維整合之散熱增益型半導體組體，其包含：一堆疊式半導體次組體，其包括一第一裝置、一第二裝置及一路由電路，其中該第一裝置電性耦接至該路由電路之一第一表面，而該第二裝置電性耦接至該路由電路之一相反第二表面；一線路板，其包括一第一線路結構、一第二線路結構及一散熱座，其中(i)該第一線路結構具有一第一表面、一相反第二表面、及從該第一表面延伸至該第二表面之一貫穿開口，(ii)該散熱座設置於該貫穿開口中，且該散熱座之一背側表面與該第一線路結構之該第一表面呈實質上共平面，(iii)該第二線路結構設置於該散熱座之該背側表面及該第一線路結構之該第一表面上，並藉由金屬化盲孔電性連接至該第一線路結構且熱性導通至該散熱座，且(iv)該堆疊式半導體次組體設置於該貫穿開口中；以及複數接合線，其電性耦接該路由電路至該線路板。
此外，本發明提供一種三維整合之散熱增益型半導體組體的製作方法，其包括下述步驟：提供一堆疊式半導體次組體，其包括一第一裝置、一第二裝置及一路由電路，其中該第一裝置電性耦接至該路由電路之一第一表面，而該第二裝置電性耦接至該路由電路之一相反第二表面；提供一線路板，其包括一第一線路結構、一第二線路結構及一散熱座，其中(i)該第一線路結構具有一第一表面、一相反第二表面、及從該第一表面延伸至該第二表面之一貫穿開口，(ii)該散熱座設置於該貫穿開口中，且該散熱座之一背側表面與該第一線路結構之該第一表面呈實質上共平面，且(iii)該第二線路結構設置於該散熱座之該背側表面及該第一線路結構之該第一表面上，並藉由金屬化盲孔電性連接至該第一線路結構且熱性導通至該散熱座；將該堆疊式半導體次組體設置於該第一線路結構之該貫穿開口中及該散熱座上；以及提供複數接合線，以電性耦接該路由電路及該線路板。
除非特別描述或步驟間使用”接著”字詞，或者是必須依序發生之步驟，上述步驟之順序並無限制於以上所列，且可根據所需設計而變化或重新安排。
本發明之半導體組體及其製作方法具有許多優點。舉例來說，將第一裝置及第二裝置堆疊並電性耦接至路由電路之相反兩側，可提供第一裝置與第二裝置間之最短互連距離。將次組體插入線路板第一線路結構之貫穿開口是特別具有優勢的，其原因在於，線路板可對次組體提供機械外殼，而位於貫穿開口中且被第二線路結構支撐的散熱座可提供第一裝置散熱途徑。此外，將接合線接至該次組體及該線路板之作法，可提供可靠的連接通道，以將組裝於次組體中之裝置互連至線路板的端子墊。
本發明之上述及其他特徵與優點可藉由下述較佳實施例之詳細敘述更加清楚明瞭。
在下文中，將提供一實施例以詳細說明本發明之實施態樣。本發明之優點以及功效將藉由本發明所揭露之內容而更為顯著。在此說明所附之圖式係簡化過且做為例示用。圖式中所示之元件數量、形狀及尺寸可依據實際情況而進行修改，且元件的配置可能更為複雜。本發明中也可進行其他方面之實踐或應用，且不偏離本發明所定義之精神及範疇之條件下，可進行各種變化以及調整。
[實施例1]
圖1-12為本發明第一實施態樣中，一種半導體組體之製作方法圖，其包括一路由電路21、一第一裝置22、一模封材25、一第二裝置27、一線路板30及接合線41。
圖1為犧牲載板10上形成路由線212之剖視圖。該犧牲載板10通常由銅、鋁、鐵、鎳、錫、不鏽鋼、矽或其他金屬或合金製成，但亦可使用任何其他導電或非導電材料製成。於本實施態樣中，該犧牲載板10係由含鐵材料所製成。路由線212通常由銅所製成，且可經由各種技術進行圖案化沉積，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合，或者藉由薄膜沉積而後進行金屬圖案化步驟而形成。就具導電性之犧牲載板10而言，一般是藉由金屬電鍍方式沉積，以形成路由線212。金屬圖案化技術包括濕蝕刻、電化學蝕刻、雷射輔助蝕刻及其組合，並使用蝕刻光罩(圖未示)，以定義出路由線212。
圖2為具有介電層215及盲孔216之剖視圖，其中介電層215位於犧牲載板10及路由線212上，而盲孔216於介電層215中。介電層215一般可藉由層壓或塗佈方式沉積而成，並接觸犧牲載板10及路由線212，且介電層215係由上方覆蓋並側向延伸於犧牲載板10及路由線212上。介電層215通常具有50微米的厚度，且可由環氧樹脂、玻璃環氧樹脂、聚醯亞胺、或其類似物所製成。於沉積介電層215後，可藉由各種技術形成盲孔216，如雷射鑽孔、電漿蝕刻、及微影技術，且通常具有50微米之直徑。可使用脈衝雷射提高雷射鑽孔效能。或者，可使用掃描雷射光束，並搭配金屬光罩。盲孔216係延伸穿過介電層215，並對準路由線212之選定部位。
參考圖3，藉由金屬沉積及金屬圖案化製程形成導線217於介電層215上。導線217自路由線212朝上延伸，並填滿盲孔216，以形成直接接觸路由線212之金屬化盲孔218，同時側向延伸於介電層215上。因此，導線217可提供X及Y方向的水平信號路由以及穿過盲孔216的垂直路由，以作為路由線212的電性連接。
導線217可藉由各種技術沉積為單層或多層，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合。舉例來說，首先藉由將該結構浸入活化劑溶液中，使介電層215與無電鍍銅產生觸媒反應，接著以無電電鍍方式被覆一薄銅層作為晶種層，然後以電鍍方式將所需厚度之第二銅層形成於晶種層上。或者，於晶種層上沉積電鍍銅層前，該晶種層可藉由濺鍍方式形成如鈦/銅之晶種層薄膜。一旦達到所需之厚度，即可使用各種技術圖案化被覆層，以形成導線217，如濕蝕刻、電化學蝕刻、雷射輔助蝕刻或其組合，並使用蝕刻光罩(圖未示)，以定義出導線217。
此階段已完成於犧牲載板10上形成路由電路21之製程。於此圖中，路由電路21為多層增層電路，其包括路由線212、介電層215及導線217。
圖4為第一裝置22電性耦接至路由電路21之剖視圖。第一裝置22可藉由熱壓、迴焊、或熱超音波接合技術，經由第一凸塊223電性耦接至路由電路21之導線217，其中第一凸塊223接觸第一裝置22及路由電路21。於此實施態樣中，該第一裝置22係繪示成半導體晶片。
圖5為形成模封材25於路由電路21上及第一裝置22周圍之剖視圖，其中該模封材25可藉由如樹脂-玻璃層壓、樹脂-玻璃塗佈或模製(molding)方式形成。該模封材25是由上方覆蓋路由電路21，且環繞、同形披覆並覆蓋第一裝置22之側壁。或者，也可省略形成該模封材25之步驟。
圖6為移除犧牲載板10之剖視圖。犧牲載板10可藉由各種方式移除，以由下方顯露路由電路21，如使用酸性溶液(如氯化鐵、硫酸銅溶液)或鹼性溶液(如氨溶液)之濕式化學蝕刻、電化學蝕刻、或於機械方式(如鑽孔或端銑)後再進行化學蝕刻。於此實施態樣中，由含鐵材料所製成之犧牲載板10可藉由化學蝕刻溶液移除，其中化學蝕刻溶液於銅與鐵間具有選擇性，以避免移除犧牲載板10時導致銅路由線212遭蝕刻。
圖7為第二裝置27電性耦接至路由電路21之剖視圖。第二裝置27可藉由熱壓、迴焊、或熱超音波接合技術，經由第二凸塊273電性耦接至路由電路21之路由線212，其中第二凸塊273接觸第二裝置27及路由電路21。於此實施態樣中，該第二裝置27係繪示成半導體晶片。然而，於其他實例中，第二裝置27亦可為已封裝元件或被動元件。
此階段已完成堆疊式半導體次組體20之製作，其包括一路由電路21、一第一裝置22、一模封材25及一第二裝置27。第一裝置22及第二裝置27分別電性耦接至路由電路21之第一表面201及第二表面202，且該模封材25設置於第一表面201上，並環繞第一裝置22。
圖8為第一線路結構31之剖視圖。該第一線路結構31具有一貫穿開口315，其自第一表面311延伸至第二表面312。於此圖式中，該第一線路結構31包含一互連基板32、一第一增層電路33及一第二增層電路34。該互連基板32包括一核心層321、一第一路由層323、一第二路由層324及金屬化貫孔327。第一路由層323及第二路由層324分別側向延伸於核心層321之兩側，而金屬化貫孔327延伸穿過該核心層321，以提供第一路由層323及第二路由層324間之電性連接。第一增層電路33及第二增層電路34分別設置於互連基板32之兩側上，且各別包括一介電層331、341及導線333、343。介電層331、341分別由下方及上方覆蓋互連基板32之兩側，且可由環氧樹脂、玻璃環氧樹脂、聚醯亞胺、或其類似物所製成。導線333、343分別側向延伸於介電層331、341上，並包括位於介電層331、341中之金屬化盲孔334、344。金屬化盲孔334、344分別接觸互連基板32之第一路由層323及第二路由層324，並延伸穿過介電層331、341。
圖9為散熱座35設置於第一線路結構31貫穿開口315中之剖視圖。散熱座35可為由金屬、合金、矽、陶瓷或石墨製成之導熱層。於此實施態樣中，該散熱座35為一金屬層，且其背側表面351於向下方向上與第一線路結構31之第一表面311呈實質上共平面。
圖10為第二線路結構36形成於散熱座35背側表面351及第一線路結構31第一表面311上之剖視圖。於此圖式中，該第二線路結構36為不具核心層之多層增層電路，其包括交替形成的多層介電層361及導線363。導線363側向延伸於介電層361上，並包含金屬化盲孔364於介電層361中。據此，第二線路結構36可透過嵌埋於介電層361中並接觸第一路由層323及散熱座35之金屬化盲孔364，電性耦接至第一線路結構31及散熱座35。
於此階段中，已完成之線路板30包括有一第一線路結構31、一散熱座35及一第二線路結構36。由於貫穿開口315深度大於散熱座35厚度，故散熱座35的外側表面與第一線路結構31貫穿開口315的側壁表面會構成位於第一線路結構31貫穿開口315中之凹穴316。因此，散熱座35可對容置於凹穴316中的裝置提供散熱，而第一線路結構31及第二線路結構36可於線路板30兩相反側提供下一級連接用的電性接點。
圖11為圖7堆疊式半導體次組體20貼附至圖10線路板30之剖視圖。該堆疊式半導體次組體20會對準第一線路結構31的貫穿開口315，並設置於第一線路結構31貫穿開口315中，且第一裝置22是利用導熱材39貼附至線路板30的散熱座35。導熱材39可為焊料(如AuSn)或銀/環氧黏著劑。貫穿開口315的內部側壁側向環繞堆疊式半導體次組體20的外圍邊緣，並與堆疊式半導體次組體20的外圍邊緣保持距離。因此，堆疊式半導體次組體20外圍邊緣與第一線路結構31內部側壁間會留有位於貫穿開口315中的間隙317。該間隙317側向環繞堆疊式半導體次組體20，且第一線路結構31側向環繞該間隙317。
圖12為接合線41接至堆疊式半導體次組體20及線路板30之剖視圖，其通常可藉由金或銅球形接合(ball bonding)或金或鋁楔型接合(wedge bonding)方式，以接置接合線41。接合線41接觸並電性耦接至路由電路21之路由線212及線路板30之導線343。因此，接合線41可將路由電路21電性耦接至第一線路結構31。
據此，如圖12所示，已完成之半導體組體110包括有藉由接合線41相互電性連接之堆疊式半導體次組體20及線路板30。於此圖中，該堆疊式半導體次組體20包括一路由電路21、一第一裝置22、一模封材25及一第二裝置27，而線路板30包括一第一線路結構31、一散熱座35及一第二線路結構36。
第一裝置22是由路由電路21之一側，以覆晶方式電性耦接至路由電路21，並被模封材25及散熱座35所包圍。第二裝置27則由路由電路21之另一側，以覆晶方式電性耦接至路由電路21，並藉由路由電路21與第一裝置22相互面朝面地連接。據此，路由電路21可提供初級扇出路由及第一裝置22與第二裝置27間之最短互連距離。線路板30之散熱座35會與第一裝置22熱性導通，並由下方覆蓋第一裝置22。第一線路結構31側向環繞堆疊式半導體次組體20及散熱座35的外圍邊緣，並藉由接合線41電性耦接至路由電路21。第二線路結構36由下方覆蓋第一線路結構31及散熱座35，並藉由金屬化盲孔364電性耦接至第一線路結構31，同時也藉由金屬化盲孔364與散熱座35熱性導通。因此，路由電路21、第一線路結構31及第二線路結構36可對第一裝置22及第二裝置27提供階段式的扇出路由。
圖13為圖12半導體組體110更設有密封材51之剖視圖。該密封材51由上方覆蓋接合線41、堆疊式半導體組體20及線路板30之選定部位，並進一步填滿堆疊式半導體組體20外圍邊緣與線路板30內部側壁間的間隙317。
圖14為圖13半導體組體110更設有第三裝置61堆疊於堆疊式半導體組體20與線路板30第一線路結構31上方之剖視圖。第三裝置61可為球柵陣列封裝(ball grid array package)或凸塊化晶片(bumped chip)，且藉由複數焊球71，電性耦接至第一線路結構31之導線343。
圖15為圖14半導體組體110更設有焊球73之剖視圖。該些焊球73接置於線路板30之第二線路結構36上，用以外部連接。
圖16為圖13半導體組體110更設有被動元件65、焊球73及散熱座81之剖視圖，其中被動元件65與散熱座81位於第一線路結構31處，而焊球73位於第二線路結構36處。被動元件65電性耦接至第一線路結構31之導線343。散熱座81具有一凹穴811，並接置於第一線路結構31上，且藉由焊球75電性耦接至第一線路結構31的導線343，以構成接地連接。第二裝置27容置於散熱座81的凹穴811中，並藉由導熱材89與散熱座81熱性導通，其中導熱材89會接觸第二裝置27與散熱座81。焊球73接置於第二線路結構36之導線363上，用以外部連接。
圖17為顛倒的圖13半導體組體110更設有第三裝置61、焊球73及散熱座81之剖視圖，其中第三裝置61與散熱座81位於第二線路結構36處，而焊球73位於第一線路結構31處。第三裝置61可為球柵陣列封裝(ball grid array package)或凸塊化晶片(bumped chip)，並容置於散熱座81之凹穴811內，且藉由複數焊球71，電性耦接至第二線路結構36之導線363。散熱座81藉由導熱材89與第三裝置61熱性導通，並藉由焊球75電性耦接至第二線路結構36之導線363。焊球73接置於第一線路結構31之導線343上，用以外部連接。
圖18為圖13半導體組體110更設有額外線路板90之剖視圖。該線路板90堆疊於堆疊式半導體次組體20與線路板30上，並包含有一第三線路結構91、一散熱座95及一第四線路結構96。於此圖中，第三線路結構91及第四線路結構96皆為不具核心層之多層增層電路，其分別包括交替形成之多層介電層911, 961及導線913, 963，以於線路板90之相反兩側提供電性接點。第三線路結構91具有從第一表面911延伸至第二表面912的貫穿開口915，並藉由焊球71電性耦接至第一線路結構31之導線343。散熱座95設置於第三線路結構91之貫穿開口915內，且散熱座95的背側表面952與第三線路結構91的第二表面912呈實質上共平面。第二裝置27藉由導熱材99貼附至散熱座95，以與散熱座95熱性導通，且第三線路結構91側向環繞第二裝置27。第四線路結構96設置於第三線路結構91第二表面912及散熱座95背側表面952上，並包括嵌埋於介電層961中並與第三線路結構91導線913及散熱座95接觸的金屬化盲孔964。
圖19為圖18半導體組體110更設有第三裝置61及焊球73之剖視圖，其中第三裝置61位於第四線路結構96處，而焊球73位於第二線路結構36處。第三裝置61可為球柵陣列封裝(ball grid array package)或凸塊化晶片(bumped chip)，並藉由焊球77堆疊且電性耦接至第四線路結構96之導線963。焊球73接置於第二線路結構36之導線363上，用以外部連接。
圖20為圖13半導體組體110更設有另一額外線路板90態樣之剖視圖。線路板90與圖18所示結構類似，不同處在於，第三線路結構91為一互連基板，其包括一核心層921、一第一路由層923、一第二路由層924及金屬化貫孔927。第一路由層923及第二路由層924設於核心層921的相反側。金屬化貫孔927延伸貫穿核心層921，並電性耦接至第一路由層923及第二路由層924。第四線路結構96包括與第三線路結構91之第二路由層924及散熱座95接觸之金屬化盲孔964。
[實施例2]
圖21-24為本發明第二實施態樣中，另一種半導體組體之製作方法圖，其中線路板的凹穴具有側向環繞堆疊式半導體次組體之金屬化側壁。
為了簡要說明之目的，上述實施例1中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。
圖21為線路板30之剖視圖。該線路板30與圖10所示結構類似，不同處在於，(i)該線路板30更包括一金屬層37，其完全覆蓋第一線路結構31之貫穿開口315側壁，並與散熱座35接觸，(ii)第二線路結構35之最外層導線363包含有一導熱墊366。於此圖中，該散熱座35的外表面與金屬層37的側表面形成一凹穴316，且該凹穴316是位於第一線路結構31之貫穿開口315中。
圖22為圖7堆疊式半導體次組體20貼附至圖21線路板30之剖視圖。該堆疊式半導體次組體20設置於線路板30之凹穴316中，並利用導熱材39貼附至散熱座35。
圖23為接合線41接至堆疊式半導體次組體20及線路板30之剖視圖。接合線41接觸並電性耦接至路由電路21之路由線212及第一線路結構31之導線343。
據此，如圖23所示，完成之半導體組體210包括藉由接合線41相互電性連接之堆疊式半導體次組體20及線路板30。於此圖中，該堆疊式半導體次組體20包括一路由電路21、一第一裝置22、一模封材25及一第二裝置27，而該線路板30包括一第一線路結構31、一散熱座35、一第二線路結構36及一金屬層37。
第一裝置22及第二裝置27分別設置於路由電路21之相反兩側處，並藉由兩者間之路由電路21，面朝面地相互電性連接。據此，路由電路21可提供第一裝置22與第二裝置27間之最短互連距離，並對第一裝置22與第二裝置27提供第一級扇出路由。該散熱座35覆蓋第一裝置22的非主動面，並與第一裝置22熱性導通，而金屬層37則環繞堆疊式半導體次組體20之外圍邊緣，並與散熱座35接觸。第一線路結構31藉由接合線41，電性耦接至路由電路21。第二線路結構36由下方覆蓋第一線路結構31及散熱座35，並透過金屬化盲孔364電性耦接至第一線路結構31，以構成信號路由，同時也藉由金屬化盲孔364電性耦接至散熱座35，以構成接地連接。據此，第一線路結構31與第二線路結構36之整體可對路由電路21提供第二級之扇出路由，並提供下一級連接用之電性接點，而電性連接至第二線路結構36之散熱座35與金屬層37則可共同對第一裝置22提供散熱及電磁屏蔽。
圖24為圖23半導體組體210更設有密封材51之剖視圖。該密封材51由上方覆蓋接合線41、堆疊式半導體組體20及第一線路結構31之選定部位，並進一步填滿堆疊式半導體組體20外圍邊緣與線路板30內部側壁間的間隙317。
圖25為顛倒的圖24半導體組體210更設有第三裝置61及被動元件65之剖視圖。第三裝置61是繪示成半導體晶片，並貼附於第二線路結構36之導熱墊366上，且藉由接合線72電性耦接至第二線路結構36之導線363。被動元件65則接置於第二線路結構36之導線363上，並與第二線路結構36之導線363電性耦接。
圖26為圖25半導體組體210更設有密封材85之剖視圖。該密封材85由上方覆蓋接合線72、第三裝置61、被動元件65及第二線路結構36。
圖27為圖26半導體組體210更設有焊球73之剖視圖。該些焊球73接置於第一線路結構31之導線343上，用以外部連接。
[實施例3]
圖28-31為本發明第三實施態樣中，線路板上設有垂直連接件之半導體組體製作方法圖。
為了簡要說明之目的，上述實施例中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。
圖28為堆疊式半導體次組體20容置於圖10線路板30凹穴316中之剖視圖。該堆疊式半導體次組體20與圖7所示結構相似，惟不同處在於，該堆疊式半導體次組體20更包括一被動元件23及一金屬柱24，該被動元件23及該金屬柱24電性耦接至路由電路21，且封埋於模封材25中。該堆疊式半導體次組體20是藉由具導熱性之導電材38貼附於散熱座35上，其中具導熱性之導電材38係與散熱座35、第一裝置22、金屬柱24及模封材25接觸。
圖29為接合線41接至堆疊式半導體次組體20及線路板30之剖視圖。接合線41接觸並電性耦接至路由電路21之路由線212及第一線路結構31之導線343。
圖30為線路板30上設置垂直連接件58之剖視圖。垂直連接件58電性耦接至第一線路結構31之導線343，並與第一線路結構31之導線343接觸。於此實施態樣中，該些垂直連接件58是繪示成焊球581。
圖31為設有密封材51之剖視圖。該密封材51由上方覆蓋垂直連接件58側壁、接合線41、堆疊式半導體次組體20及線路板30。 據此，已完成之半導體組體310包括堆疊式半導體次組體20、線路板30、接合線41、密封材51及垂直連接件58。於此圖中，該堆疊式半導體次組體20包括路由電路21、第一裝置22、被動元件23、金屬柱24、模封材25及第二裝置27，而線路板30包括第一線路結構31、散熱座35及第二線路結構36。
第一裝置22/被動元件23及第二裝置27分別設置於路由電路21之相反兩側處，並藉由兩者間之路由電路21，面朝面地相互電性連接。金屬柱24電性連接至路由電路21，並延伸穿過模封材25。該散熱座35電性連接至金屬柱24，以構成接地連接，並與第一裝置22熱性導通，以進行散熱。第一線路結構31與第二線路結構36整體係藉由接合線41，電性耦接至路由電路21，並藉由金屬化盲孔364，電性耦接至散熱座35。垂直連接件58接置於第一線路結構31上，並與第一線路結構31電性耦接，且密封材51側向環繞垂直連接件58。
圖32為圖31半導體組體310更設有第三裝置61之剖視圖。第三裝置61堆疊於密封材51上方，並藉由焊球71電性耦接至密封材51中之垂直連接件58。
圖33為圖32半導體組體310更設有焊球73之剖視圖。該些焊球73接置於第二線路結構36之導線363上，用以外部連接。
圖34為本發明第三實施例中另一半導體組體態樣之剖視圖。該半導體組體320與圖31所示結構相似，惟不同處在於，該密封材51的厚度大於焊球581，且密封材51具有開孔511，以由上方顯露焊球581。
圖35為本發明第三實施例中再一半導體組體態樣之剖視圖。該半導體組體330與圖31所示結構相似，惟不同處在於，其包含有金屬柱583作為垂直連接件58。
[實施例4]
圖36-37為本發明第四實施態樣中，第二裝置打線至路由電路之半導體組體製作方法圖。
為了簡要說明之目的，上述實施例中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。
圖36為堆疊式半導體次組體20之剖視圖。該堆疊式半導體次組體20類似於圖7所示之結構，不同處在於，該第二裝置27是透過接合線276，電性耦接至路由電路21之路由線212。
圖37為透過接合線41將圖36堆疊式半導體次組體20電性耦接至圖10線路板30之半導體組體410剖視圖。該堆疊式半導體次組體20設置於線路板30之凹穴316中，並利用導熱材39貼附至散熱座35。接合線41接觸並電性耦接至路由電路21之路由線212及第一線路結構31之導線343。
圖38為圖37半導體組體410更設有密封材51之剖視圖。該密封材51由上方覆蓋接合線41、堆疊式半導體組體20及線路板30之選定部位，並進一步填滿堆疊式半導體組體20外圍邊緣與線路板30內部側壁間的間隙317。
圖39為圖38半導體組體410更設有第三裝置61堆疊於堆疊式半導體次組體20與線路板30第一線路結構31上之剖視圖。第三裝置61係藉由焊球71，電性耦接至第一線路結構31之導線343。
圖40為顛倒的圖38半導體組體410更設有第三裝置61、焊球73及散熱座81之剖視圖，其中第三裝置61與散熱座81位於第二線路結構36處，而焊球73位於第一線路結構31處。第三裝置61容置於散熱座81之凹穴811內，且藉由焊球71，電性耦接至第二線路結構36之導線363。散熱座81藉由導熱材89與第三裝置61熱性導通，並藉由焊球75電性耦接至第二線路結構36之導線363。焊球73接置於第一線路結構31之導線343上，用以外部連接。
[實施例5]
圖41為本發明第五實施態樣之半導體組體剖視圖。
該半導體組體510類似於圖12所示之結構，不同處在於，(i)該堆疊式半導體次組體20更包括電性耦接至路由電路21並封埋於模封材25中之被動元件23，(ii)線路板30之第一線路結構31具有較厚的厚度，以構成較深的凹穴316，並使堆疊式半導體次組體20之路由電路21及第二裝置27皆延伸進入線路板30之凹穴316中。
圖42為圖41半導體組體510更設有第三裝置61於第一線路結構31處及焊球73於第二線路結構36處之剖視圖。該第三裝置61堆疊於堆疊式半導體次組體20及線路板30之上方，並藉由焊球71電性耦接至第一線路結構31。焊球73接置於第二線路結構36上，並電性耦接至第二線路結構36，用以外部連接。
圖43為圖41半導體組體510更設有透鏡88於第一線路結構31處及焊球73於第二線路結構36處之剖視圖。透鏡88(對至少一光波長範圍呈透光)堆疊於堆疊式半導體次組體20上方，並藉由接合材881接置於第一線路結構31。焊球73接置於第二線路結構36上，並電性耦接至第二線路結構36，用以外部連接。透鏡88之材料舉例包括，但不限於，多晶陶瓷(如氧化鋁陶瓷、氮氧化鋁、鈣鈦礦、多晶釔鋁石榴石等)、單晶陶瓷、非晶材料(如無機玻璃及聚合物)、玻璃陶瓷(如矽酸鹽類)。接合材881可為金屬類材料(如焊料)、環氧類材料、聚醯亞胺、任何其他樹脂或合適材料。
[實施例6]
圖44為本發明第六實施態樣之半導體組體剖視圖。
該半導體組體610類似於圖37所示之結構，不同處在於，(i)該堆疊式半導體次組體20更包括電性耦接至路由電路21並封埋於模封材25中之被動元件23，(ii)線路板30之第一線路結構31具有較厚的厚度，以構成較深的凹穴316，並使堆疊式半導體次組體20之路由電路21及第二裝置27皆延伸進入線路板30之凹穴316中。
圖45為圖44半導體組體610更設有第三裝置61於第一線路結構31處及焊球73於第二線路結構36處之剖視圖。該第三裝置61堆疊於堆疊式半導體次組體20及線路板30之上方，並藉由焊球71電性耦接至第一線路結構31。焊球73接置於第二線路結構36上，並電性耦接至第二線路結構36，用以外部連接。
圖46為圖44半導體組體610更設有透鏡88於第一線路結構31處及焊球73於第二線路結構36處之剖視圖。透鏡88(對至少一光波長範圍呈透光)堆疊於堆疊式半導體次組體20上方，並接置於第一線路結構31。焊球73接置於第二線路結構36上，並電性耦接至第二線路結構36，用以外部連接。
上述半導體組體僅為說明範例，本發明尚可透過其他多種實施例實現。此外，上述實施例可基於設計及可靠度之考量，彼此混合搭配使用或與其他實施例混合搭配使用。舉例來說，第一線路結構可包括排列成陣列形狀之多個貫穿開口，且每一堆疊式半導體次組體容置於其對應之貫穿開口中。另外，線路板之第一線路結構可包括額外導線，以連接額外堆疊式半導體次組體。
如上實施態樣所示，本發明建構出一種獨特之半導體組體，其包括藉由接合線相互電性耦接之堆疊式半導體次組體及線路板。可選擇性地更包括一密封材，以覆蓋接合線。為方便下文描述，在此將路由電路及第一線路結構之第一表面所面向的方向定義為第一方向，而路由電路及第一線路結構之第二表面所面向的方向定義為第二方向。
該堆疊式半導體次組體包括一第一裝置、一第二裝置、一路由電路及一選擇性之模封材，其可藉由下述步驟製成：藉由如凸塊，將第一裝置電性耦接至路由電路之第一表面，其中路由電路係可拆分式地接置於一犧牲載板上；選擇性提供一模封材於路由電路上；從路由電路移除犧牲載板；以及藉由如凸塊或接合線，將第二裝置電性耦接至路由電路之第二表面。據此，分別設置於路由電路第一表面及第二表面上之第一裝置及第二裝置，可藉由路由電路相互電性連接。
第一裝置及第二裝置可為半導體晶片、已封裝元件或被動元件。在此，第一裝置可利用習知覆晶接合製程，以主動面朝向路由電路之方式，藉由凸塊電性耦接至路由電路，且未有金屬化盲孔接觸第一裝置。同樣地，於移除犧牲載板後，主動面朝向路由電路之第二裝置亦可利用習知覆晶接合製程，藉由凸塊電性耦接至路由電路，且未有金屬化盲孔接觸第二裝置。或者，主動面背向路由電路之第二裝置亦可利用打線製程，電性耦接至路由電路。
路由電路可為不具核心層之增層電路，以提供初步扇出路由/互連，以及第一及第二裝置間之最短互連距離。較佳為，該路由電路為多層增層電路，其可包括至少一介電層及導線，該些導線填滿介電層中之盲孔，並側向延伸於介電層上。介電層與導線係連續輪流形成，且需要的話可重覆形成。據此，路由電路於第一表面及第二表面處形成有電性接點，以供第一裝置從第一表面連接，以及供第二裝置及下一級連接件從第二表面連接。
該線路板包括一散熱座、一第一線路結構及一第二線路結構。該第一線路結構於第二表面處包含有電性接點，以供路由電路從第二方向連接，而該第二線路結構於外表面處包含有電性接點，用以從第一方向進行下一級連接。該第一線路結構具有一貫穿開口，其從第一表面延伸至第二表面，用以容置散熱座及堆疊式半導體次組體於其中。該第一線路結構並不限於特定結構，其可為多層路由電路，並側向環繞第一裝置、選擇性模封材及散熱座之外圍邊緣。舉例說明，該第一線路結構可包括一互連基板、一第一增層電路及一第二增層電路。第一增層電路及第二增層電路分別設置於互連基板之相反兩側上。互連基板可包括一核心層、分別設於核心層相反兩側上之第一及第二路由層、及貫穿核心層之金屬化貫孔，其中金屬化貫孔可提供第一路由層與第二路由層間之電性連接。第一及第二增層電路通常各自包括一介電層及一或多導線。第一及第二增層電路之介電層分別設置於互連基板之相反兩側上。導線側向延伸於介電層上，並包括導電盲孔，該些導電盲孔接觸互連基板之第一及第二路由層。此外，若需要更多信號路由，第一及第二增層電路可包括額外的介電層、額外的盲孔、及額外導線。第一及第二增層電路中位於第一及第二表面之最外層導線可容置導電接點，以供路由電路從第二表面連接，以及供第二線路結構從第一表面連接。第二線路結構覆蓋散熱座之背側表面及第一線路結構之第一表面，並藉由嵌埋於第二線路結構介電層中之金屬化盲孔，電性耦接至散熱座及第一線路結構，其中該些金屬化盲孔會接觸散熱座之背側表面及第一線路結構之第一表面。據此，第二線路結構之介電層會從第一方向覆蓋散熱座，且第二線路結構可對散熱座提供機械支撐，而散熱座可對藉由導熱材貼附於散熱座上之第一裝置提供散熱及電磁屏蔽。由於散熱座之厚度小於第一線路結構之厚度，故形成於線路板中之凹穴可用來容置堆疊式半導體次組體。較佳為，該散熱座為一金屬層，且金屬層的外圍邊緣鄰接且貼附至第一線路結構貫穿開口之側壁。此外，可選擇性地更包括一額外金屬層，其與散熱座及第一線路結構貫穿開口之側壁接觸，並完全覆蓋第一線路結構貫穿開口側壁之剩餘部位。第二線路結構可為多層路由電路，並側向延伸至第一線路結構之外圍邊緣。較佳為，該第二線路結構為不具核心層之多層增層電路，其包括重複交替形成之介電層及導線。導線包含有位於介電層中之金屬化盲孔，並側向延伸於介電層上。第一線路結構及第二線路結構之最外層導線可分別容置導電接點，例如焊球或接合線，以與組體、電子元件、額外散熱座、額外線路板或其他元件電性傳輸及機械性連接。例如，可將第三裝置(可為一半導體晶片)接置於第二線路結構上，並藉由複數接合線，將第三裝置電性耦接至第二線路結構；或者，該第三裝置可為球柵陣列封裝或凸塊化晶片，並藉由複數焊球，接置並電性耦接至第一線路結構或第二線路結構。於本發明另一態樣中，可進一步於第一線路結構之第二表面上接置另一額外散熱座，且第二裝置可設置於該額外散熱座之凹穴內，並藉由導熱材以與額外散熱座熱性導通。此外，該額外散熱座可藉由如焊球，電性耦接至第一線路結構，以構成接地連接，其中焊球可接觸該額外散熱座及第一線路結構之最外層導線。或者，可進一步於堆疊式半導體次組體及線路板上堆疊另一額外線路板，且該額外線路板可從第一線路結構之第二表面電性耦接至第一線路結構。更具體地說，該額外線路板可包括一第三線路結構、一第四線路結構及一額外散熱座。該第三線路結構具有一貫穿開口，其從第一表面延伸至第二表面，用以容置該額外散熱座及第二裝置於其中。較佳為，第三線路結構為多層路由電路，並側向環繞額外散熱座之外圍邊緣及次組體位於第一線路結構貫穿開口外的部份。舉例說明，該第三線路結構可包括一互連基板，其具有一核心層、分別設於核心層相反兩側上之路由層、及貫穿核心層之金屬化貫孔，其中金屬化貫孔可提供兩側路由層間之電性連接。或者，該第三線路結構可為不具核心層之多層增層電路，其包括重覆交替形成之介電層及導線。據此，第三線路結構可於其相反的第一表面及第二表面處包含有電性接點，以與第一線路結構及第四線路結構電性連接。更進一步說，第三線路結構可藉由如焊球，電性耦接至第一線路結構，其中焊球位於第一線路結構之第二表面與第三線路結構之第一表面間，而第四線路結構則可藉由金屬化盲孔，電性耦接至第三線路結構之第二表面。此外，第四線路結構亦可藉由金屬化盲孔，與設於第三線路結構貫穿開口中之散熱座電性耦接，以構成接地連接。因此，當次組體之第二裝置設置於第三線路結構之貫穿開口中時，該額外線路板中之散熱座可對第二裝置(藉由導熱材貼附於散熱座)提供散熱及電磁屏蔽。較佳為，第四線路結構為多層路由電路，並側向延伸至第三線路結構之外圍邊緣。舉例說明，該第四線路結構可為不具核心層之多層增層電路，其包括重覆交替形成之介電層及導線。據此，第四線路結構可於其外表面處包含有導線，以從第二方向提供電性接點，且可選擇性地將第三裝置堆疊於第四線路結構之外表面上，並使第三裝置電性耦接至第四線路結構之外表面。另外，當該堆疊式半導體次組體為光學次組體時，可將對至少一光波長範圍具透光性之透鏡堆疊於次組體上，並接置於線路板之第一線路結構上。
接合線提供次組體中路由電路與線路板中第一線路結構間之電性連接。於一較佳實施例中，該些接合線接觸並接置於路由電路之第二表面及第一線路結構之第二表面，其中路由電路的第二表面會從第一線路結構之貫穿開口顯露。據此，第一及第二裝置可藉由路由電路及接合線，電性連接至用於外部連接之線路板。
更可選擇性提供一系列垂直連接件，其電性連接至線路板，用於下一級連接。較佳為，該些垂直連接件是由第一線路結構之第二表面，接觸並電性耦接至第一線路結構。該些垂直連接件可包括金屬柱、焊球或其他連接件，且被密封材側向覆蓋。由於垂直連接件之一選定部位未被密封材覆蓋，故可將第三裝置電性耦接至垂直連接件。
「覆蓋」一詞意指於垂直及/或側面方向上不完全以及完全覆蓋。例如，於一較佳實施態樣中，散熱座係於第一方向覆蓋第一裝置，不論另一元件例如導熱材是否位於第一裝置與散熱座間。
「貼附於…上」及「接置於…上」一詞包括與單一或多個元件間之接觸與非接觸。例如，於一較佳實施態樣中，散熱座之外圍邊緣貼附至貫穿開口之側壁，不論散熱座之外圍邊緣是否與貫穿開口之側壁接觸或以一黏著劑相隔。
「電性連接」、以及「電性耦接」之詞意指直接或間接電性連接。例如，於一較佳實施態樣中，接合線直接接觸並且電性連接至第一線路結構，而路由電路與第一線路結構保持距離，並且路由電路係藉由接合線而電性連接至第一線路結構。
「第一方向」及「第二方向」並非取決於半導體組體之定向，凡熟悉此項技藝之人士即可輕易瞭解其實際所指之方向。例如，路由電路及第一線路結構之第一表面係面朝第一方向，而路由電路及第一線路結構之第二表面係面朝第二方向，此與半導體組體是否倒置無關。因此，該第一及第二方向係彼此相反且垂直於側面方向。此外，當第二線路結構之外表面朝向上方向時，則第一方向為向上方向，而第二方向為向下方向，當第二線路結構之外表面朝向下方向時，第一方向則為向下方向，而第二方向為向上方向。
本發明之半導體組體具有許多優點。舉例來說，將第一及第二裝置接置於路由電路之相對兩側上，可於第一裝置與第二裝置間提供最短的互連距離。路由電路可對第一裝置與第二裝置提供初級的扇出路由/互連，而線路板可提供第二級的扇出路由/互連。由於次組體之路由電路是藉由接合線，連接至線路板之第一線路結構，而不是直接藉由增層製程進行連接，故此簡化的製程步驟可降低製作成本。散熱座可提供第一裝置之散熱、電磁屏蔽、以及濕氣阻障。第二線路結構可提供散熱座機械支撐，並將熱從散熱座散出。藉由此方法製備成的半導體組體係為可靠度高、價格低廉、且非常適合大量製造生產。
本發明之製作方法具有高度適用性，且係以獨特、進步之方式結合運用各種成熟之電性及機械性連接技術。此外，本發明之製作方法不需昂貴工具即可實施。因此，相較於傳統技術，此製作方法可大幅提升產量、良率、效能與成本效益。
在此所述之實施例係為例示之用，其中該些實施例可能會簡化或省略本技術領域已熟知之元件或步驟，以免模糊本發明之特點。同樣地，為使圖式清晰，圖式亦可能省略重覆或非必要之元件及元件符號。
110、210、310、320、330、410、510、610‧‧‧半導體組體
10‧‧‧犧牲載板
20‧‧‧堆疊式半導體次組體
201、311、911‧‧‧第一表面
202、312、912‧‧‧第二表面
21‧‧‧路由電路
212‧‧‧路由線
215、331、341、361、911、 961‧‧‧介電層
216‧‧‧盲孔
217、333、343、363、913、963‧‧‧導線
218、334、344、364、964‧‧‧金屬化盲孔
22‧‧‧第一裝置
223‧‧‧第一凸塊
23、65‧‧‧被動元件
24、583‧‧‧金屬柱
25‧‧‧模封材
27‧‧‧第二裝置
273‧‧‧第二凸塊
276、41‧‧‧接合線
30、90‧‧‧線路板
31‧‧‧第一線路結構
315、915‧‧‧貫穿開口
316、811‧‧‧凹穴
317‧‧‧間隙
32‧‧‧互連基板
321‧‧‧核心層
323‧‧‧第一路由層
324‧‧‧第二路由層
327、927‧‧‧金屬化貫孔
33‧‧‧第一增層電路
34‧‧‧第二增層電路
35、81、95‧‧‧散熱座
351、952‧‧‧背側表面
36‧‧‧第二線路結構
366‧‧‧導熱墊
37‧‧‧金屬層
38‧‧‧導電材
39、89、99‧‧‧導熱材
51、85‧‧‧密封材
511‧‧‧開孔
58‧‧‧垂直連接件
61‧‧‧第三裝置
71、73、75、77、581‧‧‧焊球
88‧‧‧透鏡
881‧‧‧接合材
91‧‧‧第三線路結構
921‧‧‧核心層
923‧‧‧第一路由層
924‧‧‧第二路由層
96‧‧‧第四線路結構
參考隨附圖式，本發明可藉由下述較佳實施例之詳細敘述更加清楚明瞭，其中： 圖1為本發明第一實施態樣中，於犧牲載板上形成路由線之剖視圖； 圖2為本發明第一實施態樣中，圖1結構上形成介電層及盲孔之剖視圖； 圖3為本發明第一實施態樣中，圖2結構上形成導線之剖視圖； 圖4為本發明第一實施態樣中，圖3結構上接置第一裝置之剖視圖； 圖5為本發明第一實施態樣中，圖4結構上形成模封材之剖視圖； 圖6為本發明第一實施態樣中，自圖5結構移除犧牲載板之剖視圖； 圖7為本發明第一實施態樣中，圖6結構上接置第二裝置以完成堆疊式半導體次組體製作之剖視圖； 圖8為本發明第一實施態樣中，第一線路結構之剖視圖； 圖9為本發明第一實施態樣中，圖8結構中更設置散熱座之剖視圖； 圖10為本發明第一實施態樣中，圖9結構上形成第二線路結構以完成線路板製作之剖視圖； 圖11為本發明第一實施態樣中，圖10結構上設置圖7堆疊式半導體次組體之剖視圖； 圖12為本發明第一實施態樣中，圖11結構上接置接合線以完成半導體組體製作之剖視圖； 圖13為本發明第一實施態樣中，圖12結構上形成密封材之剖視圖； 圖14為本發明第一實施態樣中，圖13結構上接置第三裝置之剖視圖； 圖15為本發明第一實施態樣中，圖14結構上接置焊球之剖視圖； 圖16為本發明第一實施態樣中，圖13結構上接置被動元件、另一散熱座及焊球之剖視圖； 圖17為本發明第一實施態樣中，顛倒的圖13結構上接置第三裝置、另一散熱座及焊球之剖視圖； 圖18為本發明第一實施態樣中，圖13結構上接置額外線路板之剖視圖； 圖19為本發明第一實施態樣中，圖18結構上接置第三裝置及焊球之剖視圖； 圖20為本發明第一實施態樣中，圖13結構上接置另一態樣之額外線路板剖視圖； 圖21為本發明第二實施態樣中，線路板之剖視圖； 圖22為本發明第二實施態樣中，圖21結構中設置圖7堆疊式半導體次組體之剖視圖； 圖23為本發明第二實施態樣中，圖22結構上接置接合線以完成半導體組體製作之剖視圖； 圖24為本發明第二實施態樣中，圖23結構上形成密封材之剖視圖； 圖25為本發明第二實施態樣中，顛倒的圖24結構上設置第三裝置及被動元件之剖視圖； 圖26為本發明第二實施態樣中，圖25結構上形成密封材之剖視圖； 圖27為本發明第二實施態樣中，圖26結構上設置焊球之剖視圖； 圖28為本發明第三實施態樣中，堆疊式半導體次組體貼附至圖10線路板之剖視圖； 圖29為本發明第三實施態樣中，圖28結構上接置接合線以完成半導體組體製作之剖視圖； 圖30為本發明第三實施態樣中，圖29結構上設置垂直連接件之剖視圖； 圖31為本發明第三實施態樣中，圖30結構上形成密封材以完成半導體組體製作之剖視圖； 圖32為本發明第三實施態樣中，圖31結構上設置第三裝置之剖視圖； 圖33為本發明第三實施態樣中，圖32結構上設置焊球之剖視圖； 圖34為本發明第三實施態樣中，另一半導體組體態樣之剖視圖； 圖35為本發明第三實施態樣中，再一半導體組體態樣之剖視圖； 圖36為本發明第四實施態樣中，堆疊式半導體次組體之剖視圖； 圖37為本發明第四實施態樣中，圖36次組體打線至圖10線路板之剖視圖； 圖38為本發明第四實施態樣中，圖37結構上形成密封材之剖視圖； 圖39為本發明第四實施態樣中，圖38結構上設置第三裝置之剖視圖； 圖40為本發明第四實施態樣中，顛倒的圖38結構上設置第三裝置、散熱座及焊球之剖視圖； 圖41為本發明第五實施態樣中，半導體組體之剖視圖； 圖42為本發明第五實施態樣中，圖41結構上設置第三裝置及焊球之剖視圖； 圖43為本發明第五實施態樣中，圖41結構上設置透鏡及焊球之剖視圖； 圖44為本發明第六實施態樣中，半導體組體之剖視圖； 圖45為本發明第六實施態樣中，圖44結構上設置第三裝置及焊球之剖視圖； 圖46為本發明第六實施態樣中，圖44結構上設置透鏡及焊球之剖視圖。

Claims (12)

  1. 一種三維整合之散熱增益型半導體組體，其包括： 　　　　　一堆疊式半導體次組體，其包括一第一裝置、一第二裝置及一路由電路，其中該第一裝置電性耦接至該路由電路之一第一表面，而該第二裝置電性耦接至該路由電路之一相反第二表面； 　　　　　一線路板，其包括一第一線路結構、一第二線路結構及一散熱座，其中(i)該第一線路結構具有一第一表面、一相反第二表面、及從該第一表面延伸至該第二表面之一貫穿開口，(ii)該散熱座設置於該貫穿開口中，且該散熱座之一背側表面與該第一線路結構之該第一表面呈實質上共平面，(iii)該第二線路結構設置於該散熱座之該背側表面及該第一線路結構之該第一表面上，並藉由金屬化盲孔電性連接至該第一線路結構且熱性導通至該散熱座，且(iv)該堆疊式半導體次組體設置於該貫穿開口中；以及 　　　　　複數接合線，其電性耦接該路由電路至該線路板。
  2. 如申請專利範圍第1項所述之半導體組體，其中，該散熱座之外圍邊緣鄰近於該貫穿開口之側壁，且該散熱座之厚度小於該貫穿開口之深度，該堆疊式半導體次組體藉由一導熱材，使該第一裝置貼附於該散熱座上。
  3. 如申請專利範圍第1項所述之半導體組體，更包括：一第三裝置，其堆疊於該第一線路結構或該第二線路結構上，並電性耦接至該第一線路結構或該第二線路結構。
  4. 如申請專利範圍第1項所述之半導體組體，更包括：一密封材，其覆蓋該些接合線。
  5. 如申請專利範圍第1項所述之半導體組體，更包括：一透鏡，其設置於該堆疊式半導體次組體上，並接置於該第一線路結構，其中該透鏡對至少一光波長範圍具透光性。
  6. 如申請專利範圍第1項所述之半導體組體，更包括：一額外線路板，其堆疊於該第一線路結構上，該額外線路板包括一第三線路結構、一第四線路結構及一額外散熱座，其中(i)該第三線路結構具有一第一表面、一相反第二表面、及從該第一表面延伸至該第二表面之一貫穿開口，(ii)該額外散熱座設置於該貫穿開口中，且該額外散熱座之一背側表面與該第三線路結構之該第二表面呈實質上共平面，(iii)該第四線路結構設置於該額外散熱座之該背側表面及該第三線路結構之該第二表面上，並藉由金屬化盲孔電性連接至該第三線路結構且熱性導通至該額外散熱座，且(iv)該第二裝置貼附至該額外散熱座，並被該第三線路結構側向環繞，而該第三線路結構則電性耦接至該第一線路結構。
  7. 如申請專利範圍第1項所述之半導體組體，更包括：另一散熱座，其電性耦接至該第一線路結構，且與該第二裝置熱性導通。
  8. 一種三維整合之散熱增益型半導體組體之製作方法，其包括： 　　　　　提供一堆疊式半導體次組體，其包括一第一裝置、一第二裝置及一路由電路，其中該第一裝置電性耦接至該路由電路之一第一表面，而該第二裝置電性耦接至該路由電路之一相反第二表面； 　　　　　提供一線路板，其包括一第一線路結構、一第二線路結構及一散熱座，其中(i)該第一線路結構具有一第一表面、一相反第二表面、及從該第一表面延伸至該第二表面之一貫穿開口，(ii)該散熱座設置於該貫穿開口中，且該散熱座之一背側表面與該第一線路結構之該第一表面呈實質上共平面，且(iii)該第二線路結構設置於該散熱座之該背側表面及該第一線路結構之該第一表面上，並藉由金屬化盲孔電性連接至該第一線路結構且熱性導通至該散熱座； 　　　　　將該堆疊式半導體次組體設置於該第一線路結構之該貫穿開口中及該散熱座上；以及 提供複數接合線，以電性耦接該路由電路及該線路板。
  9. 如申請專利範圍第8項所述之製作方法，更包括一步驟：將一第三裝置堆疊於該第一線路結構或該第二線路結構上，且使該第三裝置電性耦接至該線路板。
  10. 如申請專利範圍第8項所述之製作方法，更包括以下步驟： 提供一額外線路板，其包括一第三線路結構、一第四線路結構及一額外散熱座，其中(i)該第三線路結構具有一第一表面、一相反第二表面、及從該第一表面延伸至該第二表面之一貫穿開口，(ii)該額外散熱座設置於該貫穿開口中，且該額外散熱座之一背側表面與該第三線路結構之該第二表面呈實質上共平面，且(iii)該第四線路結構設置於該額外散熱座之該背側表面及該第三線路結構之該第二表面上，並藉由金屬化盲孔電性連接至該第三線路結構且熱性導通至該額外散熱座；以及 將該額外線路板堆疊於該第一線路結構上，並使該第三線路結構電性耦接至該第一線路結構，且該第二裝置貼附至該額外散熱座，並被該第三線路結構側向環繞。
  11. 如申請專利範圍第8項所述之製作方法，更包括一步驟：堆疊另一散熱座於該第一線路結構上，其中該另一散熱座電性耦接至該第一線路結構並貼附至該第二裝置。
  12. 如申請專利範圍第8項所述之製作方法，更包括一步驟：堆疊一透鏡於該堆疊式半導體次組體上，其中該透鏡接置於該第一線路結構上，且該透鏡對至少一光波長範圍具透光性。
TW107106052A 2015-05-27 2018-02-23 三維整合之散熱增益型半導體組體及其製作方法 TWI656615B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562166771P 2015-05-27 2015-05-27
US15/473629 2017-03-30
US15/473,629 US10134711B2 (en) 2015-05-27 2017-03-30 Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same

Publications (2)

Publication Number Publication Date
TW201842636A true TW201842636A (zh) 2018-12-01
TWI656615B TWI656615B (zh) 2019-04-11

Family

ID=57398959

Family Applications (2)

Application Number Title Priority Date Filing Date
TW105116541A TWI650846B (zh) 2015-05-27 2016-05-27 內建散熱座之散熱增益型面朝面半導體組體及製作方法
TW107106052A TWI656615B (zh) 2015-05-27 2018-02-23 三維整合之散熱增益型半導體組體及其製作方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW105116541A TWI650846B (zh) 2015-05-27 2016-05-27 內建散熱座之散熱增益型面朝面半導體組體及製作方法

Country Status (3)

Country Link
US (2) US10121768B2 (zh)
CN (2) CN106206488B (zh)
TW (2) TWI650846B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115066746A (zh) * 2020-02-12 2022-09-16 华为技术有限公司 封装结构及其制备方法和电子设备

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102565119B1 (ko) * 2016-08-25 2023-08-08 삼성전기주식회사 전자 소자 내장 기판과 그 제조 방법 및 전자 소자 모듈
CN108400118A (zh) * 2017-02-06 2018-08-14 钰桥半导体股份有限公司 三维整合的半导体组件及其制作方法
CN108400117A (zh) * 2017-02-06 2018-08-14 钰桥半导体股份有限公司 三维整合的散热增益型半导体组件及其制作方法
TWI641095B (zh) * 2017-08-30 2018-11-11 欣興電子股份有限公司 散熱基板的結構及製造方法與封裝結構與方法
FR3079068B1 (fr) * 2018-03-13 2023-05-26 St Microelectronics Grenoble 2 Dispositifs electroniques et procedes de fabrication
CN110364496A (zh) * 2018-04-11 2019-10-22 中国科学院微电子研究所 一种芯片封装结构及其封装方法
US11227841B2 (en) * 2018-06-28 2022-01-18 Intel Corporation Stiffener build-up layer package
US10825781B2 (en) * 2018-08-01 2020-11-03 Nxp B.V. Semiconductor device with conductive film shielding
DE102019117844A1 (de) 2018-09-27 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltung-package und verfahren
US10790162B2 (en) * 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
KR102524812B1 (ko) * 2018-11-06 2023-04-24 삼성전자주식회사 반도체 패키지
WO2020101572A1 (en) * 2018-11-12 2020-05-22 Agency For Science, Technology And Research Multi-chip system and method of forming the same
KR20200145387A (ko) * 2019-06-21 2020-12-30 에스케이하이닉스 주식회사 인터포저를 포함하는 적층 반도체 패키지
WO2021016547A1 (en) * 2019-07-25 2021-01-28 Samtec, Inc. Wirebondable interposer for flip chip packaged integrated circuit die
US11145624B2 (en) * 2019-07-26 2021-10-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
TWI791881B (zh) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其組合式基板與製法
US11296005B2 (en) 2019-09-24 2022-04-05 Analog Devices, Inc. Integrated device package including thermally conductive element and method of manufacturing same
CN110856374A (zh) * 2019-11-28 2020-02-28 苏州晶鼎鑫光电科技有限公司 一种用于5g光模块的陶瓷薄膜电路表面选择性制备金锡共晶焊料的方法
US12040249B2 (en) * 2019-12-31 2024-07-16 Texas Instruments Incorporated Packages with separate communication and heat dissipation paths
US11699662B2 (en) 2020-01-23 2023-07-11 Nvidia Corporation Face-to-face dies with probe pads for pre-assembly testing
US11127719B2 (en) 2020-01-23 2021-09-21 Nvidia Corporation Face-to-face dies with enhanced power delivery using extended TSVS
US11616023B2 (en) 2020-01-23 2023-03-28 Nvidia Corporation Face-to-face dies with a void for enhanced inductor performance
US11227821B2 (en) 2020-04-21 2022-01-18 Toyota Motor Engineering & Manufacturing North America, Inc. Chip-on-chip power card with embedded thermal conductor
US11769752B2 (en) * 2020-07-24 2023-09-26 Micron Technology, Inc. Stacked semiconductor die assemblies with substrate heat sinks and associated systems and methods
US11502060B2 (en) 2020-11-20 2022-11-15 Rockwell Collins, Inc. Microelectronics package with enhanced thermal dissipation
US20230059142A1 (en) * 2021-08-17 2023-02-23 Texas Instruments Incorporated Flip chip packaged devices with thermal interposer
CN116013881B (zh) * 2023-03-28 2023-06-16 甬矽电子(宁波)股份有限公司 芯片封装结构、芯片封装结构的制备方法和打线修补方法

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583377A (en) 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5886412A (en) 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5801072A (en) 1996-03-14 1998-09-01 Lsi Logic Corporation Method of packaging integrated circuits
US5790384A (en) 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US6091138A (en) 1998-02-27 2000-07-18 Advanced Micro Devices, Inc. Multi-chip packaging using bump technology
US6150724A (en) 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6084308A (en) 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6204562B1 (en) 1999-02-11 2001-03-20 United Microelectronics Corp. Wafer-level chip scale package
JP3339838B2 (ja) 1999-06-07 2002-10-28 ローム株式会社 半導体装置およびその製造方法
JP2001024150A (ja) 1999-07-06 2001-01-26 Sony Corp 半導体装置
JP2001077293A (ja) 1999-09-02 2001-03-23 Nec Corp 半導体装置
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US7247932B1 (en) 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6432742B1 (en) 2000-08-17 2002-08-13 St Assembly Test Services Pte Ltd. Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages
US6495910B1 (en) 2000-08-25 2002-12-17 Siliconware Precision Industries Co., Ltd. Package structure for accommodating thicker semiconductor unit
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
AU2002217987A1 (en) 2000-12-01 2002-06-11 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
US6507115B2 (en) 2000-12-14 2003-01-14 International Business Machines Corporation Multi-chip integrated circuit module
US6906414B2 (en) 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US7161239B2 (en) 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6979894B1 (en) 2001-09-27 2005-12-27 Marvell International Ltd. Integrated chip package having intermediate substrate
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6861750B2 (en) 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US6659512B1 (en) 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
US7087988B2 (en) 2002-07-30 2006-08-08 Kabushiki Kaisha Toshiba Semiconductor packaging apparatus
TWI236117B (en) 2003-02-26 2005-07-11 Advanced Semiconductor Eng Semiconductor package with a heat sink
DE102006001767B4 (de) 2006-01-12 2009-04-30 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US20080042265A1 (en) 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
US7554194B2 (en) 2006-11-08 2009-06-30 Amkor Technology, Inc. Thermally enhanced semiconductor package
TWI332244B (en) 2007-01-26 2010-10-21 Taiwan Solutions Systems Corp Fabrication method of leadframe and semiconductor package
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US7919853B1 (en) 2007-11-01 2011-04-05 Amkor Technology, Inc. Semiconductor package and fabrication method thereof
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US7859120B2 (en) 2008-05-16 2010-12-28 Stats Chippac Ltd. Package system incorporating a flip-chip assembly
US8188379B2 (en) 2008-07-04 2012-05-29 Unimicron Technology Corp. Package substrate structure
US7944043B1 (en) 2008-07-08 2011-05-17 Amkor Technology, Inc. Semiconductor device having improved contact interface reliability and method therefor
US8836115B1 (en) 2008-07-31 2014-09-16 Amkor Technology, Inc. Stacked inverted flip chip package and fabrication method
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8212342B2 (en) 2009-12-10 2012-07-03 Stats Chippac Ltd. Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8654538B2 (en) 2010-03-30 2014-02-18 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US8288854B2 (en) 2010-05-19 2012-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for making the same
US20120098129A1 (en) * 2010-10-22 2012-04-26 Harris Corporation Method of making a multi-chip module having a reduced thickness and related devices
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US20120229990A1 (en) * 2011-03-08 2012-09-13 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
KR101829392B1 (ko) * 2011-08-23 2018-02-20 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US9847284B2 (en) 2013-01-29 2017-12-19 Apple Inc. Stacked wafer DDR package
US9196575B1 (en) * 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
US9252130B2 (en) 2013-03-29 2016-02-02 Stats Chippac, Ltd. Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding
TWI541954B (zh) * 2013-08-12 2016-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9147667B2 (en) * 2013-10-25 2015-09-29 Bridge Semiconductor Corporation Semiconductor device with face-to-face chips on interposer and method of manufacturing the same
CN104701187A (zh) * 2013-10-25 2015-06-10 钰桥半导体股份有限公司 半导体装置以及其制备方法
US9379078B2 (en) 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
US9318411B2 (en) * 2013-11-13 2016-04-19 Brodge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
CN103794587B (zh) * 2014-01-28 2017-05-17 江阴芯智联电子科技有限公司 一种高散热芯片嵌入式重布线封装结构及其制作方法
JP6338409B2 (ja) * 2014-03-14 2018-06-06 アルパッド株式会社 発光装置及びその製造方法
TWI611534B (zh) * 2015-09-03 2018-01-11 鈺橋半導體股份有限公司 適用於可堆疊式半導體組體之具有凹穴的互連基板、其製作方法及垂直堆疊式半導體組體
US9570372B1 (en) * 2016-03-24 2017-02-14 Bridge Semiconductor Corporation Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115066746A (zh) * 2020-02-12 2022-09-16 华为技术有限公司 封装结构及其制备方法和电子设备

Also Published As

Publication number Publication date
US20170207200A1 (en) 2017-07-20
US10134711B2 (en) 2018-11-20
TWI656615B (zh) 2019-04-11
US10121768B2 (en) 2018-11-06
TW201709474A (zh) 2017-03-01
CN106206488A (zh) 2016-12-07
US20160351549A1 (en) 2016-12-01
TWI650846B (zh) 2019-02-11
CN108695274B (zh) 2020-01-17
CN106206488B (zh) 2019-05-31
CN108695274A (zh) 2018-10-23

Similar Documents

Publication Publication Date Title
TWI656615B (zh) 三維整合之散熱增益型半導體組體及其製作方法
US10177130B2 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US10354984B2 (en) Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same
CN104882416B (zh) 具有堆叠式封装能力的半导体封装件及其制作方法
TWI619210B (zh) 介電材凹穴內設有半導體元件之面朝面半導體組體
TWI517322B (zh) 半導體元件及其製作方法
TWI594346B (zh) 半導體組體及其製作方法
US20170194300A1 (en) Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same
US20150115433A1 (en) Semiconducor device and method of manufacturing the same
US20170025393A1 (en) Thermally enhanced face-to-face semiconductor assembly with heat spreader and method of making the same
TW201705830A (zh) 介電材凹穴內設有電性元件之可堆疊式線路板製作方法
US20180374827A1 (en) Semiconductor assembly with three dimensional integration and method of making the same
US20170243803A1 (en) Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same
TW201941394A (zh) 線路基板、堆疊式半導體組體及其製作方法
TWI614855B (zh) 具有電磁屏蔽及散熱特性之半導體組體及製作方法
US20170133352A1 (en) Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same
TWI657555B (zh) 三維整合之半導體組體及其製作方法
TW201933568A (zh) 中介層及電性元件併於基底板中之線路板製法
TWI626719B (zh) 三維整合之散熱增益型半導體組體及其製作方法
TWI611530B (zh) 具有散熱座之散熱增益型面朝面半導體組體及製作方法
TW201940026A (zh) 具有嵌埋式元件及加強層之線路板、其製法及其面朝面半導體組體
TW201937673A (zh) 具有散熱特性之三維可堆疊式半導體組體
CN221282118U (zh) 一种基板和封装结构
CN108400118A (zh) 三维整合的半导体组件及其制作方法
TW201939679A (zh) 整合元件及導線架之線路板及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees