CN109659293B - 在敷金属系统中具有优越抗裂性的半导体装置 - Google Patents

在敷金属系统中具有优越抗裂性的半导体装置 Download PDF

Info

Publication number
CN109659293B
CN109659293B CN201811179911.XA CN201811179911A CN109659293B CN 109659293 B CN109659293 B CN 109659293B CN 201811179911 A CN201811179911 A CN 201811179911A CN 109659293 B CN109659293 B CN 109659293B
Authority
CN
China
Prior art keywords
semiconductor device
contact pad
metal region
metal
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811179911.XA
Other languages
English (en)
Other versions
CN109659293A (zh
Inventor
迪克·彼尔
格奥尔格·塔卢特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries US Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries US Inc filed Critical GlobalFoundries US Inc
Publication of CN109659293A publication Critical patent/CN109659293A/zh
Application granted granted Critical
Publication of CN109659293B publication Critical patent/CN109659293B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05011Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05016Shape in side view
    • H01L2224/05017Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05025Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05551Shape comprising apertures or cavities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05559Shape in side view non conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605Shape
    • H01L2224/06051Bonding areas having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/37Effects of the manufacturing process
    • H01L2924/37001Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及在敷金属系统中具有优越抗裂性的半导体装置,其中,半导体装置包含位在最后敷金属层中的非四边形金属区及/或非四边形接触垫,其中,在一些说明性具体实施例中,可获得指叉式横向组态,及/或可提供接触垫与下伏金属区的重叠。所以,可增加接触垫及下伏层间介电材料底下的钝化材料的机械稳建性,由此抑制裂纹形成及裂纹传播。

Description

在敷金属系统中具有优越抗裂性的半导体装置
技术领域
大体上,本申请关于包括敷金属(metallization)系统的半导体装置的技术及用于连接至封装件的接垫结构的技术。
背景技术
取决于复杂程度,半导体装置一般包括更多或更少数量的半导体基础电路组件,诸如场效晶体管、双极晶体管及类似者,一般与电阻器、电容器及类似者组合。在大部分方法中,这些电路组件可在对应的半导体层中及上形成,诸如硅层、硅/锗层或任何其它适当的半导体材料层,其中,可通过使用建置良好且又尖端的制造技术,诸如光刻(photolithography)、蚀刻、离子布植及类似者,根据指定设计及相关设计规则,一层接着一层地形成及/或处理相应装置图案。取决于所思半导体装置的总体复杂度,可能需要相对大量的程序步骤才能完成功能装置。举例而言,在所谓的“前段制程”(front end of line;FEOL)中,进行相应程序步骤以完成实际的半导体基础电路组件,诸如晶体管及类似者,其中,在尖端应用中,可制造30nm或更小关键尺寸的晶体管组件,由此为实施非常大量电路组件提供可能性,并因此在单芯片中组配整个系统。之后,可钝化先前形成的半导体基础电路组件,诸如晶体管、电阻器及类似者,并且尤其可通过提供所谓的接触组件使该等电路组件彼此互连,该等接触组件可在适当的介电材料中形成,以便可靠地包覆先前制作的电路组件。
其次,必须通过提供适当的介电材料并在其中形成金属及接触贯孔来形成敷金属系统,由此提供含高导电金属的连接的“组构”,类似于多层阶印刷电路板,以便建立为了获得所欲功能行为所需的电连接。大体上,在复杂敷金属系统中,可能必须实施二或更多个敷金属层,才能在个别电路组件之间提供所需数量的电连接,因为一般而言,相对装置阶中实施的电路组件数量,所需的连接数量增加比例更高。
再者,由于敷金属系统中的电连接可能对完成的半导体装置的整体效能具有显著影响,因此已开发尖端材料及技术,以便形成具有更小横向尺寸但效能高的高导电金属线及贯孔,从而一般而言,需要搭配适当设计的材料,诸如具有介电常数为3.7或更低的所谓低k介电材料,合并高导电金属,诸如铜、铜合金及类似者。所以,在许多情况下,产生的敷金属系统代表敷金属层的复杂堆栈,其中至少一些敷金属层可基于关键材料形成,相比于传统介电材料,诸如二氧化硅、氮化硅及类似者,机械稳定性较不明显。所以,当进一步处理期间或操作此类半导体装置(包括相应敷金属系统)期间遭遇某些负载时,可观察到半导体装置的良率损失及/或过早疲劳,其可能常因敏感介电材料中形成裂纹所造成,这不仅可能导致机械稳定性降低,还可能使敷金属系统的相应部分电气强度降低。
常可通过与连接至敷金属系统并使之钝化的最终层或钝化层交互作用,将实质机械应力引入敏感敷金属系统,其可包含相对环境条件及类似者提供所需稳建性的适当钝化材料,并且还可在其中形成相应接触垫,接触垫可用于将所思半导体装置连接至其它组件,诸如封装件、任何其它适当的载体材料、为了形成三维芯片组态的其它半导体装置、以及类似者。亦即,相应接触垫的配置乃为了针对与环境的机械、电及热交互作用向外界提供通讯而设计。举例而言,一种用于使半导体装置与环境通讯的常用方法是将半导体芯片并入封装件,并且通过打线向封装件或其接脚(pins)提供电接触,其中可通过施压及施热,将适当的金属线,诸如铜线及类似者,连接至相应接触垫,亦称为接合垫。举例而言,打线已经成为用于半导体装置的非常成熟且经济的技术,其中,无论内部复杂度如何,需要与环境接触的数量都相对有限。
在其它接触技术中,半导体装置与载体或封装基材之间的电气及机械接触可通过焊接技术来建立,其中相应焊块可设于封装基材及半导体装置其中至少一者中,而实际连接则可基于焊接程序建立。同样,在这种情况下,可在半导体装置的钝化阶中诱发显著机械应力,钝化阶可包含聚亚酰胺及类似者,具有优越钝化特性,但曝露于机械应力时呈现较脆的行为。所以,在常可由铝所构成的相应接触垫的配置中,可能产生应力,举例来说,形式为拉伸应力,常由铝接触垫与周围钝化介电材料间热膨胀系数的显著差异所促进。相应裂纹可接着在拉伸应力的影响下传播,并且可到达横置于更深处的敷金属层,当已可在其中使用尖端介电材料时尤其如此。如上述,敷金属系统中的任何此类裂纹相关缺陷都可能导致所思半导体装置损失良率、过早疲劳或降低可靠度。
在许多方法中,相应接触垫可能必须在钝化阶中以紧密间隔置放才能符合设计准则,使得举例来说,提供相应接合垫作为实质“隔离”结构以增强机械稳健性可能不代表可行选项。在其它情况下,除了接触垫以外,例如对于RF应用,可能还必须常实施较厚金属线,从而甚至进一步加剧钝化层及下伏敷金属层中裂纹形成的问题。
举例而言,美国专利第8,860,224号揭示一种在顶端金属层上方形成超厚金属(ultra-thick metal;UTM)线的半导体装置,其中形成钝化材料以便相比于金属层呈现特定厚度,试图使敷金属失效减少。
美国公开专利第2013/0320522号揭示一种在基材上方形成有接触垫的半导体装置,其中第一钝化层中形成贯孔,以便以专门设计的贯孔几何形态为基础,将接触垫连接至最后敷金属层的金属区。
美国公开专利第2015/0061156号揭示一种用于通过使半导体装置的钝化层中的介电层数量减少来形成接合垫的制造技术,举例来说,用于打线,然而,并未专门解决钝化材料及位于钝化层下面的敷金属层的裂纹形成问题。
鉴于上述情况,本申请因此关于半导体装置及制造技术,其中可在钝化材料中形成接触垫,诸如接合垫及类似者,同时避免或至少减小上面所指认的一或多个问题的效应。
发明内容
以下介绍本申请的简化概要,以便对本发明的一些态样有基本的了解。本概要并非本发明的详尽概述。用意不在于指认本发明的重要或关键要素,或叙述本发明的范畴。目的仅在于以简化形式介绍一些概念,作为下文更详细说明的引言。
为了降低裂纹形成及传播的可能性,本申请乃基于如下概念:相邻接触垫及/或必须与该等接触垫连接的相邻下伏金属区经过适当设计可实现本质上可使裂纹形成且尤其是裂纹传播可能性降低的组态。亦即,根据本申请的原理,极最后敷金属层的相邻连接垫或金属区的某一程度的横向指叉、及/或接触垫与两个下伏金属区的特定重叠可导致机械稳建性更大的构造,并且可另外导致某一程度的压缩应力,从而降低形成裂纹的趋势,即使在例如打线、焊接、制作及使用半导体装置期间的热循环及类似过程中蒙受外部应力分量时亦然。再者,通过提供压缩应力促进极最后敷金属层的金属区及/或接触垫的整体横向设计,虽然可能形成某一程度的裂纹,仍可有效率地抑制裂纹传播。
本文中所揭示的一项说明性具体实施例中提供一种半导体装置。该半导体装置包括敷金属系统,该敷金属系统包括最后敷金属层,该最后敷金属层包含第一金属区及第二金属区,其中第二金属区与第一金属区横向分开并且相邻于第一金属区。该半导体装置更包括最后敷金属层上面形成的钝化层。再者,钝化层中形成第一接触垫,以便与第一金属区接触。另外,该半导体装置包括为了与第二金属区接触并与第一金属区的一部分重叠而在相邻于第一接触垫的钝化层中形成的第二接触垫。
根据本文中所揭示的另一说明性具体实施例,提供一种半导体装置。该半导体装置包括敷金属系统,该敷金属系统包括最后敷金属层,该最后敷金属层包含第一金属区、及与第一金属区横向分开并且相邻于第一金属区的第二金属区。再者,该半导体装置包括最后敷金属层上面形成的钝化层。另外,该半导体装置包括在钝化层中形成的第一接触垫,以便与第一金属区接触。此外,该半导体装置包括为了与第二金属区接触而在相邻于第一接触垫的钝化层中形成的第二接触垫,其中第一金属区及/或第一接触垫具有非四边形横向形状。
根据本文中所揭示的一再进一步具体实施例,提供一种方法。该方法包括在半导体装置的敷金属系统的最后敷金属层的介电材料中形成第一金属区及第二金属区,第一与第二金属区适于连接至不同电位;以及在钝化层中形成第一与第二接触垫,其中第一与第二接触垫导电耦接至第一与第二金属区,并且其中第一接触垫与第二金属区重叠。
附图说明
本申请可搭配附图参照以下说明来了解,其中相似的附图标记表示相似的组件,并且其中:
图1A及图1B根据据信尤其在钝化材料下面形成的介电材料中促进裂纹形成的传统设计,分别示意性绘示半导体装置的俯视图及截面图,该半导体装置包括敷金属系统及钝化层,该钝化层包括接触垫;
图2A及图2B根据说明性具体实施例,分别示意性绘示半导体装置、以及接触垫及最后敷金属层的金属区的对应设计的俯视图及截面图,以便提供用于使尤其最后敷金属层中及下面使用的脆性层间介电材料的机械稳建性强化的重叠部分;
图2C示意性绘示图2A及图2B的半导体装置的最后敷金属层的俯视图;
图3A及图3B根据进一步说明性具体实施例,分别示意性绘示设计及对应半导体装置的俯视图及截面图,其中重叠部分可基于接触垫及/或金属区的对置边缘区的指叉式”组态来达成;
图3C根据说明性具体实施例,示意性绘示半导体装置的最后敷金属层中的金属区的设计的俯视图,其包括彼此面向的边缘区,并且基于四边形凸出物形成指叉式组态;
图3D根据进一步说明性具体实施例,在俯视图中示意性绘示设计及相应半导体装置,其中重叠及指叉式组态通过使用在相邻金属区及相邻接触垫中具有四边形凸出物的边缘区来获得;
图3E根据进一步说明性具体实施例,示意性绘示设计及半导体装置的俯视图,其中最后敷金属层的金属区的相邻边缘区的指叉式组态以实质线性边缘区的接触垫为基础,搭配重叠所获得;
图3F根据说明性具体实施例,示意性绘示设计及半导体装置的俯视图,其中最后敷金属层中的邻接金属区及接触垫两者中都获得指叉式组态,其中指叉式几何形态在各对金属区/接触垫中具有实质相同的渐进过程;以及
图4示意性绘示包括敷金属系统及钝化层的半导体装置的截面图,该钝化层包括根据如上述的设计及程序技术形成的接触垫。
尽管本文中所揭示的专利目标易受各种修改和替代形式所影响,其特定具体实施例仍已通过图式中的实施例予以表示并且在本文中予以详述。然而,应了解的是,本文中特定具体实施例的说明用意不在于将本发明限制于所揭示的特定形式,相反地,如随附权利要求书所界定,用意在于涵盖落于本发明的精神及范畴内的所有修改、均等例、及替代方案。
主要附图标记说明
100 半导体装置
101 裂纹
110A 接触垫、第一接触垫或第一连接垫
110B 接触垫、第二接触垫
110S 间隔
111A、111B 贯孔
112 边缘区
120 钝化层或钝化阶
121 钝化材料
122、141 介电材料、敏感材料或敏感介电材料
140 敷金属层
140A 金属区、下伏金属区或第一金属区
140B 金属区、下伏金属区或第二金属区
150 敷金属系统
200 半导体装置
201 裂纹
210A 接触垫、第一接触垫或第一连接垫
210B 接触垫或第二接触垫
210S 间隔
211A、211B 贯孔
214A 凸出物
215 转角部分或转角
220 钝化阶或钝化层
221 钝化材料
240A、240B、240C 金属区
241 介电材料
244B、244C 凸出物
245 转角
250 敷金属系统
300 半导体装置
310A、310B 接触垫
311A、311B 贯孔
314A、314B 凸出物
312 边缘或边缘区
320 钝化阶
321 钝化材料
340 敷金属层
340A、340B 金属区或下伏金属区
341 介电材料
344A、344B 凸出物
350 敷金属系统
400 半导体装置
401 基材
402 半导体层或半导体材料
403 接触阶
404 电路组件
405 接触组件
410A、410B、410C 接触垫
411A、411B、411C 贯孔
417 接触表面或接触表面区
420 钝化层或钝化阶
421 钝化材料
440 敷金属层
440A、440B、440C 金属区
441 介电材料
450 敷金属系统
460 敷金属层或第一敷金属层
460A 金属线
461、471、481 介电材料
470、480 敷金属层
470A、480A 金属区。
具体实施方式
在底下的说明中,为了解释,提出许多特定细节以便透彻理解例示性具体实施例。然而,应显而易知的是,没有这些特定细节或利用均等配置也可实践例示性具体实施例。在其它实例中,众所周知的结构及装置是以方块图形式来展示,为的是要避免不必要地混淆例示性具体实施例。另外,除非另有所指,本说明书及权利要求书中用来表达成分、反应条件等等的量、比率、及数值特性的所有数字都要了解为在所有实例中是以“约”一语来修饰。
下面说明本发明的各项说明性具体实施例。为了澄清,本说明书中并未说明实际实作态样的所有特征。当然,将会领会的是,在开发任何此实际具体实施例时,必须作出许多实作态样特定决策才能达到开发者的特定目的,例如符合系统有关及业务有关的限制条件,这些限制条件会随实作态样不同而变。此外,将会领会的是,此一开发努力可能复杂且耗时,虽然如此,仍会是受益于本申请的所属技术领域中具有通常知识者的例行工作。
本申请现将参照附图来说明。各种结构、系统及装置在图式中只是为了阐释而绘示,为的是不要因所属技术领域中具有通常知识者众所周知的细节而混淆本申请。虽然如此,仍将附图包括进来以说明并阐释本申请的说明性实施例。本文中使用的字组及词组应了解并诠释为与所属技术领域中具有通常知识者了解的字组及词组具有一致的意义。与所属技术领域中具有通常知识者了解的通常或惯用意义不同的词汇或词组(即定义)的特殊定义,用意不在于通过本文词汇或词组的一致性用法提供暗示。就一词汇或词组用意在于具有特殊意义的方面来说,即有别于所属技术领域中具有通常知识者了解的意义,此一特殊定义应会按照为此词汇或词组直接且不含糊地提供此特殊定义的定义方式,在本说明书中明确提出。
本申请的原理格外基于与半导体装置的裂纹相关失效相关联的某些观察,其中,尤其是在紧密相隔的接触垫配置中,可能遭遇机械稳建性显著降低,这可能导致裂纹形成、及任何此类裂纹传播进入更深层敏感介电材料,从而当整体制造程序期间诱发裂纹形成时,例如在接触垫与适当的接合线、焊块及类似者接触时,便导致装置过早疲劳、或导致良率明显损失。请参阅图1A及图1B,将说明的是半导体装置及其最后敷金属层与钝化层的基本组态。
图1A示意性绘示半导体装置100或其几何组态的俯视图,亦称为电路设计或单纯地称为设计,以便提供所欲的接触垫的结构,可将其当作接触垫用于打线及类似者。如图所示,根据总体设计准则,在俯视图中具有实质四边形形状的第一接触垫110A可设有特定装置及设计相依性横向间隔110S。再者,第二接触垫110B可设有与第一连接垫110A实质相同的大小及形状,并且亦可使用实质相同的间隔110S,以便根据设计要求获得所欲的接触垫110A、110B的阵列。应领会的是,多个此类接触垫110A、110B一般可能必须设于相应敷金属系统(图未示)的顶部,以便对封装件、载体基材及类似者提供所需连接性。接触垫110A可代表连接至相同电位的接触垫,并且因此可连接至最后敷金属层的相同金属区(图未示)。另一方面,接触垫110B可代表要连接至不同电位的接触垫,从而需要连接至最后敷金属层中的不同金属区(图未示)。再者,可用虚线展示相应“贯孔”结构,其可代表相应金属接触,以便连接至最后敷金属层的下伏金属区。举例而言,相应贯孔111A可用于第一接触垫110A,而相应贯孔111B则可提供第二接触垫110B至下伏敷金属系统的连接。
大体上,接触垫110A、110B及相应贯孔111A、111B可由相同材料(例如铝)所构成,其为用于提供贯孔接合垫、RF应用附加金属线及类似者的常用且建置良好的材料。此外,横向尺寸属于设计规则问题,然而,却可包括比上覆敷金属层中的相应最小尺寸远远更小的最小尺寸。如图所示,在一项具体实施例中,接触垫110A、110B及贯孔111A、111B在俯视图中的外形可代表具有实质线性边缘区112的正方形。
再者,接触垫110A、110B可横向嵌埋于适当的钝化材料中,诸如聚酰胺及类似者,为了简化起见并未予以展示。再者,钝化材料可与接触垫110A、110B的一部分重叠,以便例如为了贯孔接合及类似者而使适当的接触表面区曝露。另一方面,贯孔111A、111B可横向嵌埋于任何适当的层间介电材料中,诸如富含氢的二氧化硅、二氧化硅及类似者。
本案发明人已认识到,裂纹101常可在钝化材料及/或下伏层间介电材料中形成,较佳为在连接至不同金属区的第一接触垫110A与第二接触垫110B之间的间隔110S中形成,而另一方面,相应裂纹在介于诸第一接触垫110A之间的间隔110S中可能很罕见。此类裂纹形成可在附加机械应力下出现,举例来说,可在进行可施加机械力及施热的贯孔结合程序时出现,而在其它情况下,温度循环可单纯地导致额外显著的应力分量,这举例来说,乃导因于接触垫110A、110B的材料与周围介电材料的热膨胀系数的差异。
图1B示意性绘示半导体装置100的截面图。如图所示,可提供敷金属系统150,为了方便起见,以极最后敷金属层140为基础绘示,其包括适当的介电材料141、以及嵌埋于介电材料141中的第一金属区140A与第二金属区140B。应领会的是,取决于半导体装置100的总体复杂度,敷金属系统150可具有两个、三个、四个、五个或更多个敷金属层,以便为半导体装置100中形成的任何电路组件实施所需连接性,如前所述。如图所示,当接触垫110A必须连接至相同电位时,可通过贯孔111A将接触垫110A连接至第一金属区140A。另一方面,可通过贯孔111B将接触垫110B连接至金属区140B,以便将接触垫110B与特定电位连接。因此,第一金属区140A与第二金属区140B之间没有机械连接,介电材料141除外。
此外,如上述,接触垫110A、110B可搭配贯孔111A、111B形成钝化层或钝化阶120,其可代表半导体装置100的极最后装置阶,并且还可提供半导体装置100的所需钝化,用于使接触垫110A、110B的中央区曝露的相应开口除外。举例而言,可在第一接触垫110A与第二接触垫110B的边缘区处取看图1B的截面,以使得钝化材料121可予以绘示为接触垫110A、110B的相应部分上面形成的连续层,并且还可以可靠地包覆间隔110S。如上述,介电材料122可横向围绕贯孔111A、111B,其可代表接触垫110A、110B的下部分,并且可基于诸如镀覆等等任何适当的沉积技术由相同材料所构成。一般而言,介电材料122亦称为层间介电材料,可有别于钝化材料121的材料组成。类似的是,最后敷金属层140的介电材料或层间介电材料141亦可与钝化材料121有不同的组成。
从图1A及图1B明显看出,由于机械应力及类似者、以及由于设计方面金属区140A可具有与组合的第一连接垫110A实质相同的横向尺寸、及接触垫110B可具有与下伏金属区140B基本上相同的尺寸而产生裂纹101时,可促进裂纹101传播进入下伏介电材料,原因举例来说,在于此材料中的一般拉伸应力,以及尤其在于间隔110S内介电材料122、141所形成的路径的机械稳建性降低。另一方面,由于第一接触垫110A与下伏金属区140A的显著重叠,介于诸第一接触垫之间的敏感介电材料122、141中可能实质观察不到相应裂纹形成。
所以,本案发明人已认识到,通过重新设计接垫配置及/或极最后敷金属层中金属区的配置,在不影响功能行为且不使这些组件的位置及总体大小显著改变的情况下,可使敏感材料122、141的机械稳建性显著提升。为此,可修改半导体装置100的设计以便提供裂纹抑制设计,这可通过提供指叉式及/或重叠组态来达成,下文有更详细的说明。
图2A示意性绘示半导体装置200的俯视图,其可具有与图1A及图1B的装置100类似的组态,原因在于为了方便起见,可假设半导体装置200可具有与半导体装置100相同的基本组态及功能,却在如上述的钝化阶及敷金属系统中提供裂纹抑制组态。
如图所示,半导体装置200可包含钝化阶或钝化层220,其一部分可代表钝化材料(图未示)及相应接触垫,诸如第一接触垫210A及第二接触垫210B。基本上,接触垫210A、210B可实质占据与半导体装置100的上下文中所示及所述组态相同的区域,其中亦可提供相同的连接性及功能性。与可提供实质似正方形接触垫的前述组态相比之下,可修改设计,并从而修改横向形状,即如图2A所示俯视图中的形状,以便提供增强的机械稳建性。为此,可修改至少一个第一连接垫210A的形状,即相邻于第二接触垫210B的接触垫210A的形状,以便代表非四边形横向形状,为的是要在一项说明性具体实施例中,通过在相邻于接触垫210B的接触垫210A与置于接触垫210B下面的金属区240B之间提供某一重叠来提升机械稳建性。
举例而言,可在例如相应接触垫210A的相应拐角部分处提供一或多个凸出物214A(例如,形状基本上为实质三角形的凸出物),以便“桥接”对应基本间隔210S的一部分。同时,金属区240B可具有相反安置的凸出物244B(例如,形状基本上为实质三角形的凸出物),以使得可在代表最后敷金属层中的对应金属区用于连接至接触垫210B的区域240B、与最后敷金属层中所设再一金属区(图未示)的接触垫210A之间获得图2A的俯视图中这些“垂直”堆栈组件的重叠,以便获得与图1A及图1B中半导体装置100的上下文中所述相同的连接性及功能行为。
再者,如图所示,凸出物214A可相对接触垫210B的转角部分215在大小及形状方面互补,以便在第一接触垫210A与第二接触垫210B之间提供所欲横向距离。“互补”一词应理解为意指在俯视图中,相应组件的对置边缘部分,诸如凸出物214A及相反安置的转角215,具有可保留实质恒定横向间隔的几何组态。所以,转角215处“圆角化”的程度可通过将具有线件与三角形凸出物214A的相应线件平行的相应三角形部分切掉来获得。所以,第一接触垫210A与第二接触垫210B的非四边形横向形状可通过这些接触垫的对置边缘的互补几何组态来达成,其中至少一个边缘包含相应凸出物,诸如三角形凸出物214A。
应领会的是,当必须在接触垫210B的右手边提供附加接触垫时,第二接触垫210B亦可在对立侧具有相应凸出物(图未示)。所以,通过适当地设计旨在连接至不同电位的相邻接触垫的边缘、及通过适当地设计最后敷金属层中的下伏金属区,可获得垂直堆栈部分的重叠,从而提供优越的裂纹抑制特性。在此背景下,应领会的是,“重叠”一词应理解为说明第一组件的一部分、及第二组件于第一组件上面或下面的一部分在不同高度位准的同一横向位置。就这一点来说,相邻于接触垫210B横向而置的接触垫210A与金属区240B重叠,因为接触垫210A的凸出物214A的至少一部分具有与下伏金属区240B的凸出物244B相同的横向位置。
图2B示意性绘示图2A的装置200的截面图。如图所示,可根据整体装置要求提供包括一或多个敷金属层的敷金属系统250,为了方便起见,仅绘示其最后敷金属层240,亦如上述。最后敷金属层240可包含介电材料241,可在其中嵌埋金属区240A及金属区240B,亦如以上在半导体装置100的上下文中所述。如参照图2A所阐释,金属区240A及240B可代表不同电位,这按照传统导致金属区240A、240B的对应间隔,并且导致相应接触垫的稳定性降低,如以上在图1A及图1B的上下文中所述。由于半导体装置200的设计经过修改,金属区240B可包含凸出物244B,以便由于凸出物214A的提供而提供与相邻接触垫210A的重叠。所以,可沿着深度方向限制钝化材料221中形成的裂纹201的相应裂纹传播,以免因金属区240B的凸出物244B而进一步传播进入敷金属系统250的深度。
请再次参照图2A,经证实,可对于举例如由钝化阶中的凸出物214A及最后敷金属层240中的凸出物244B所提供的裂纹传播达成横向限制、以及亦对于因重叠凸出物214A、244B而沿着深度方向的裂纹传播达成限制,从而显著降低沿着敷金属系统250中任何方向的裂纹传播的可能性。
所以,敷金属系统250及钝化层220的增强机械效能可通过使用适当调适的装置设计来达成,不需要显著变更整个装置组态,也不需要重新设计相应制造程序,但提供适当设计的光刻掩膜除外,以便将金属区及/或接触垫的非四边形横向形状的修改设计转移到实际半导体装置。就这一点来说,应注意的是,金属区240A、240B及/或接触垫210A、210B相比于传统设计(图1A及图1B)更复杂的边缘几何形态可基于建置良好的光刻技术来轻易达成,因为如上述,一般而言,钝化阶220及最后敷金属层240中的任何最小尺寸相比于下横置敷金属层中的关键尺寸可显著更大,以使得边缘区的更复杂设计可全然在建置良好的光刻技术的能力范围内。
当从另一个观点看时,如设计或半导体装置200在图2A及图2B所示的具体实施例可代表横向指叉式组态,其中这项具体实施例中的指叉式本质是在至少两个层阶中完成,亦即,在接触垫210A、210B的最上层阶中、及由区域240A、240B所界定的下横置层阶中完成。接触垫210A、210B的指叉式组态乃通过相应横向对立设置边缘的互补横向形状或设计所获得,其乃为了接触垫210A而通过说明性三角形凸出物214A形成,并且为了接触垫210B而通过对应转角部分215形成,对接触垫210B的此部分付与多边形几何形态。金属区240A、240B的层阶处获得类似的互补或指叉式组态。
图2C示意性绘示敷金属层240的俯视图,包括金属区240A、240B。在这种情况下,金属区240A、240B的横向对立设置边缘具有由实质三角形凸出物244B、及金属区240A的边缘处提供的互补“圆化”转角245所界定的指叉式横向组态。另外,这些互补或指叉式横向组态可重叠,本身对介于金属区240A、240B之间的任何层间介电材料付与横向裂纹抑制行为,如参照图2A及图2B所述,其可通过金属区240B的凸出物244B与接触垫210A的凸出物214A的重叠来达成,如图2A及图2B所示。
再者,如前述,亦可为任何进一步邻接金属区,诸如相邻于金属区240B而置的区域240C,建立类似的指叉式或互补横向组态。所以,金属区240C的相应凸出物244C可采互补方式对应于金属区240B的“圆化”转角,即多边形转角245。
应领会的是,接触垫的层阶中亦可继续类似组态,以便提供具有横向指叉式几何形态并与金属区(诸如区域240A、240B、240C)的下伏链重叠的多个链接的接触垫。
要注意的是,亦可适当地调适相应贯孔211A、211B的横向形状,以便符合接触垫210A、210B的横向形状,举例来说,通过使贯孔211A、211B设有透过“圆化”转角部分所获得的多边形形状。
图3A在俯视图中示意性绘示半导体装置300或其设计的进一步说明性具体实施例,其具有相邻接触垫310A、310B及下伏金属区340A、340B。从图3A明显看出,至少在接触垫310A、310B的层阶处获得指叉式横向组态,其中接触垫310A、310B的相应横向对置边缘可分别由对应的凸出物314A、314B所形成,由此在接触垫310A、310B中形成互补组态的锯齿边缘几何形态。类似的是,下伏金属区340A、340B可具有横向对立设置边缘,该等边缘具有通过对应凸出物所获得的指叉式组态,在这种情况下,该等凸出物分别为实质三角形几何形态的凸出物344A、344B,从而亦在金属区340A、340B之间形成实质锯齿形边界或间隔。再者,亦如以上参照图2A至图2C所述,可在接触垫310A、310B与下伏金属区340A、340B之间达成重叠,因为金属区340A的凸出物344A可与接触垫310B的凸出物314B重叠,并且金属区340B的凸出物344B可与接触垫310A的凸出物314A重叠。所以,指叉式组态乃顺着横向方向获得,亦即顺着图3A中的水平及垂直方向获得,而重叠组态则是顺着高度方向获得,亦即顺着与图3A的绘制平面垂直的方向获得。按照这种方式,可更进一步增强裂纹抑制效能,因为可采高效率方式顺着横向及高度方向抑制裂纹传播。应领会的是,在一些说明性具体实施例中,分别在接触垫310A与金属区340A之间、及接触垫310B与金属区340B之间提供电气及机械接触的相应贯孔311A、311B亦可具有与对应接触垫310A、310B的横向形状实质类似的横向形状,从而亦在横向对立设置边缘处形成互补组态,并且避免贯孔311A、311B的表面区明显缩减,同时仍然提供所欲截面形状,即锥形形状,下文将参照图3B论述。
图3B示意性绘示沿着图3A的线条IIIB-IIIB取看的截面图。如图所示,半导体装置300包括设于钝化阶320中的接触垫310A、310B,亦包含钝化材料321。再者,金属区340A、340B可代表敷金属系统350的极最后敷金属层340,其中可将金属区340A、340B嵌埋于对应层间介电材料341中。再者,接触垫310A可通过贯孔311A连接至金属区340A,贯孔311A可代表接触垫310A的下部分,并且可具有锥形形状,以便相对周围介电材料341提供优越的黏附力及机械稳定性。类似的是,可基于具有锥形截面形状的贯孔311B将接触垫310B连接至金属区340B。再者,接触垫310A、310B与下伏金属区340A、340B的重叠可通过相应凸出物来达成,其中,根据图3A中所示的区段,金属区340B的凸出物344B可与接触垫310A的凸出物314A重叠。
所以,请再次参照图3A,当顺着图3A的向下方向移动截面线IIIB-IIIB时,将获得接触垫310B与金属区340A的相应重叠部分,以此类推。显然,至少在相应接触垫与金属区的重叠区内,用于裂纹传播的“垂直”路径乃实质受到重叠组态阻碍。
图3C根据进一步说明性具体实施例,示意性绘示半导体装置300的俯视图,其中设于最后敷金属层340中的金属区340A、340B可具有基于实质四边形凸出物344A、344B形成的横向指叉式组态。亦即,金属区340A、340B的相应横向对立设置边缘312具有位在金属区340A上的凸出物344A、及位在金属区340B上的互补设置凸出物344B,从而获得横向指叉式组态,在层件340内,即顺着图3C的垂直方向,提供高裂纹抑制行为。在一些说明性具体实施例中,相对对应层间介电材料中的裂纹形成,极最后敷金属层340的这种裂纹抑制特性可足以获得所欲的更高稳建性。
在进一步说明性具体实施例中,亦可至少在接触垫的层阶处建立对应指叉式组态,下文将参照图3D作说明。
图3D示意性绘示半导体装置300或其设计的俯视图,其中接触垫310A、310B可大致置于对应金属区340A、340B上面,并可通过贯孔或下部分与其连接,如以上参照图2A至图2C及图3A至图3B所述。为简单起见,图3D中未展示任何此类贯孔。然而,如上述,任何此类贯孔皆可具有可与接触垫310A、310B的横向形状对应的横向形状,但尺寸稍微缩减。
如图所示,接触垫310A可具有相应凸出物314A,其可具有实质四边形横向形状,以便与接触垫310B的相应凸出物314B形成指叉式组态。再者,接触垫310A、310B的指叉式组态可视为相对由金属区340A、340B所形成的指叉式组态呈现“反转”或“互补”,原因在于可获得某一重叠,举例来说,通过接触垫310A的凸出物314A与金属区340B的凸出物344B获得、以及通过接触垫310B的凸出物314B与金属区340A的凸出物344A获得。所以,亦如上述,可达成高效率组态,其中可抑制顺着横向方向(即图3D的水平及垂直方向)、及顺着高度方向(即与图3D的绘制平面垂直的方向)的裂纹传播。
图3E根据金属区340A、340B可界定指叉式横向组态的进一步说明性具体实施例,示意性绘示半导体装置300或其设计的俯视图,举例如以上参照图3C所述。此外,接触垫310A、310B可在相应对立设置边缘312处设有简化几何组态,其在所示具体实施例中,可代表实质线性边缘区。然而,接触垫310A、310B的线性边缘区312乃横向而置,以便分别提供与对应相邻金属区340B,340A的重叠。亦即,接触垫310A的对应线性边缘区312乃安置成使得与金属区340B的对应凸出物344B获得某一重叠。类似的是,接触垫310B的边缘区312乃安置成使得与金属区340A的对应凸出物344A建立重叠。所以,基于指叉式组态,亦在金属区340A、340B的层阶中获得非常有效率的裂纹传播抑制行为,同时由于重叠组态而显著抑制沿着高度方向(即沿着与图3E的绘制平面垂直的方向)的裂纹传播,而另一方面,可实施边缘区312的实质线性组态。
图3F根据进一步说明性具体实施例,示意性绘示半导体装置300或其设计的俯视图。如图所示,金属区340A、340B可分别通过相应实质四边形凸出物344A、344B来提供横向指叉式组态,亦如以上参照图3C所阐释。再者,接触垫310A、310B可通过实质四边形横向形状的相应凸出物314A、314B来形成指叉式组态。如图所示,在这种情况下,可在金属区340A的对应凸出物344A上面形成接触垫310A的凸出物314A,以使得凸出物314A,344A在相应边缘区处界定非四边形形状,其中对应的凸出物系彼此上下置中。类似的是,接触垫310B的凸出物314B在金属区340B的相应凸出物344B上面置中。另一方面,边缘区312乃安置成使得获得某一重叠,举例来说,通过在接触垫310B的两个横向相邻凸出物314B之间具有非凸出部分的凸出物344A所获得。对于金属区340B的凸出物344B、及介于接触垫310A的相应凸出物314A之间的非凸出区域也是如此。
所以,通过大体上提供金属区及/或接触垫的非四边形横向形状,可提供多种几何组态,其中相邻金属区及/或相邻接触垫的横向对立设置边缘可在相邻金属区及/或接触垫之间提供非线性横向空间,由此显著增加为了顺着横向方向产生裂纹所需的能量,而且尤其是造成该裂纹的传播。举例来说,在说明性具体实施例中,相邻金属区及/或相邻接触垫的横向指叉式或互补组态可提供明显抵抗力来对抗裂纹产生及裂纹传播。再者,接触垫与金属区的重叠一经提供,便亦可获得机械性、高度稳健的整体组态,从而至少显著增加为了沿着组态的高度方向产生裂纹所需的能量,并且还增加顺着高度方向的裂纹传播抑制行为。在有帮助的具体实施例中,高度横向有效概念即相邻金属区及/或接触垫中非四边形本质的横向指叉式或互补组态,可与接触垫及金属区的重叠组态搭配,由此提供对应半导体装置更加优越的裂纹抑制效能。由于设计修改相比于纯四边形金属区及接触垫可全然在建置良好的光刻技术的能力范围内,因此可在不对任何程序及材料进行显著修改的情况下达成与抗裂相关的优越效能,但用于在实际半导体装置中实施适当设计的相应光刻掩膜的调适除外。
图4示意性绘示在抑制裂纹形成及裂纹传播方面具有优越效能的半导体装置400的截面图。如图所示,半导体装置400可包含基材401,诸如包含硅、硅/锗或任何其它适当半导体材料的半导体基材,可能与埋置型介电材料搭配,端视半导体装置400的整体组态而定。可在基材401中或上形成具有适当材料组成及特性的半导体层402,以便在其中及其上形成相应电路组件404,诸如场效晶体管、电阻器及类似者。电路组件404可具有任何适当的关键尺寸,其中,在尖端半导体装置中,可能必须实施30nm且甚至更小的垂直尺寸才能符合对应的设计规则。电路组件404的至少一部分可嵌埋于接触阶403中,接触阶403可包含任何适当的介电材料,并且可包括接触组件405,接触组件405包含适当的含金属材料,以便连接至电路组件404的相应接触区。
可在接触阶403上面形成敷金属系统450,以便连接至相应接触组件405,并且提供半导体装置400正常作用所需的电气、热及机械连接。如前述,诸如系统450的相应敷金属系统可具有多个敷金属层,其数量及复杂度可显著取决于半导体装置400的整体组态。举一实施例来说,可提供第一敷金属层460以便连接至接触阶403,并且可已在其中形成相应金属区,诸如横向嵌埋于适当介电材料461中的金属线460A。此外,敷金属系统450可分别包含具有相应介电材料471、481及金属区470A、480A的附加敷金属层470、480。无论敷金属层460、470、480的实际数量有多少,都可存在极最后敷金属层440,以便作用为钝化层420的“接口(interface)”,其进而可就环境影响及类似者提供半导体装置400的钝化,并且还可对环境提供连接性,举例来说,用于连接至封装件、再一半导体装置及类似者。因此,最后敷金属层440可包含高导电金属区440A、440B、440C,其可适当地连接至下一个下敷金属层480,并且可提供导电性及导热性。为此,可提供任何适当的层间介电材料441,其特性可取决于半导体装置400关于介电常数及类似者的总体要求。特别的是,金属区440A、440B、440C可代表用于连接至相应接触垫410A、410B、410C的接触区,接触垫410A、410B、410C进而可提供由钝化材料421所曝露的相应接触表面417。举例而言,在一些说明性具体实施例中,接触表面区417可代表用于容置接合线的区域,以便建立连至再一装置(例如封装件及类似者)的打线连接。在其它具体实施例中,接触垫410A、410B、410C可代表用于其它接触技术的组件,诸如焊接技术,如覆晶方法中使用的技术。
如前述,最后敷金属层440的金属区440A、440B、440C一般至少是以最小尺寸为基础的所形成,其相比于下横置敷金属层(诸如层件460、470及类似者)所需的尺寸,可能关键性较不显著。所以,由于横向尺寸实质增大,金属区440A、440B、440C的非四边形横向形状可至少在邻接边缘区处,通过形成相应互补几何组态,基于建置良好的光刻技术来达成,如前文参照图2A至图2C及图3A至图3F所述。因此,虽然相比于传统四边形设计,金属区440A、440B、440C的任何此类非四边形横向形状可能需要实施稍微缩减的最小横向尺寸,但任何此类缩减的横向尺寸仍在建置良好的的光刻技术的能力范围内。
类似的是,可基于如上述的横向形状或设计来形成接触垫410A、410B、410C,其可通过相应贯孔或下部分411A、411B、411C连接至相应下横置金属区440A、440B、440C。所以,相邻的金属区440A、440B、440C可形成横向指叉式或互补组态,如上述。类似的是,在一些说明性具体实施例中,相邻的接触垫410A、410B、410C可通过提供非四边形组态来形成横向指叉式组态。在进一步具体实施例中,除了或替代地,接触垫410A、410B、410C可基于非四边形或四边形横向形状与下伏且横向相邻的金属区形成重叠。举例而言,如图4所示,接触垫410A可与金属区440B重叠,并且接触垫410B可与金属区440C重叠,以此类推,端视相邻金属区及接触垫的数量而定。因此,可在最后敷金属层440及钝化阶420中实施任何上述横向及垂直组态。
再者,在图2A至图2C及图3A至图3F所示的具体实施例中,仅在一个维度中绘示金属区及接触垫的横向邻域,其举例来说,可适用于提供打线接触垫,而在其它说明性具体实施例(图未示)中,亦可顺着第二横向方向建立相应邻域,由此沿着两种不同横向方向提供相应的互补或指叉式组态及/或重叠组态,其举例来说,可能需用于更复杂的接触体制,诸如覆晶接合及类似者。
可基于以下程序形成如图4所示的半导体装置400。
在提供基材401之后,可根据装置要求形成或修改半导体材料402。电路组件404可基于建置良好的程序技术形成,包括尖端光刻程序,用于形成例如场效晶体管的闸极电极结构及类似者。再者,可应用磊晶生长技术、离子布植、尖端蚀刻技术及类似者,以便最终获得电路组件404。之后,接触阶403可通过沉积任何适当的介电材料、使其平坦化并形成开口、然后沉积一或多种适当的导电材料来形成,以便获得接触组件405。其次,可逐层形成敷金属系统450,举例来说,通过沉积任何适当的介电材料来形成,诸如二氧化硅、富含氢的二氧化硅或任何其它低k介电材料,端视需求而定,然后可将其图案化,以便形成沟槽及贯孔开口,随后可用适当的材料予以填充,诸如铜、铜合金及类似者。在用于形成敷金属系统450的制造程序期间,最后敷金属层440亦可通过提供介电材料441并基于光刻掩膜对其进行图案化来形成,该光刻掩膜包括适当设计的横向结构,举例如以上参照图2A至图2C及图3A至图3F所述者。所以,在相应光刻程序及随后的图案化序列期间,可为金属区440A、440B、440C达成适当的非四边形横向形状。之后,可沉积并图案化进一步介电材料(亦以参考附图标记441表示),以便基于用于将介电材料441图案化的适当光刻技术来形成贯孔411A、411B、411C,可能连同接触垫410A、410B、410C一起形成,其中,在这种情况下,如对照区域440A、440B、440C所述的相同准则亦适用。亦即,取决于是否要建立横向指叉式组态及/或是否要与相应下伏金属区440A、440B、440C在某些区域实施适当的重叠,可在相应光刻程序期间将相应设计转移到材料441内,并且可能转移到再一掩膜层(图未示)内。之后,可例如通过镀覆技术,然后沉积钝化材料421及其相应图案来沉积任何适当的材料,诸如铝,以便使接触表面417曝露。
结果是,本申请提供半导体装置及相应制造技术,其中可为了极最后敷金属层的金属区、及/或为了连接至最后敷金属层中金属区的接触垫而实施特定非四边形横向形状,即设计,以便降低裂纹顺着半导体装置的横向及/或高度方向传播的可能性。据信,修改的横向及垂直组态(即指叉式组态及重叠),可增加可能为了产生裂纹、或为了造成裂纹横向及垂直传播而需要的临界能量位准。
以上所揭示的特殊具体实施例仅属说明性,正如本发明可用所属技术领域中具有通常知识者所明显知道的不同但同等方式予以修改并且实践而具有本文的指导效益。举例而言,以上所提出的程序步骤可按照不同顺序来进行。再者,除了如所附权利要求书中所述除外,未意图限制于本文所示构造或设计的细节。因此,证实可改变或修改以上揭示的特定具体实施例,而且所有此类变例全都视为在本发明的范畴及精神内。要注意的是,本说明书及所附权利要求书中如“第一”、“第二”、“第三”或“第四”的类用以说明各个程序或结构的术语,仅当作这些步骤/结构节略参考,并且不必然暗喻这些步骤/结构的进行/形成序列。当然,取决于精准表达的措辞,可或可不需要这些程序的排列顺序。因此,本文寻求的保护如所附权利要求书中所提。

Claims (19)

1.一种半导体装置,其包含:
包括最后敷金属层的敷金属系统,该最后敷金属层包含第一金属区、及与该第一金属区横向分开并相邻于该第一金属区的第二金属区;
在该最后敷金属层上面形成的钝化层;
在该钝化层中形成以与该第一金属区接触的第一接触垫,其中,该第一接触垫在垂直于该第一接触垫的上平面的高度方向与该第二金属区的一部分重叠,以及
在该钝化层中形成相邻于该第一接触垫以与该第二金属区接触的第二接触垫,并且,该第二接触垫在垂直于该第二接触垫的上平面的高度方向与该第一金属区的一部分重叠。
2.根据权利要求1所述的半导体装置,其中,该第一金属区与第二金属区其中至少一者具有非四边形横向形状。
3.根据权利要求2所述的半导体装置,其中,该第一金属区与第二金属区其中至少该者的该非四边形横向形状由该第一金属区及该第二金属区其中至少该者的边缘所界定,该边缘面向该第一金属区与该第二金属区其中至少另一该者的边缘。
4.根据权利要求2所述的半导体装置,其中,该第一金属区与第二金属区各具有非四边形横向形状。
5.根据权利要求4所述的半导体装置,其中,该第一金属区与第二金属区的对向边缘具有互补横向形状,以便形成指叉式横向组态。
6.根据权利要求1所述的半导体装置,其中,该第一接触垫与第二接触垫其中至少一者具有非四边形横向形状。
7.根据权利要求6所述的半导体装置,其中,该第一接触垫与第二接触垫其中至少该者的该非四边形横向形状由该第一接触垫及该第二接触垫其中至少该者的边缘所界定,该边缘面向该第一接触垫与该第二接触垫其中至少另一该者的边缘。
8.根据权利要求6所述的半导体装置,其中,该第一接触垫与第二接触垫各具有非四边形横向形状。
9.根据权利要求8所述的半导体装置,其中,该第一接触垫与第二接触垫的对向边缘具有互补横向形状,以便形成指叉式横向组态。
10.根据权利要求1所述的半导体装置,其中,该第一金属区与第二金属区其中至少一者具有非四边形横向形状,并且该第一接触垫与第二接触垫其中至少一者具有非四边形横向形状。
11.根据权利要求2所述的半导体装置,其中,该第一金属区与第二金属区其中至少该者的该非四边形横向形状由在该第一金属区与第二金属区其中至少该者的边缘区处形成的二或更多个四边形凸出物所形成。
12.根据权利要求2所述的半导体装置,其中,该第一金属区与第二金属区其中至少该者的该非四边形横向形状由在该第一金属区与第二金属区其中至少该者的边缘区处形成的二或更多个三角形凸出物所形成。
13.根据权利要求6所述的半导体装置,其中,该第一接触垫与第二接触垫其中至少该者的该非四边形横向形状由在该第一接触垫与第二接触垫其中至少该者的边缘区处形成的二或更多个四边形凸出物所形成。
14.根据权利要求6所述的半导体装置,其中,该第一接触垫与第二接触垫其中至少该者的该非四边形横向形状由在该第一接触垫与第二接触垫其中至少该者的边缘区处形成的二或更多个三角形凸出物所形成。
15.根据权利要求1所述的半导体装置,其中,该第一金属区与第二金属区包含铜,并且该第一接触垫及第二接触垫包含铝。
16.一种半导体装置,其包含:
包括最后敷金属层的敷金属系统,该最后敷金属层包含第一金属区、及与该第一金属区横向分开并相邻于该第一金属区的第二金属区;
在该最后敷金属层上面形成的钝化层;
在该钝化层中形成以与该第一金属区接触的第一接触垫,其中,该第一接触垫在垂直于该第一接触垫的上平面的高度方向与该第二金属区的一部分重叠,以及
在该钝化层中形成相邻于该第一接触垫以与该第二金属区接触的第二接触垫,并且,该第二接触垫在垂直于该第二接触垫的上平面的高度方向与该第一金属区的一部分重叠,该第一金属区及该第一接触垫其中至少一者具有非四边形横向形状。
17.根据权利要求16所述的半导体装置,其中,该非四边形横向形状由包括四边形凸出物及三角形凸出物其中至少一者的至少一个边缘区所形成。
18.一种制造半导体装置的方法,其包含:
在该半导体装置的敷金属系统的最后敷金属层的介电材料中形成第一金属区及第二金属区,该第一金属区与第二金属区适于连接至不同电位;以及
在钝化层中形成第一接触垫与第二接触垫,其中,该第一接触垫与第二接触垫导电耦接至该第一金属区与第二金属区,并且其中,该第一接触垫在垂直于该第一接触垫的上平面的高度方向与该第二金属区重叠,该第二接触垫在垂直于该第二接触垫的上平面的高度方向与该第一金属区重叠。
19.根据权利要求18所述的方法,更包含界定该第一接触垫与该第二接触垫、该第一金属区及该第二金属区其中至少一者的非四边形横向形状。
CN201811179911.XA 2017-10-11 2018-10-10 在敷金属系统中具有优越抗裂性的半导体装置 Active CN109659293B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/729,774 US10340229B2 (en) 2017-10-11 2017-10-11 Semiconductor device with superior crack resistivity in the metallization system
US15/729,774 2017-10-11

Publications (2)

Publication Number Publication Date
CN109659293A CN109659293A (zh) 2019-04-19
CN109659293B true CN109659293B (zh) 2023-02-03

Family

ID=65992621

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811179911.XA Active CN109659293B (zh) 2017-10-11 2018-10-10 在敷金属系统中具有优越抗裂性的半导体装置

Country Status (3)

Country Link
US (1) US10340229B2 (zh)
CN (1) CN109659293B (zh)
TW (1) TWI694573B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714195B (zh) * 2019-08-02 2020-12-21 信通交通器材股份有限公司 具有抗熱應力的系統級半導體雙面封裝電路板及製造方法
US11069562B1 (en) 2020-01-15 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation layer for integrated circuit structure and forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120282753A1 (en) * 2008-03-31 2012-11-08 Kim Sun-Oo Semiconductor Devices and Methods of Manufacture Thereof
CN103367295A (zh) * 2012-03-27 2013-10-23 瑞萨电子株式会社 半导体器件及其制造方法
CN106486478A (zh) * 2015-08-27 2017-03-08 格罗方德半导体公司 具有金属裂纹停止的集成电路结构及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200941544A (en) * 2005-05-25 2009-10-01 Megica Corp Chip structure and process for forming the same
US8860224B2 (en) 2011-02-25 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Preventing the cracking of passivation layers on ultra-thick metals
US20130320522A1 (en) 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
US20150061156A1 (en) 2013-09-03 2015-03-05 Globalfoundries Singapore Pte. Ltd. Pad solutions for reliable bonds

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120282753A1 (en) * 2008-03-31 2012-11-08 Kim Sun-Oo Semiconductor Devices and Methods of Manufacture Thereof
CN103367295A (zh) * 2012-03-27 2013-10-23 瑞萨电子株式会社 半导体器件及其制造方法
CN106486478A (zh) * 2015-08-27 2017-03-08 格罗方德半导体公司 具有金属裂纹停止的集成电路结构及其形成方法

Also Published As

Publication number Publication date
US20190109097A1 (en) 2019-04-11
CN109659293A (zh) 2019-04-19
US10340229B2 (en) 2019-07-02
TW201931553A (zh) 2019-08-01
TWI694573B (zh) 2020-05-21

Similar Documents

Publication Publication Date Title
JP4878030B2 (ja) エッチング処理されたリードフレームを用いる再分散型ハンダパッド
JP5308145B2 (ja) 半導体装置
CN100593232C (zh) 制造倒装芯片器件的结构和方法
CN116705737A (zh) 半导体封装
CN106548996B (zh) 具有锯齿形边缘的伪金属
CN102969305B (zh) 用于半导体结构的管芯对管芯间隙控制及其方法
JP2008091852A (ja) 積層パッケージおよびその製造方法
TWI551199B (zh) 具電性連接結構之基板及其製法
WO2011013091A2 (en) Semiconductor device including a stress buffer material formed above a low-k metallization system
US9806056B2 (en) Method of packaging integrated circuits
CN105470235A (zh) 中介板及其制法
CN109659293B (zh) 在敷金属系统中具有优越抗裂性的半导体装置
US8338288B2 (en) Method of manufacturing semiconductor device
CN109216209B (zh) 集成电路封装件及其形成方法
TWI443774B (zh) 金屬重分佈層之製造方法
JP2013247139A (ja) 半導体装置及びその製造方法
TW201338109A (zh) 半導體結構與其形成方法
JP6846117B2 (ja) 半導体装置および半導体装置の製造方法
US7420280B1 (en) Reduced stress under bump metallization structure
CN105489581A (zh) 半导体结构及其制作方法
JP4009380B2 (ja) 半導体チップの製造方法
JP4074721B2 (ja) 半導体チップおよび半導体チップの製造方法
US9922957B2 (en) Semiconductor device and method for manufacturing the same
US20080251907A1 (en) Electronic Device With Stress Relief Element
US11798904B2 (en) Semiconductor structure, redistribution layer (RDL) structure, and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20210304

Address after: California, USA

Applicant after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Applicant before: GLOBALFOUNDRIES INC.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant