JP5147234B2 - 半導体集積回路装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 176
- 238000009792 diffusion process Methods 0.000 claims description 50
- 238000012905 input function Methods 0.000 claims description 6
- 230000006870 function Effects 0.000 description 14
- 230000002829 reductive effect Effects 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 230000005611 electricity Effects 0.000 description 8
- 230000003068 static effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- 230000001681 protective effect Effects 0.000 description 1
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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Description
図1は、本発明の第1の実施形態の半導体集積回路装置を示す配置図である。
図5は、本発明の第2の実施形態の半導体集積回路装置を示す配置図である。
次に、本発明の第3の実施形態を説明する。
図16は、本発明の第4の実施形態の半導体集積回路装置を示す配置図である。
1b 電極パッド(特定電極パッド)
2、25 入出力セル
3 スクライブ領域
4 電源配線
5 接地配線
6 接地側保護回路(所定回路)
7 電源側保護回路(所定回路)
21 出力制御回路
22 入力回路
30 P型半導体基板
31、32 N型ディープウェル
35、36、46 ガードリング用拡散層(ウェル電位固定用の拡散領域)
48 トリプルウェル領域
50 空き領域
51、53 電源配線
52、54 接地配線
53 電源配線
54 接地配線
56 信号線
57 半導体基板
58 電荷チャージアップ防止用ダイオード
59 電源間容量
60 メッシュ状電源構造
65 半導体ウェハー
66 半導体チップ
70 I/Oバッファ回路(所定回路)
71a レベルシフト回路(高耐圧用)
71b レベルシフト回路(低耐圧用)
Claims (11)
- データ入力機能のみ、データ出力機能のみ又はデータ入出力機能を持つと共に静電気放電に対して内部回路を保護する保護回路を備えた入出力セルが、半導体チップの周辺に並行に複数個並んで配置された半導体集積回路装置において、
前記複数個の入出力セルは、各々、自己の保護回路と接続され且つ自己の入出力セルの上方に位置する電極パッドを有し、
前記複数個の入出力セルの電極パッドは、その複数個の電極パッド全体として千鳥状に配置され、
前記複数個の入出力セルの電極パッドのうち、前記半導体チップの辺に近い位置の電極パッドは、その半導体チップの辺に近い端部の位置が自己の入出力セルの端部の位置と同位置に設定され、
前記複数個の入出力セルが各々備える保護回路は、
自己の電極パッドと電源配線との間に配置された電源側保護回路と、自己の電極パッドと接地配線との間に配置された接地側保護回路とを備え、
前記電源側保護回路は半導体チップの辺側に位置すると共に、前記接地側保護回路は前記半導体チップの内方側に位置し、
自己の入出力セルの前記接地側保護回路の中心位置とこの接地側保護回路に接続される電極パッドの中心位置との間の距離は、
隣接する2個の入出力セル間で同一距離である
ことを特徴とする半導体集積回路装置。 - 前記請求項1記載の半導体集積回路装置において、
前記電源配線は前記半導体チップの辺側に位置すると共に、前記接地配線は前記半導体チップの内方側に位置する
ことを特徴とする半導体集積回路装置。 - 前記請求項2記載の半導体集積回路装置において、
前記電源配線は前記電源側保護回路の上方に位置すると共に、前記接地配線は前記接地側保護回路の上方に位置する
ことを特徴とする半導体集積回路装置。 - 前記請求項1記載の半導体集積回路装置において、
前記電源側保護回路及び接地側保護回路は、各々、MOS型トランジスタで構成される
ことを特徴とする半導体集積回路装置。 - 前記請求項1記載の半導体集積回路装置において、
前記電源側保護回路及び接地側保護回路は、各々、バイポーラ型トランジスタで構成される
ことを特徴とする半導体集積回路装置。 - 前記請求項1記載の半導体集積回路装置において、
前記電源側保護回路及び接地側保護回路は、各々、ダイオードで構成される
ことを特徴とする半導体集積回路装置。 - 前記請求項1〜6の何れか1項に記載の半導体集積回路装置において、
前記複数個の入出力セルの上方には、半導体チップの辺から内方側に向かう方向に2列の電極パッド列が千鳥状に配置され、
更に、前記半導体チップの内方側に向かって1列以上の電極バッドが配置され、
前記3列以上の電極パッドが全体として千鳥状に配置されている
ことを特徴とする半導体集積回路装置。 - データ入力機能のみ、データ出力機能のみ又はデータ入出力機能を持つと共に静電気放電に対して内部回路を保護する保護回路を備えた入出力セルが、半導体チップの周辺に並行に複数個並んで配置された半導体集積回路装置において、
前記複数個の入出力セルは、各々、自己の保護回路と接続され且つ自己の入出力セルの上方に位置する電極パッドを有し、
前記複数個の入出力セルの電極パッドは、その複数個の電極パッド全体として千鳥状に配置され、
前記複数個の入出力セルの電極パッドのうち、前記半導体チップの辺に近い位置の電極パッドは、その半導体チップの辺に近い端部の位置が自己の入出力セルの端部の位置と同位置に設定され、
前記複数個の入出力セルが各々備える保護回路は、
自己の電極パッドと電源配線との間に配置された電源側保護回路と、自己の電極パッドと接地配線との間に配置された接地側保護回路とを備え、
前記電源側保護回路は半導体チップの辺側に位置すると共に、前記接地側保護回路は前記半導体チップの内方側に位置し、
前記保護回路を備えた入出力セルは、トリプルウェル領域に配置され、
前記半導体チップの辺側のディープウェルの電位固定用ガードリング用拡散層は、前記電源側保護回路のガードリング用拡散層と共用されている
ことを特徴とする半導体集積回路装置。 - 前記請求項8記載の半導体集積回路装置において、
前記接地側保護回路のガードリング用拡散層と、自己の入出力セル内に配置された所定回路のガードリング用拡散層とは、互いに隣接する部分同士が共用されている
ことを特徴とする半導体集積回路装置。 - 前記請求項8記載の半導体集積回路装置において、
自己の入出力セル内に配置され且つ隣り合う2つの所定回路のガードリング用拡散層同士は、互いに隣接する部分同士が共用されている
ことを特徴とする半導体集積回路装置。 - 前記請求項10記載の半導体集積回路装置において、
前記隣り合う2つの所定回路のガードリング用拡散層において、前記互いに隣接する部分同士は削除されている
ことを特徴とする半導体集積回路装置。
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
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JP2006354397A JP5147234B2 (ja) | 2006-12-28 | 2006-12-28 | 半導体集積回路装置 |
CN2007103004663A CN101211911B (zh) | 2006-12-28 | 2007-12-28 | 半导体集成电路装置 |
US11/966,529 US7750373B2 (en) | 2006-12-28 | 2007-12-28 | Semiconductor integrated circuit |
US12/786,090 US8759883B2 (en) | 2006-12-28 | 2010-05-24 | Semiconductor integrated circuit |
US14/276,940 US9029917B2 (en) | 2006-12-28 | 2014-05-13 | Semiconductor integrated circuit device |
US14/684,323 US9379101B2 (en) | 2006-12-28 | 2015-04-10 | Semiconductor integrated circuit device |
US15/147,555 US9576947B2 (en) | 2006-12-28 | 2016-05-05 | Semiconductor integrated circuit device |
US15/402,952 US9812441B2 (en) | 2006-12-28 | 2017-01-10 | Semiconductor integrated circuit device |
US15/722,901 US10366980B2 (en) | 2006-12-28 | 2017-10-02 | Semiconductor integrated circuit device |
US16/441,361 US10692856B2 (en) | 2006-12-28 | 2019-06-14 | Semiconductor integrated circuit device |
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JP2006354397A JP5147234B2 (ja) | 2006-12-28 | 2006-12-28 | 半導体集積回路装置 |
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JP2008166495A JP2008166495A (ja) | 2008-07-17 |
JP2008166495A5 JP2008166495A5 (ja) | 2010-01-28 |
JP5147234B2 true JP5147234B2 (ja) | 2013-02-20 |
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JP5147234B2 (ja) * | 2006-12-28 | 2013-02-20 | パナソニック株式会社 | 半導体集積回路装置 |
JP2009302136A (ja) * | 2008-06-10 | 2009-12-24 | Panasonic Corp | 半導体集積回路 |
JP5467736B2 (ja) * | 2008-06-23 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP5503208B2 (ja) | 2009-07-24 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US20080157124A1 (en) | 2008-07-03 |
US20190296006A1 (en) | 2019-09-26 |
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US7750373B2 (en) | 2010-07-06 |
US10366980B2 (en) | 2019-07-30 |
US9576947B2 (en) | 2017-02-21 |
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CN101211911B (zh) | 2011-02-09 |
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