JP5467736B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
- Publication number
- JP5467736B2 JP5467736B2 JP2008163111A JP2008163111A JP5467736B2 JP 5467736 B2 JP5467736 B2 JP 5467736B2 JP 2008163111 A JP2008163111 A JP 2008163111A JP 2008163111 A JP2008163111 A JP 2008163111A JP 5467736 B2 JP5467736 B2 JP 5467736B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- mesh
- bonding pad
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
パッドピッチ=2×セルピッチ
とし、且つ、接続パッド全体のパッドピッチを、
パッドピッチ/3(=2×セルピッチ/3)
として、2個のIOセル当り3個の接続パッドを配置している。
2…半導体基板
3…I/Oセル
4…内部コア領域
5…信号用ボンディングパッド
6…第1電源用ボンディングパッド
7…第2電源用ボンディングパッド
8…第1電源リング
9…第2電源リング
11…第1拡張電源リング
12…第2拡張電源リング
13…上層配線
14…下層配線
15…第1電源リング接続配線
16…第2電源リング接続配線
17…第1拡張リング接続コンタクト
18…第2拡張リング接続コンタクト
19…信号用接続コンタクト
21…I/O領域
22…基本コア領域
23…拡張コア領域
24…上層配線メッシュ
25…下層配線メッシュ
26…第1パッド列
27…第2パッド列
Claims (5)
- 半導体基板に形成される複数のI/Oセルが配置されるI/O領域と、
前記半導体基板に形成され、前記I/O領域に囲まれるコア領域と、
ICチップの周縁に沿って配置される複数のボンディングパッドと、
前記ボンディングパッドと同じ層に構成され、前記ボンディングパッドに囲まれた領域に配置される上層配線メッシュと、
前記上層配線メッシュと前記半導体基板との間に配置される下層配線メッシュと
を具備し、
前記下層配線メッシュは、
前記上層配線メッシュと前記コア領域との間に構成される第1下層配線メッシュと、
前記ボンディングパッドと前記コア領域との間に構成される第2下層配線メッシュとを備える
半導体集積回路。 - 請求項1に記載の半導体集積回路において、
前記上層配線メッシュは、
上層環状電源配線を含み、
前記第2下層配線メッシュは、
前記ボンディングパッドの下に構成される下層環状電源配線を含み、
前記コア領域は、
前記上層環状電源配線と前記下層環状電源配線との各々を介して供給される電力に基づいて動作する論理セルを含む
半導体集積回路。 - 請求項2に記載の半導体集積回路において、
前記ボンディングパッドは、
電源供給用パッドと、
前記I/Oセルに信号を供給する信号供給用パッドと
を備え、
前記電源供給用パッドは、
ビアコンタクトを介して前記下層環状電源配線に接続されるとともに、配線パターンを介して前記上層環状電源配線にも接続される
半導体集積回路。 - I/Oセルが配置されるI/O領域と、
論理セルが配置されるコア領域と、
前記I/O領域と前記コア領域との間に構成され、他の論理セルが配置される拡張コア領域と
を具備し、
前記I/O領域は、
前記I/Oセルの上に構成され、前記I/Oセルに信号を供給する第1ボンディングパッドを備え、
前記コア領域は、
上層配線メッシュと、
前記上層配線メッシュの下に構成される下層配線メッシュと、
を備え、
前記拡張コア領域は、
前記上層配線メッシュと同じ層に構成される第2ボンディングパッドと、
前記第2ボンディングパッドの下に位置し、前記下層配線メッシュと同じ層で前記下層配線メッシュに接続する拡張下層配線メッシュと、
前記拡張下層配線メッシュの下の拡張論理セル領域に配置される拡張論理セルと
を備える
半導体集積回路。 - 請求項4に記載の半導体集積回路において、
前記ボンディングパッドは、
前記I/Oセルに信号を供給する信号供給用パッドと、
電源供給用パッドと
を備え、
前記電源供給用パッドは、
前記上層配線メッシュに設けられた上層環状電源配線に、配線パターンを介して接続されるとともに、前記ボンディングパッドの下の前記下層配線メッシュに設けられた下層環状電源配線にも、ビアコンタクトを介して接続される
半導体集積回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008163111A JP5467736B2 (ja) | 2008-06-23 | 2008-06-23 | 半導体集積回路 |
US12/385,501 US8115325B2 (en) | 2008-06-23 | 2009-04-09 | Semiconductor integrated circuit including plurality of bonding pads |
CN200910203377.6A CN101615605B (zh) | 2008-06-23 | 2009-06-09 | 半导体集成电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008163111A JP5467736B2 (ja) | 2008-06-23 | 2008-06-23 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010003953A JP2010003953A (ja) | 2010-01-07 |
JP5467736B2 true JP5467736B2 (ja) | 2014-04-09 |
Family
ID=41430373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008163111A Expired - Fee Related JP5467736B2 (ja) | 2008-06-23 | 2008-06-23 | 半導体集積回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8115325B2 (ja) |
JP (1) | JP5467736B2 (ja) |
CN (1) | CN101615605B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5513902B2 (ja) | 2010-01-12 | 2014-06-04 | カヤバ工業株式会社 | トルクセンサ |
JP5498896B2 (ja) * | 2010-08-26 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | 半導体チップ |
JP5727288B2 (ja) * | 2011-04-28 | 2015-06-03 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の設計方法、半導体装置設計装置、及びプログラム |
CN102545827B (zh) * | 2012-01-04 | 2015-09-09 | 华为技术有限公司 | 薄膜体声波谐振器、通信器件和射频模块 |
JP2014033109A (ja) * | 2012-08-03 | 2014-02-20 | Renesas Electronics Corp | 半導体チップ |
US9929095B2 (en) * | 2014-11-06 | 2018-03-27 | Qualcomm Incorporated | IO power bus mesh structure design |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0183339U (ja) * | 1987-11-24 | 1989-06-02 | ||
JP2002016069A (ja) * | 2000-06-29 | 2002-01-18 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4460227B2 (ja) * | 2003-03-10 | 2010-05-12 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路 |
US6717270B1 (en) * | 2003-04-09 | 2004-04-06 | Motorola, Inc. | Integrated circuit die I/O cells |
JP4428514B2 (ja) * | 2004-03-30 | 2010-03-10 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
CN100421241C (zh) * | 2005-01-18 | 2008-09-24 | 松下电器产业株式会社 | 半导体集成电路 |
JP2007059867A (ja) * | 2005-07-26 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007305822A (ja) * | 2006-05-12 | 2007-11-22 | Kawasaki Microelectronics Kk | 半導体集積回路 |
JP5264135B2 (ja) * | 2006-11-09 | 2013-08-14 | パナソニック株式会社 | 半導体集積回路及びマルチチップモジュール |
JP5147234B2 (ja) * | 2006-12-28 | 2013-02-20 | パナソニック株式会社 | 半導体集積回路装置 |
US7554133B1 (en) * | 2008-05-13 | 2009-06-30 | Lsi Corporation | Pad current splitting |
-
2008
- 2008-06-23 JP JP2008163111A patent/JP5467736B2/ja not_active Expired - Fee Related
-
2009
- 2009-04-09 US US12/385,501 patent/US8115325B2/en not_active Expired - Fee Related
- 2009-06-09 CN CN200910203377.6A patent/CN101615605B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101615605B (zh) | 2014-02-12 |
JP2010003953A (ja) | 2010-01-07 |
CN101615605A (zh) | 2009-12-30 |
US20090315191A1 (en) | 2009-12-24 |
US8115325B2 (en) | 2012-02-14 |
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