CN106952884A - 扇出晶圆级封装 - Google Patents

扇出晶圆级封装 Download PDF

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CN106952884A
CN106952884A CN201610189227.4A CN201610189227A CN106952884A CN 106952884 A CN106952884 A CN 106952884A CN 201610189227 A CN201610189227 A CN 201610189227A CN 106952884 A CN106952884 A CN 106952884A
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layer
passivation layer
fan
out wafer
crystal grain
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CN106952884B (zh
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罗翊仁
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明涉及一种扇出晶圆级封装，包含有一重分布层；一被动器件，设在重分布层的第一金属层中；一第一钝化层，覆盖重分布层的上表面；一第二钝化层覆盖重分布层的下表面；一晶粒安装在第一钝化层上，晶粒包含一接点；一模塑料，设在晶粒周围及第一钝化层上；一导孔，贯穿第一钝化层、重分布层的介电层及第二钝化层，暴露出接点；一接触洞，设在第二钝化层中，暴露出被动器件的电极；以及一第二金属层，设在导孔及接触洞中，电连接被动器件的电极至晶粒的接点。

Description

扇出晶圆级封装
技术领域
本发明涉及半导体封装领域，特别是一种扇出晶圆级封装(fan-out wafer levelpackaging，FOWLP)。
背景技术
随着半导体制造工艺的进步，微电子器件的尺寸变得更小，器件中的电路也变得更密集。为了得到更小尺寸的微电子器件，其封装与安装到电路板上的结构都必须变得更紧密。
半导体封装技术领域中公知的嵌入晶圆球栅阵列(embedded wafer ball gridarray,eWLB)或扇出晶圆级封装(FOWLP)，是通过位于衬底上的重分布层(RDL)，例如位于具有穿硅通孔(TSV)的衬底，将原本半导体晶粒的接垫重新布线分配到一较大的区域。
重分布层是在晶圆表面上形成介电层与金属导线的叠层，将芯片原本的输入/输出(I/O)接垫重新布线分配到一个间距较宽松的布局范围。上述重布线的制作通常使用薄膜高分子聚合物，例如苯并环丁烯(benzocyclobutene,BCB)、聚酰亚胺(polyimide,PI)，或其他有机高分子聚合物作为介电层材料，再用金属化工艺，例如铝或铜，形成金属导线，将芯片周围的接垫重新布线分配成阵列状连接垫。
由于工艺繁复，具有穿硅通孔的中介层衬底成本较高，因此，使用具有穿硅通孔中介层的扇出晶圆级封装也会比较昂贵，并不利于特定的应用场合。
此外，晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的模塑料。此模塑料与集成电路衬底的热膨胀系数(CTE)差异，容易导致封装翘曲变形，也使得封装整体的厚度增加。晶圆翘曲一直是本领域关注的问题。
晶圆翘曲使芯片与晶圆间的接合不易维持，使“芯片对晶圆接合”(chip towafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重分布层的晶圆级半导体封装制，问题更为严重。因此，本领域仍需要一个改良的晶圆级封装方法，可以解决上述现有技术的问题。
发明内容
本发明的主要目的在提供一种改良的半导体装置及其制作方法，用来解决现有技术的不足与缺点。
根据本发明一实施例，提供一种扇出晶圆级封装，包含一重分布层，包含至少一介电层以及至少一第一金属层；一被动器件，设在所述重分布层的所述第一金属层中；一第一钝化层，覆盖所述重分布层的一上表面；一第二钝化层覆盖所述重分布层的一下表面；至少一晶粒安装在所述第一钝化层上，其中所述晶粒包含一接点，直接接触所述第一钝化层；一模塑料，设在所述晶粒周围以及所述第一钝化层上；一导孔，贯穿所述第一钝化层、所述介电层以及所述第二钝化层，以暴露出所述接点；一接触洞，设在所述第二钝化层中，暴露出所述被动器件的一电极；以及一第二金属层，设在所述导孔以及所述接触洞中，用来电连接所述被动器件的所述电极到所述晶粒的所述接点。
毋庸置疑的，本领域的技术人员读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1是依据本发明一实施例所绘示的扇出晶圆级封装的剖面示意图。
图2到图9是依据本发明一实施例所绘示的制作图1中扇出晶圆级封装的方法示意图。
其中，附图标记说明如下：
1 扇出晶圆级封装
300 载板
310 钝化层
310a 接触洞
400 中介层
410 重分布层
412 介电层
413 钝化层
414 金属层
420a、420b 晶粒
421 接点
480 贯通中介层导孔
482 金属层
482a 焊垫
500 模塑料
520 锡球
512 层间介电层
600 光刻胶图案
602 第一开口
604 第二开口
700 被动器件
702 电极
具体实施方式
接下来的详细叙述须参考相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例提供足够的细节，可使此领域中的技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义，也应属本发明涵盖的范围。
下面的描述须参考相关附图以便彻底理解本发明，其中相同或类似的特征通常用相同的附图标记描述，而且描述的结构并不必然按比例绘制。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”等词具有相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包含一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重分布层(RDL)。须了解的是“基板”包含半导体晶圆，但并不限于此。"基板"在工艺中也意指包含制作于其上的材料层的半导体结构物。
请参阅图1，是依据本发明一实施例所绘示的扇出晶圆级封装(fan-out waferlevel packaging，FOWLP)的剖面示意图。如图1所示，扇出晶圆级封装1包含一重分布层(redistribution layer,RDL)410。重分布层410包含至少一介电层412以及至少一金属层(第一金属层)414。介电层412可以包含无机材料，例如，氮化硅、氧化硅等，但不限于此。金属层414可以包含铝、铜、钨、钛、氮化钛等。需理解的是，金属层414可以包含多层的金属绕线，且介电层412可以包含多层的介电堆叠结构。
根据本发明一实施例，扇出晶圆级封装1可以另包含至少一被动器件700，例如，金属-绝缘-金属(metal-insulator-metal,MIM)电容，其制作于重分布层410中。根据本发明一实施例，被动器件700是嵌入埋设在介电层412中。
根据本发明一实施例，一钝化层413(或一黏着层)是层叠在重分布层410的上表面。钝化层413是直接接触到重分布层410的介电层412，并且覆盖部分的金属层414。例如，钝化层413可以包含聚合物，例如，苯并环丁烯(benzocyclobutene,BCB)，但不限于此。根据本发明一实施例，在安装贴合芯片之后，可以对钝化层413进行一固化工艺。含有如苯并环丁烯等聚合物的钝化层413可以被部分固化，例如，介于60％到80％之间的固化程度。
扇出晶圆级封装1另包含个别的覆晶芯片或晶粒420a及420b，其主动面朝下面对着重分布层410。所述晶粒420a及420b是被安装贴合在钝化层413上。所述晶粒420a及420b包含接点421，其包括，但不限于，设在输出/输入(input/output,I/O)垫上的金属凸块。这些输出/输入垫是分布在所述晶粒420a及420b的主动面上。为简化说明，在各个晶粒420a及420b上仅绘示出一个接点421。
另外，可选择在各个晶粒420a及420b下方形成一层间介电层512。所述层间介电层512可以形成在各个晶粒420a及420b与钝化层413之间，并且围绕接点421。
根据本发明一实施例，另包含一模塑料500，其包覆晶粒420a及420b以及钝化层413的上表面。可以对所述模塑料500进行一固化工艺。所述模塑料500可以包含环氧树脂以及硅土填料，但不限于此。
根据本发明一实施例，在重分布层410的一底表面上层叠有一钝化层310。所述钝化层310是直接接触到重分布层410的介电层412，并且覆盖部分的金属层414。所述钝化层310可以包含有机材料，例如，聚酰亚胺(polyimide,PI)，或者无机材料，例如，氮化硅、氧化硅等。根据本发明一实施例，重分布层410、钝化层(第一钝化层)310及钝化层(第二钝化层)413构成一中介层(或一中介层基板)400。
根据本发明一实施例，扇出晶圆级封装1另包含贯通中介层导孔(through-interposer-vias)480，设在钝化层310、介电层412及钝化层413中。所述贯通中介层导孔480贯穿中介层400的整个厚度，包括钝化层310、介电层412及钝化层413。所述贯通中介层导孔480是分别对准接点421。
根据本发明一实施例，所述贯通中介层导孔480是通过金属层(第二金属层)482金属化。例如，所述金属层482可以是一铜层，其可以利用电镀工艺或溅镀工艺形成，但不限于此。所述金属层482可以是共形的沉积在贯通中介层导孔480的内壁上，且可以包含一焊垫482a在钝化层310上。
根据本发明一实施例，在钝化层310中可以形成一接触洞310a，暴露出被动器件700的一电极702。金属层482可以填入接触洞310a中，以电连接被动器件700的电极702。在金属层482的焊垫482a上可以形成有锡球520，用来供进一步连结到，例如，一主机板或一电路板。金属层482及414，以及金属化的贯通中介层导孔480，共同构成晶粒420a及晶粒420b之间的芯片内连结。
值得注意的是，根据本发明一实施例，在重分布层410上不需要形成任何的微凸块(micro-bumps)。换句话说，晶粒420a及420b并不是通过微凸块电连结到重分布层410。根据本发明一实施例，晶粒420a及420b是通过金属化的贯通中介层导孔480以及金属层482电连结到重分布层410及/或被动器件700。通过去除微凸块，扇出晶圆级封装的整体厚度可以被降低。
请参阅图2至图9，是依据本发明一实施例所绘示的制作晶圆级封装的方法示意图。
如图2所示，首先提供一载板300，其中载板300可以是一晶圆或一基板材料，其上具有一黏着层(图未明示)，但不限于此。例如，载板300可以包含一玻璃基板或一硅基板。接着，于载板300的一上表面形成至少一介电层或一钝化层310。所述钝化层310可以包含有机材料，例如，聚酰亚胺，或者无机材料，例如，氮化硅、氧化硅等。
接着，在钝化层310上形成一重分布层410。所述重分布层410可以包含至少一介电层412以及至少一金属层414。介电层412可以包含无机材料，例如，氮化硅、氧化硅等，但不限于此。
金属层414可以包含铝、铜、钨、钛、氮化钛等。重分布层410中包含至少一被动器件700，例如，金属-绝缘-金属(metal-insulator-metal,MIM)电容，其嵌入埋设在介电层412中。
根据本发明一实施例，一钝化层413(或一黏着层)是层叠在重分布层410的上表面。钝化层413是直接接触到重分布层410的介电层412，并且覆盖部分的金属层414。例如，钝化层413可以包含聚合物，例如，苯并环丁烯(benzocyclobutene,BCB)，但不限于此。根据本发明一实施例，在安装贴合芯片之后，可以对钝化层413进行一固化工艺。含有如苯并环丁烯等聚合物的钝化层413可以被部分固化，例如，介于60％到80％之间的固化程度。重分布层410、钝化层310及413构成一中介层(或一中介层基板)400。
如图3所示，接着，将个别的覆晶芯片或晶粒420a及420b，使其主动面朝下面对着重分布层410，安装贴合在钝化层413上，如此构成一芯片对晶圆堆叠(chip-to-wafer,C2W)结构。所述晶粒420a及420b包含接点421，其包括，但不限于，设在输出/输入垫上的金属凸块。这些输出/输入垫是分布在所述晶粒420a及420b的主动面上。
为简化说明，在各个晶粒420a及420b上仅绘示出一个接点421。此时，接点421是直接接触到钝化层413，且被钝化层413所覆盖。
另外，可选择在各个晶粒420a及420b下方形成一层间介电层512。所述层间介电层512可以形成在各个晶粒420a及420b与钝化层413之间，并且围绕接点421。
如图4所示，在贴合芯片之后，可以形成一模塑料500。模塑料500包覆晶粒420a及420b以及钝化层413的上表面。可以对所述模塑料500进行一固化工艺。所述模塑料500可以包含环氧树脂以及硅土填料，但不限于此。此外，可选择对模塑料500的上表面进行一抛光工艺，用来去除部分的模塑料500。
此时，根据本发明一实施例，晶粒420a及420b的上表面是与模塑料500的上表面齐平。根据本发明一实施例，在上述抛光工艺中，晶粒420a及420b的一上部可以选择被抛光掉。
如图5所示，接着可以进行另一抛光工艺，例如，化学机械抛光(chemicalmechanical polishing,CMP)工艺，用来抛光掉载板300，直到钝化层310被暴露出来。需理解的是，去除载板300的方法不限于抛光方式，也可以使用其它方法。
如图6所示，接着在钝化层310上形成一光刻胶图案600。光刻胶图案600包含一第一开口602，定义出后续将形成于中介层400内的一贯通中介层导孔的图案及位置，以及一第二开口604，定义出后续用来暴露出被动器件700的电极的一接触洞的图案及位置。
如图7所示，进行一各向异性干蚀刻工艺，经由第一开口602及第二开口604蚀刻中介层400，在钝化层310、介电层412及钝化层413中形成至少一贯通中介层导孔480，以及在钝化层310中形成一接触洞310a。所述贯通中介层导孔480贯穿中介层400的整个厚度，包括钝化层310、介电层412及钝化层413。所述贯通中介层导孔480是分别对准接点421并且暴露出部分的接点421。接触洞310a暴露出被动器件700的部分的电极702。
根据本发明一实施例，上述工艺步骤可以被称为“导孔后制(via-last)”工艺，因为所述贯通中介层导孔480是在中介层400形成后、晶粒或芯片安装贴合工艺、以及成型工艺后，始开始制作。
如图8所示，进行一电镀工艺，例如，一溅射电镀(sputter plating)工艺，将贯通中介层导孔480以及接触洞310a金属化。在上述电镀工艺中，金属层482，例如，铜层，被共形的沉积到贯通中介层导孔480的内壁上，并且可以填满接触洞310a，如此使接点421电连接至被动器件700的电极702。金属层482可以包含一焊垫482a，设在钝化层310上。
如图9所示，在金属层482的焊垫482a上形成锡球520，以供进一步连结到，例如，一主机板或一电路板。金属层482及414，以及金属化的贯通中介层导孔480共同构成晶粒420a及晶粒420b之间的芯片内连结。最后，图中的晶圆级封装再被切割形成个别的芯片封装。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

1.一种扇出晶圆级封装，其特征在于，包含有：
一重分布层，包含至少一介电层，以及至少一第一金属层；
一被动器件，设在所述重分布层的所述第一金属层中；
一第一钝化层，覆盖所述重分布层的一上表面；
一第二钝化层，覆盖所述重分布层的一下表面；
至少一晶粒安装在所述第一钝化层上，其中所述晶粒包含一接点，直接接触所述第一钝化层；
一模塑料，设在所述晶粒周围以及所述第一钝化层上；
一导孔，贯穿所述第一钝化层、所述介电层以及所述第二钝化层，以暴露出所述接点；
一接触洞，设在所述第二钝化层中，暴露出所述被动器件的一电极；以及
一第二金属层，设在所述导孔以及所述接触洞中，用来电连接所述被动器件的所述电极至所述晶粒的所述接点。
2.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述介电层包含无机材料。
3.根据权利要求2所述的扇出晶圆级封装，其特征在于，所述无机材料包含氮化硅或氧化硅。
4.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述被动器件包含一金属-绝缘-金属电容。
5.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述第一钝化层包含苯并环丁烯。
6.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述第一金属层包含铝、铜、钨、钛或氮化钛。
7.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述第二金属层包含铜。
8.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述第二金属层另包含一焊垫，设在所述第二钝化层上。
9.根据权利要求8所述的扇出晶圆级封装，其特征在于，另包含一锡球，设在所述焊垫上。
10.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述接点包含设在所述晶粒的主动面上的一输出/输入垫以及设在所述输出/输入垫上的一金属凸块。
11.根据权利要求1所述的扇出晶圆级封装，其特征在于，所述重分布层、所述第一钝化层及所述第二钝化层构成一中介层。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390306A (zh) * 2017-08-02 2019-02-26 矽品精密工业股份有限公司 电子封装件
US10593629B2 (en) 2018-07-09 2020-03-17 Powertech Technology Inc. Semiconductor package with a conductive casing for heat dissipation and electromagnetic interference (EMI) shield and manufacturing method thereof

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721923B1 (en) * 2016-04-14 2017-08-01 Micron Technology, Inc. Semiconductor package with multiple coplanar interposers
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
TWI659515B (zh) * 2018-07-26 2019-05-11 欣興電子股份有限公司 封裝結構及其製造方法
WO2020133420A1 (zh) * 2018-12-29 2020-07-02 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
CN109940285B (zh) * 2019-03-22 2020-10-16 苏州福唐智能科技有限公司 一种扇出形晶圆激光隐形切割方法
US20220310777A1 (en) * 2021-03-26 2022-09-29 Intel Corporation Integrated circuit package redistribution layers with metal-insulator-metal (mim) capacitors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425510A (zh) * 2007-11-01 2009-05-06 育霈科技股份有限公司 半导体元件的叠层封装结构及其方法
CN102804364A (zh) * 2009-06-26 2012-11-28 英特尔公司 封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的系统
US20150228632A1 (en) * 2014-02-13 2015-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
TW201601214A (zh) * 2014-06-27 2016-01-01 台灣積體電路製造股份有限公司 封裝半導體裝置之方法及封裝的半導體裝置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770955B1 (en) * 2001-12-15 2004-08-03 Skyworks Solutions, Inc. Shielded antenna in a semiconductor package
IL175011A (en) * 2006-04-20 2011-09-27 Amitech Ltd Coreless cavity substrates for chip packaging and their fabrication
US20080237828A1 (en) * 2007-03-30 2008-10-02 Advanced Chip Engineering Technology Inc. Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for wlp and method of the same
US7648911B2 (en) * 2008-05-27 2010-01-19 Stats Chippac, Ltd. Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias
US8344506B2 (en) * 2009-12-08 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Interface structure for copper-copper peeling integrity
JP5897486B2 (ja) * 2013-03-14 2016-03-30 株式会社東芝 半導体装置
US10074631B2 (en) * 2014-04-14 2018-09-11 Taiwan Semiconductor Manufacturing Company Packages and packaging methods for semiconductor devices, and packaged semiconductor devices
US9899442B2 (en) * 2014-12-11 2018-02-20 Invensas Corporation Image sensor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101425510A (zh) * 2007-11-01 2009-05-06 育霈科技股份有限公司 半导体元件的叠层封装结构及其方法
CN102804364A (zh) * 2009-06-26 2012-11-28 英特尔公司 封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的系统
US20150228632A1 (en) * 2014-02-13 2015-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
TW201601214A (zh) * 2014-06-27 2016-01-01 台灣積體電路製造股份有限公司 封裝半導體裝置之方法及封裝的半導體裝置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390306A (zh) * 2017-08-02 2019-02-26 矽品精密工业股份有限公司 电子封装件
US10593629B2 (en) 2018-07-09 2020-03-17 Powertech Technology Inc. Semiconductor package with a conductive casing for heat dissipation and electromagnetic interference (EMI) shield and manufacturing method thereof

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