CN109860140A - 电子封装件及其制法 - Google Patents
电子封装件及其制法 Download PDFInfo
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- CN109860140A CN109860140A CN201711440046.5A CN201711440046A CN109860140A CN 109860140 A CN109860140 A CN 109860140A CN 201711440046 A CN201711440046 A CN 201711440046A CN 109860140 A CN109860140 A CN 109860140A
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- 238000012856 packing Methods 0.000 title claims abstract description 74
- 238000002360 preparation method Methods 0.000 title claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 132
- 238000009413 insulation Methods 0.000 claims abstract description 67
- 239000000463 material Substances 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 238000004806 packaging method and process Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005253 cladding Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 10
- 239000011230 binding agent Substances 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 241000196324 Embryophyta Species 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- CLDVQCMGOSGNIW-UHFFFAOYSA-N nickel tin Chemical compound [Ni].[Sn] CLDVQCMGOSGNIW-UHFFFAOYSA-N 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 241000219000 Populus Species 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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Abstract
一种电子封装件及其制法,包括:具有第一绝缘部的第一基板、设于该第一基板上的第一电子元件、通过多个导电元件堆叠于该第一基板上并具有第二绝缘部的第二基板、以及形成于该第一基板与第二基板之间的第一封装层,通过该第一基板的第一绝缘部的刚性不同于该第二基板的第二绝缘部的刚性,以于高温制程时,该第一基板与第二基板的其中一者会拉动另一者朝同一方向发生弯曲,以减少该电子封装件的整体翘曲程度。
Description
技术领域
本发明关于一种封装结构,特别是关于一种电子封装件及其制法。
背景技术
随着近年来可携式电子产品的蓬勃发展,各类相关产品也逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展,为因应此趋势,半导体封装业界遂开发各态样的封装堆叠(package on package,简称PoP)技术,以期能符合轻薄短小与高密度的要求。
如图1所示,其为现有堆叠式电子封装件1的剖视示意图。该电子封装件1包括两相叠的第一封装结构1a与第二封装结构1b,以及黏固该第一封装结构1a与第二封装结构1b的封装胶体13。该第一封装结构1a包含第一基板10、以多个导电凸块110覆晶结合该第一基板10的第一电子元件11(如半导体晶片)、及包覆该些导电凸块110的底胶111。该第二封装结构1b包含第二基板12、以多个导电凸块140覆晶结合该第二基板12的第二电子元件14(如半导体晶片)、及包覆该些导电凸块140的底胶141。于制作时,先将该第二基板12通过焊锡球120堆叠且电性连接于该第一基板10上,再将该封装胶体13形成于该第一基板10与第二基板12之间以包覆该些焊锡球120与该第一电子元件11,之后设置该第二电子元件14于该第二基板12上。传统制程中,为了减少该电子封装件1的整体翘曲程度(warpage),该第一基板10与第二基板12的绝缘材质选用低膨胀系数及高刚性的材料。
惟,现有电子封装件1中,该第一基板10与第二基板12的厚度d1,d2及配置(线路布设方式或晶片布设方式)不同,导致于高温制程时,该第一基板10与第二基板12会互相拉扯,并朝不同方向发生弯曲(如图1所示的该第一基板10与第二基板12的虚线态样),使得该电子封装件1的整体翘曲程度的偏差(deviation)变大。
因此,如何克服上述现有技术的问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失,本发明提供一种电子封装件及其制法,可减少该电子封装件的整体翘曲程度。
本发明的电子封装件,包括:第一基板,其包含有第一绝缘部;第一电子元件,其设于该第一基板上;第二基板,其包含有第二绝缘部且通过多个导电元件堆叠于该第一基板上,其中,该第一绝缘部的刚性不同于该第二绝缘部的刚性;以及第一封装层,其形成于该第一基板与第二基板之间,以包覆该第一电子元件与该导电元件。
本发明还提供一种电子封装件的制法,包括:提供包含有第一绝缘部的第一基板及包含有第二绝缘部的第二基板,其中,该第一基板上设有第一电子元件,且该第一绝缘部的刚性不同于该第二绝缘部的刚性;将该第二基板通过多个导电元件堆叠于该第一基板上;以及形成第一封装层于该第一基板与第二基板之间,以包覆该第一电子元件与该导电元件。
前述的电子封装件及其制法中,该第一绝缘部的刚性大于或小于该第二绝缘部的刚性。
前述的电子封装件及其制法中,该导电元件为金属块,或者,该导电元件具有金属块与包覆该金属块的导电材。
前述的电子封装件及其制法中,该导电元件为焊锡凸块。
前述的电子封装件及其制法中,还包括设置支撑件于该第一与第二基板之间,且该支撑件未电性连接该第一与第二基板。
前述的电子封装件及其制法中,还包括设置第二电子元件于该第二基板上,并形成第二封装层于该第二基板上,且该第二封装层包覆该第二电子元件。
前述的电子封装件及其制法中,还包括设置封装件于该第二基板上。
前述的电子封装件及其制法中,该第一与第二绝缘部的刚性较低者的材质为环氧树脂绝缘膜(AjinomotoBuild-up Film,简称ABF)、聚酰亚胺或感光性介电层。
前述的电子封装件及其制法中,该第一与第二绝缘部的刚性较高者的材质为预浸材。
前述的电子封装件及其制法中,该第一与第二绝缘部的其中一者的杨氏系数小于15GPa,而另一者大于15GPa。
前述的电子封装件及其制法中,该第一与第二绝缘部的其中一者的杨氏系数为2.5至15GPa。
前述的电子封装件及其制法中,该第一与第二绝缘部的其中一者的杨氏系数大于20GPa。
由上可知,本发明的电子封装件及其制法中,主要通过该第一基板的第一绝缘部的刚性不同于该第二基板的第二绝缘部的刚性,以于高温制程时,该第一基板与第二基板的其中一者会拉动另一者朝同一方向发生弯曲,故相比于现有技术,本发明的电子封装件于高温制程时可减少其整体翘曲程度。
附图说明
图1为现有堆叠式电子封装件的剖面示意图;
图2A至图2C为本发明电子封装件的制法的剖面示意图;其中,图2B’为图2B的另一实施例;以及
图2D及图2D’为图2C的其它实施例的剖面示意图。
符号说明:
1,2,2’,2” 电子封装件
1a 第一封装结构
1b 第二封装结构
10,20 第一基板
11,21 第一电子元件
110,140,210 导电凸块
111,141 底胶
12,22 第二基板
120 焊锡球
13 封装胶体
14,24 第二电子元件
20a,20b 第一线路层
20c 第一绝缘部
20d,22d 防焊材
200 电性接触垫
201,202,220,221 电性接点
203 植球垫
22a,22b 第二线路层
22c 第二绝缘部
23 第一封装层
240 焊线
241 黏着层
25 第二封装层
26 封装件
260 载体
261 第三电子元件
262 封装体
263,28 焊球
27 支撑件
270,280 金属块
271,281 导电材
28a 第一导电元件
28b 第二导电元件
29 结合层
30 定位垫
d1,d2 厚度
S 切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“下”、及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
请参阅图2A至图2C,其为本发明的电子封装件2的制法的剖面示意图。
如图2A所示,提供一第一基板20与一第二基板22。该第一基板20上设有至少一第一电子元件21,且该第二基板22下侧形成有多个第一导电元件28a、多个第二导电元件28b与一如薄膜(film)或散热材的结合层29。
于本实施例中,该第一基板20与第二基板22为线路板,其分别具有第一绝缘部20c与第二绝缘部22c、多个第一线路层20a,20b与多个第二线路层22a,22b,该第一线路层20a,20b结合该第一绝缘部20c且包含电性接触垫200、电性接点201,202与植球垫203,且该第二线路层22a,22b包含电性接点220,221,其中,该第一绝缘部20c(不含防焊材20d)为低膨胀系数及高刚性(杨氏系数(Young's Modulus)约为15GPa以上,较佳为20GPa以上)的介电材,例如预浸材(Prepreg,简称PP)(约15~27GPa)等;该第二绝缘部22c(不含防焊材22d)为低膨胀系数及低刚性(杨氏系数(Young's Modulus)约为15GPa以下,较佳为2.5~15GPa)的介电材,例如环氧树脂绝缘膜
(AjinomotoBuild-up Film,简称ABF)(约4~13GPa)、聚酰亚胺
(Polyimide,简称PI)(约2.5GPa)、感光性介电层
(Photo-Imageable dielectric,简称PID)(约3~4GPa)等。
此外,该第一电子元件21可例如通过多个导电凸块210以覆晶方式设于该第一基板20上侧的电性接触垫200上。
又,该第一导电元件28a形成于该第二基板22下侧的电性接点220上,且该第一导电元件28a具有金属块280与包覆该金属块280的导电材281,抑或该第一导电元件28a仅为金属块280(不含导电材),其中,该金属块280例如为铜球或铜柱,且该导电材281为焊锡材,如镍锡、锡铅或锡银,但不限于此。
另外,该第二导电元件28b形成于该第二基板22下侧的电性接点221上,且该第二导电元件28b为焊锡凸块。
如图2B所示,将该第二基板22堆叠于该第一基板20上,其中,该第二基板22透过该结合层29结合于该第一电子元件21上,并令该些第一导电元件28a与第二导电元件28b电性连接该第一基板20的电性接点201,202,使该第二基板22通过该些第一导电元件28a与第二导电元件28b电性连接该第一基板20。
应可理解地,如图2B’所示,也可先将该结合层29设于该第一电子元件21上,另该第一导电元件28a与第二导电元件28b先设于该第一基板20的电性接点201,202上,再堆叠该第二基板22于该第一基板20上,以呈现图2B的状态。
如图2C所示,形成第一封装层23于该第一基板20上侧与该第二基板22下侧之间,使该第一封装层23包覆该第一电子元件21、该些第一导电元件28a与第二导电元件28b、该结合层29与该些导电凸块210。
接着,沿切割路径S进行切单制程,以制成多个电子封装件2。
于本实施例中,由于该结合层29形成于该第二基板22与该第一电子元件21之间,故该第一封装层23不会填入该第二基板22与该第一电子元件21之间。
此外,该第一基板20下侧的植球垫203上可形成有如焊球28的导电元件,以供接置如电路板或另一线路板的电子结构。
于另一实施例中,如图2D所示的电子封装件2’中,可通过一黏着层241设置至少一第二电子元件24于该第二基板22上侧上,再形成第二封装层25于该第二基板22上侧,且该第二封装层25包覆该第二电子元件24。例如,该第二电子元件24通过多个焊线240以打线方式电性连接该第二基板22上侧的第二线路层22a,且该第二封装层25还包覆该些焊线240。于其它实施例中,该第二电子元件24也可以覆晶方式设于该第二基板22上侧。
或者,如图2D’所示,也可设置至少一封装件26于该第二基板22上。例如,该封装件26包含一载体260、设置并电性连接至该载体260的第三电子元件261、及包覆该第三电子元件261的封装体262。具体地,该封装件26通过多个如焊球263的导电元件电性连接该第二基板22,且该第三电子元件261的封装方式可为打线(如图2D’所示)、覆晶或嵌埋等,但并无特别限制。
于另一实施例中,如图2D所示,也可设置至少一支撑件27于该第一与第二基板20,22之间,使该第二基板22通过该支撑件27堆叠于该第一基板20上,且该第一封装层23还包覆该支撑件27。
具体地,该支撑件27的构造类似该第一导电元件28a的构造,即具有金属块270与包覆该金属块270的导电材271,其中,该金属块270为铜球,且该导电材271为焊锡材,如镍锡、锡铅或锡银,但不限于此。
此外,于制程中,该支撑件27可与该第一导电元件28a一同制作,且该第一基板20与第二基板22可通过定位垫30的设计,以利于该支撑件27的定位。具体地,该定位垫30未电性连接该第一基板20的第一线路层20a,20b与该第二基板22的第二线路层22a,22b,致使该支撑件27未电性连接该第一基板20与第二基板22,因而该支撑件27可视为虚设金属件(dummy metal member)。应可理解地,如图2D’所示,该支撑件27也可直接设于该第一基板20的表面与该第二基板22的表面,而省略该定位垫30的制作。
另外,上述电子元件(如第一电子元件21、第二电子元件24或第三电子元件261)为主动元件、被动元件或其二者组合等,其中,该主动元件为例如半导体晶片,且该被动元件为例如电阻、电容及电感。
本发明的制法中,通过该第一基板20的第一绝缘部20c的刚性不同于(高于)该第二基板20的第二绝缘部22c的刚性,以于高温制程时,该第一基板20会拉动该第二基板22朝同一方向发生弯曲,故相比于现有技术,本发明的电子封装件2,2’,2”于高温制程时可减少其整体翘曲程度的偏差。
应可理解地,也可令该第一基板20的第一绝缘部20c的刚性小于该第二基板20的第二绝缘部22c的刚性,以于高温制程时,该第二基板22会拉动该第一基板20朝同一方向发生弯曲。
本发明提供一种电子封装件2,2’,2”,其包括:具有第一绝缘部20c的第一基板20、设于该第一基板20上的第一电子元件21、通过多个第一导电元件28a与第二导电元件28b堆叠于该第一基板20上的第二基板22、以及设于该第一基板20与第二基板22之间的第一封装层23。
所述的第一电子元件21通过多个导电凸块210设于该第一基板20上。
所述的第二基板22具有刚性不同于该第一绝缘部20c的第二绝缘部22c,且通过该些第一导电元件28a与第二导电元件28b电性连接该第一基板20。例如,该第一导电元件28a为金属块、或具有金属块280与包覆该金属块280的导电材281,且该第二导电元件28b为焊锡凸块。
所述的第一封装层23包覆该第一电子元件21、该些第一导电元件28a与第二导电元件28b。
于一实施例中,该电子封装件2’,2”还包括至少一支撑件27,其设于该第一与第二基板20,22之间。例如,该支撑件27未电性连接该第一与第二基板20,22。
于一实施例中,该电子封装件2’还包括设于该第二基板22上的第二电子元件24及第二封装层25,且该第二封装层25包覆该第二电子元件24。
于一实施例中,该电子封装件2”还包括设于该第二基板22上的至少一封装件26。
于一实施例中,该第一绝缘部20c的刚性较高,其材质为预浸材。
于一实施例中,该第二绝缘部22c的刚性较低,其材质为环氧树脂绝缘膜(AjinomotoBuild-up Film,简称ABF)、聚酰亚胺或感光性介电层。
于一实施例中,该第一绝缘部20c的杨氏系数大于15GPa,而该第二绝缘部22c的杨氏系数小于15GPa。
于一实施例中,该第一绝缘部20c的杨氏系数大于20GPa。
于一实施例中,该第二绝缘部22c的杨氏系数为2.5至15GPa。
综上所述,本发明的电子封装件及其制法,主要通过该第一基板的刚性不同于该第二基板的刚性,以于高温制程时,该第一与第二基板的其中一者会拉动另一者朝同一方向发生弯曲,故相比于现有技术,本发明的电子封装件于高温制程时可减少其整体翘曲程度的偏差。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (30)
1.一种电子封装件,其特征在于,包括:
第一基板,其包含有第一绝缘部;
第一电子元件,其设于该第一基板上;
第二基板,其包含有第二绝缘部且通过多个导电元件堆叠于该第一基板上,其中,该第一绝缘部的刚性不同于该第二绝缘部的刚性;以及
第一封装层,其形成于该第一基板与第二基板之间,以包覆该第一电子元件与该导电元件。
2.根据权利要求1所述的电子封装件,其特征在于,该第一绝缘部的刚性大于或小于该第二绝缘部的刚性。
3.根据权利要求1所述的电子封装件,其特征在于,该导电元件为金属块。
4.根据权利要求1所述的电子封装件,其特征在于,该导电元件包含有金属块与包覆该金属块的导电材。
5.根据权利要求1所述的电子封装件,其特征在于,该导电元件为焊锡凸块。
6.根据权利要求1所述的电子封装件,其特征在于,该电子封装件还包括设于该第一基板与第二基板之间的支撑件。
7.根据权利要求6所述的电子封装件,其特征在于,该支撑件未电性连接该第一基板与第二基板。
8.根据权利要求1所述的电子封装件,其特征在于,该电子封装件还包括设于该第二基板上的第二电子元件。
9.根据权利要求8所述的电子封装件,其特征在于,该电子封装件还包括形成于该第二基板上且包覆该第二电子元件的第二封装层。
10.根据权利要求1所述的电子封装件,其特征在于,该电子封装件还包括设于该第二基板上的封装件。
11.根据权利要求1所述的电子封装件,其特征在于,该第一与第二绝缘部的刚性较低者的材质为环氧树脂绝缘膜(AjinomotoBuild-up Film,简称ABF)、聚酰亚胺或感光性介电层。
12.根据权利要求1所述的电子封装件,其特征在于,该第一与第二绝缘部的刚性较高者的材质为预浸材。
13.根据权利要求1所述的电子封装件,其特征在于,该第一与第二绝缘部的其中一者的杨氏系数小于15GPa,而另一者大于15GPa。
14.根据权利要求1所述的电子封装件,其特征在于,该第一与第二绝缘部的其中一者的杨氏系数为2.5至15GPa。
15.根据权利要求1所述的电子封装件,其特征在于,该第一与第二绝缘部的其中一者的杨氏系数大于20GPa。
16.一种电子封装件的制法,其特征在于,该制法包括:
提供包含有第一绝缘部的第一基板及包含有第二绝缘部的第二基板,其中,该第一基板上设有第一电子元件,且该第一绝缘部的刚性不同于该第二绝缘部的刚性;
将该第二基板通过多个导电元件堆叠于该第一基板上;以及
形成第一封装层于该第一基板与第二基板之间,以包覆该第一电子元件与该导电元件。
17.根据权利要求16所述的电子封装件的制法,其特征在于,该第一绝缘部的刚性大于或小于该第二绝缘部的刚性。
18.根据权利要求16所述的电子封装件的制法,其特征在于,该导电元件为金属块。
19.根据权利要求16所述的电子封装件的制法,其特征在于,该导电元件包含有金属块与包覆该金属块的导电材。
20.根据权利要求16所述的电子封装件的制法,其特征在于,该导电元件为焊锡凸块。
21.根据权利要求16所述的电子封装件的制法,其特征在于,该制法还包括设置支撑件于该第一基板与第二基板之间。
22.根据权利要求21所述的电子封装件的制法,其特征在于,该支撑件未电性连接该第一基板与第二基板。
23.根据权利要求16所述的电子封装件的制法,其特征在于,该制法还包括设置第二电子元件于该第二基板上。
24.根据权利要求23所述的电子封装件的制法,其特征在于,该制法还包括形成第二封装层于该第二基板上,以包覆该第二电子元件。
25.根据权利要求16所述的电子封装件的制法,其特征在于,该制法还包括设置封装件于该第二基板上。
26.根据权利要求16所述的电子封装件的制法,其特征在于,该第一与第二绝缘部的刚性较低者的材质为环氧树脂绝缘膜(AjinomotoBuild-up Film,简称ABF)、聚酰亚胺或感光性介电层。
27.根据权利要求16所述的电子封装件的制法,其特征在于,该第一与第二绝缘部的刚性较高者的材质为预浸材。
28.根据权利要求16所述的电子封装件的制法,其特征在于,该第一与第二绝缘部的其中一者的杨氏系数小于15GPa,而另一者大于15GPa。
29.根据权利要求16所述的电子封装件的制法,其特征在于,该第一与第二绝缘部的其中一者的杨氏系数为2.5至15GPa。
30.根据权利要求16所述的电子封装件的制法,其特征在于,该第一与第二绝缘部的其中一者的杨氏系数大于20GPa。
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