CN110718541A - 包括应力均衡芯片的半导体封装件 - Google Patents

包括应力均衡芯片的半导体封装件 Download PDF

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CN110718541A
CN110718541A CN201910119871.8A CN201910119871A CN110718541A CN 110718541 A CN110718541 A CN 110718541A CN 201910119871 A CN201910119871 A CN 201910119871A CN 110718541 A CN110718541 A CN 110718541A
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chip
semiconductor
stress
equalizing
semiconductor chip
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金一浩
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本申请提供一种半导体封装件。所述半导体封装件包括具有竖直地堆叠在封装件衬底上的多个半导体芯片的芯片堆叠件。应力均衡芯片布置在所述芯片堆叠件上，所述应力均衡芯片构造为提供减小所述多个半导体芯片之间的电特性的变化。密封剂布置在所述封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分。所述多个半导体芯片中的每一个电连接至所述封装件衬底。所述应力均衡芯片不电连接至所述衬底或所述多个半导体芯片。

Description

包括应力均衡芯片的半导体封装件
相关申请的交叉引用
该申请要求于2018年7月13日在韩国知识产权局(KIPO)提交的韩国专利申请No.10-2018-0081546的优先权，该申请的公开内容通过引用方式整体并入本文中。
技术领域
根据示例实施例的封装件涉及一种在芯片堆叠件上包括应力均衡芯片的多芯片半导体封装件。
背景技术
多芯片半导体封装件在减轻电子设备的重量、厚度和尺寸方面具有优势，从而使半导体装置小型化。多芯片半导体封装件具有多个半导体芯片堆叠的结构。所述多个半导体芯片堆叠的结构根据所述半导体芯片的堆叠位置而受到不同量的应力。由于应力奇点的出现，多个半导体芯片的电特性的分布增加。某些应力可能导致压电效应，在压电效应中，电路的电气特性由于半导体芯片上的物理应力而改变。
发明内容
示例实施例旨在提供一种能够减小由特定应力导致的特定电特性的分布的半导体封装件及形成所述半导体封装件的方法。
根据示例实施例，一种半导体封装件包括具有竖直地堆叠在封装件衬底上的多个半导体芯片的芯片堆叠件。应力均衡芯片布置在所述芯片堆叠件上，所述应力均衡芯片构造为减小所述多个半导体芯片之间的电特性的变化。密封剂布置在封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分。所述多个半导体芯片中的每一个电连接至所述封装件衬底。所述应力均衡芯片不电连接至所述封装件衬底或所述多个半导体芯片。
根据可包括上述实施例的示例实施例，一种半导体封装件包括芯片堆叠件，其具有封装件衬底上的多个半导体芯片。作为虚设芯片的应力均衡芯片布置在芯片堆叠件上。密封剂布置在所述封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分。所述多个半导体芯片包括布置在所述芯片堆叠件的最上层处的最上面的半导体芯片和所述最上面的半导体芯片下方的多个下半导体芯片。所述多个半导体芯片中的每个半导体芯片与邻近的半导体芯片分隔开第一竖直距离。所述应力均衡芯片与所述最上面的半导体芯片分隔开第一竖直距离。
根据示例实施例，一种半导体封装件包括芯片堆叠件，其具有在封装件衬底上偏移地堆叠的多个半导体芯片。虚设芯片堆叠在所述芯片堆叠件上，并且相对于所述多个半导体芯片中的最上面的半导体芯片偏移布置，并且与所述多个半导体芯片中的每一个具有相同的宽度和长度。密封剂布置在所述封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分。所述多个半导体芯片中的每一个包括非易失性存储器。虚设芯片包括半导体衬底、一个或多个金属层以及一个或多个绝缘层，构造为减小所述多个半导体芯片之间的电特性变化,并且所述虚设芯片不电连接至封装件衬底的电路。
附图说明
图1至图3是用于描述根据示例实施例的半导体封装件的剖视图。
图4和图5是用于描述根据示例实施例的半导体封装件的俯视图。
图6至图17是用于描述根据示例实施例的半导体封装件的剖视图。
具体实施方式
图1至图3是用于描述根据示例实施例的半导体封装件的剖视图。
参照图1，根据本发明构思的示例实施例的半导体封装件可包括衬底21、多个突出电极23、芯片堆叠件30、多个粘合剂41、多个互连部分45、密封剂56和应力均衡芯片139。衬底21可包括多个外部端子24、内部互连部分25和至少一个内部端子27。芯片堆叠件30可包括多个半导体芯片31、32、33、34、35、36、37和38。所述多个半导体芯片31、32、33、34、35、36、37和38可包括第一半导体芯片31、第二半导体芯片32、第三半导体芯片33、第四半导体芯片34、第五半导体芯片35、第六半导体芯片36、第七半导体芯片37和第八半导体芯片38，所述半导体芯片可竖直地堆叠在衬底21上。所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可包括至少一个应力敏感区149和至少一个芯片焊盘43。
衬底21可包括诸如刚性印刷电路板、柔性印刷电路板、刚性-柔性印刷电路板或它们的组合的封装件衬底。衬底21可为多层电路板。所述多个外部端子24可布置在衬底21的下表面上，并且所述至少一个内部端子27可布置在衬底21的上表面上。所述至少一个内部端子27可经由衬底21内的内部互连部分25电连接至选自所述多个外部端子24中的一个。所述多个突出电极23中的每一个可形成在所述多个外部端子24中的每一个上。
所述多个突出电极23可包括焊料球、导电凸块、导电片、导电线或者它们的组合。所述多个外部端子24、内部互连部分25和所述至少一个内部端子27可包括诸如金属、金属氮化物、导电碳或者它们的组合的导电材料。例如，所述多个外部端子24、内部互连部分25和所述至少一个内部端子27可包括铜(Cu)。所述至少一个内部端子27可对应于指形焊点(bond finger)。在示例实施例中，可选择性地省略所述多个外部端子24和所述多个突出电极23。衬底21可对应于主板或插入器。
所述多个外部端子24和所述至少一个内部端子27中的每一个可为形成在衬底21的表面并且具有平坦表面的导电焊盘，所述平坦表面可与衬底21的表面共面。另外，突出电极23可自己或与对应的外部端子24组合被称为外部端子或外部封装件端子。内部互连部分25可被称作内部导电互连部分或内部布线。
如本文所用，被描述为“电连接”的组件被构造成使得可以从一个组件向另一个组件地、通过组件电传递电信号。因此，诸如电线、焊盘、内部电线、晶体管、电容器等物理地连接至电绝缘组件(例如，印刷电路板的预浸渍层、连接两个装置的电绝缘粘合剂、电绝缘底部填充物或模具层等)并且不通过该电绝缘组件电传递信号的组件不与该组件电连接。
所述多个半导体芯片31、32、33、34、35、36、37和38可包括非易失性存储器、易失性存储器、微处理器、应用处理器、控制器、图像传感器或者它们的组合。在示例实施例中，所述多个半导体芯片31、32、33、34、35、36、37和38中的一些可具有不同尺寸。半导体芯片31、32、33、34、35、36、37和38可各自形成在来自晶圆的晶片上，并且可包括半导体衬底、形成在所述半导体衬底上的一个或多个集成电路、一个或多个导电层和一个或多个绝缘层。各个半导体芯片31、32、33、34、35、36、37和38包括电连接至半导体芯片外和半导体封装件内的其它组件的被描述为外部芯片端子的外部端子，并且各个半导体芯片31、32、33、34、35、36、37和38电连接至封装件衬底21的电路，并且可通过封装件衬底21的电路电连接至半导体封装件外部的装置。
例如，所述多个粘合剂41(例如，粘合剂层)可包括芯片贴附膜(DAF)。所述多个粘合剂41可对应地附着于所述多个半导体芯片31、32、33、34、35、36、37和38和应力均衡芯片139的下表面。所述多个粘合剂41可在第一半导体芯片31与衬底21之间、所述多个半导体芯片31、32、33、34、35、36、37和38之间以及第八半导体芯片38与应力均衡芯片139之间附着。所述多个粘合剂41各自可具有相同厚度(例如，在z方向上)，并且芯片31、32、33、34、35、36、37、38和139可竖直地彼此等距间隔开(例如，在z方向上)。按照这种方式，所述多个半导体芯片31、32、33、34、35、36、37和38的各个半导体芯片与邻近的半导体芯片分离开第一竖直距离，并且应力均衡芯片139可与最上面的半导体芯片38分离开相同的第一竖直距离。
所述至少一个芯片焊盘43可包括导电材料，诸如金属、金属氮化物、导电碳或者它们的组合。例如，所述至少一个芯片焊盘43可包括Cu、Co、Al、Sn、Ni、Au、Ag、W、WN、Ti、TiN、Ta、TaN、Ru、Pt或者它们的组合。所述至少一个芯片焊盘43可电连接至包括在所述多个半导体芯片31、32、33、34、35、36、37和38中的有源或无源元件。
所述多个互连部分45中的每一个可包括键合线、束引线(BL)、带式自动键合(TAB)或者它们的组合。例如，所述多个互连部分45中的每一个可包括Au、Al、Cu、Ag或者它们的组合。所述多个互连部分45可接触所述至少一个内部端子27和所述至少一个芯片焊盘43。本文所用的术语“接触”是指直接物理连接，例如，触摸。所述多个半导体芯片31、32、33、34、35、36、37和38可经由所述多个互连部分45电连接至衬底21。在示例实施例中，所述多个互连部分45不电连接至应力均衡芯片139。所述多个互连部分45可与应力均衡芯片139绝缘。在特定实施例中，应力均衡芯片139不电连接至衬底21或者所述多个半导体芯片31、32、33、34、35、36、37和38。应力均衡芯片139可与衬底21和所述多个半导体芯片31、32、33、34、35、36、37和38电绝缘，并因此在一些实施例中，不与半导体封装件中或半导体封装件外的其它组件通信。
密封剂56可包括环氧模塑化合物(EMC)。密封剂56可覆盖芯片堆叠件30的至少一部分。在示例实施例中，密封剂56可形成在衬底21上，以覆盖芯片堆叠件30、应力均衡芯片139和所述多个互连部分45的侧表面和上部。密封剂56的侧表面和衬底21的侧表面可基本共面，并且暴露于半导体封装件外。
如本文所用，当参照取向、布局、位置、形状、尺寸、量或其它量度时，诸如“相同”、“相等”、“平坦的”或“共面的”这些术语并不一定意指完全相同的取向、布局、位置、形状、尺寸、量或其它量度，而是旨在涵盖在可能例如由于制造工艺导致的可接受的变化范围内的近似相同的取向、布局、位置、形状、尺寸、量或其它量度。除非上下文或其它陈述另有说明，否则本文可使用术语“基本上”来强调这种含义。例如，描述为“基本上相同”、“基本上相等”或者“基本上平坦”的术语可为完全相同、相等或平坦，或者可为例如可能由于制造工艺导致的可接受的变化范围内的相同、相等或平坦。
在示例实施例中，所述多个半导体芯片31、32、33、34、35、36、37和38可为相同类型。所述多个半导体芯片31、32、33、34、35、36、37和38可包括相同类型的存储器。例如，所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可包括具有基本相同的大小和基本相同的存储容量的诸如闪速存储器等的非易失性存储器。所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可具有基本相同的大小。所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可具有基本相同的横向宽度、基本相同的横向长度和基本相同的厚度。所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可在基本相同的位置包括所述至少一个应力敏感区149。所述至少一个应力敏感区149可邻近于所述至少一个芯片焊盘43。
所述多个半导体芯片31、32、33、34、35、36、37和38可按次序偏移堆叠在衬底21上。第一半导体芯片31可布置在衬底21上。第二半导体芯片32可偏移排列在第一半导体芯片31上。例如，第二半导体芯片32可沿着第一半导体芯片31的长度在横向方向(例如，y方向)上以预定距离偏移排列在第一半导体芯片31上。从俯视图来看,第二半导体芯片32可与第一半导体芯片31中的所述至少一个应力敏感区149重叠。第二半导体芯片32可布置为完全覆盖第一半导体芯片31中的所述至少一个应力敏感区149。第三半导体芯片33至第八半导体芯片38可在与第二半导体芯片32相同的横向方向上各自沿着下半导体芯片的长度按次序偏移排列在第二半导体芯片32上。可将芯片堆叠件30描述为级联堆叠，或者具有楼梯结构。
第八半导体芯片38可偏移排列在第七半导体芯片37上。从俯视图来看，第八半导体芯片38可与第七半导体芯片37中的所述至少一个应力敏感区149重叠。如图1所示，在一个实施例中，芯片堆叠件30中的各个半导体芯片31至38可与紧接着其下方的半导体芯片的所述至少一个应力敏感区149重叠，并且可与所述至少一个应力敏感区149整体重叠。
应力均衡芯片139可布置在芯片堆叠件30上。应力均衡芯片139可与所述多个半导体芯片31、32、33、34、35、36、37和38在相同的横向方向上偏移排列在第八半导体芯片38上。所述多个半导体芯片31、32、33、34、35、36、37和38与应力均衡芯片139之间的偏移距离d1可基本相同。例如，应力均衡芯片139与第八半导体芯片38之间的偏移距离d1可与第八半导体芯片38与第七半导体芯片37之间的偏移距离d1基本相同。应力均衡芯片139可与第八半导体芯片38中的所述至少一个应力敏感区149重叠。所述多个半导体芯片31、32、33、34、35、36、37和38的水平宽度(例如，在x方向上)与应力均衡芯片139的水平宽度可基本相同。所述多个半导体芯片31、32、33、34、35、36、37和38的长度(例如，在y方向上)以及应力均衡芯片139的长度可基本相同。所述多个半导体芯片31、32、33、34、35、36、37和38的厚度或高度(例如，在z方向上)以及应力均衡芯片139可基本相同。应力均衡芯片139可为与所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个具有基本相同的大小(例如，长度和宽度)的虚设芯片。应力均衡芯片139可与所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个具有基本相同的厚度。
所述多个半导体芯片31、32、33、34、35、36、37和38的电特性可通过由于诸如压阻效应等的各种机制施加至所述多个半导体芯片31、32、33、34、35、36、37和38的应力而改变。当施加至所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的应力的变化大时，所述多个对应的半导体芯片31、32、33、34、35、36、37和38可具有不同的电特性。当所述多个半导体芯片31、32、33、34、35、36、37和38的电特性之间的变化大时，难以设计和操作用于芯片堆叠件30的校正电路。
压阻效应可包括由于施加至晶体管的沟道区的应力导致硅原子之间的间隔变化和电子迁移率变化的现象。在示例实施例中，所述至少一个应力敏感区149可包括对于压阻效应敏感的部分。当所述多个半导体芯片31、32、33、34、35、36、37和38是相同类型时，可在所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的基本相同的位置产生所述至少一个应力敏感区149。
应力均衡芯片139可用于减小施加至所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的应力的变化。应力均衡芯片139可用于相似地控制在所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个中出现的应力奇点的位置和大小。应力均衡芯片139可用于使施加至第八半导体芯片38的应力均衡，以与施加至第一半导体芯片31至第七半导体芯片37中的每一个的应力相似。例如，应力均衡芯片139可根据其组成、大小和位置用作以及被构造为减小所述多个半导体芯片31、32、33、34、35、36、37和38之间的电特性的变化。所述多个半导体芯片31、32、33、34、35、36、37和38之间的电特性的变化的减小可有利于用于芯片堆叠件30的校正电路的设计和操作。
第一半导体芯片31可对应于布置在芯片堆叠件30的最下层上的最下面的半导体芯片，并且第八半导体芯片38可对应于布置在芯片堆叠件30的最上层上的最上面的半导体芯片。在示例实施例中，第七半导体芯片37可对应于下半导体芯片，并且第八半导体芯片38可对应于布置在下半导体芯片上的上半导体芯片。在示例实施例中，第六半导体芯片36可对应于下半导体芯片，第七半导体芯片37可对应于布置在下半导体芯片上的中间半导体芯片，并且第八半导体芯片38可对应于布置在中间半导体芯片上的最上面的半导体芯片。
在示例实施例中，应力均衡芯片139可包括半导体衬底、金属板、金属氮化物板、金属氧化物板、绝缘衬底或它们的组合或者它们中的一个或多个。应力均衡芯片139可包括半导体衬底、一个或多个金属层以及一个或多个绝缘层。可将衬底和/或这些层中的一个或多个图案化。
在示例实施例中，应力均衡芯片139是例如不电连接至衬底21(例如，衬底21的电路)或半导体封装件的任何其它芯片的虚设芯片。应力均衡芯片可具有或不具有形成在其上的电路(例如，内部布线或集成电路)。
在一些实施例中，为了确保芯片堆叠件30中的各个后续较高的半导体芯片覆盖下半导体芯片的应力敏感区149，在各个半导体芯片堆叠在下方芯片上之前，测试下半导体芯片以确定应力敏感区149。然后，基于测试结果，下一个半导体芯片布置为覆盖下方芯片的应力敏感区149。对于第八半导体芯片38，可执行相同的测试以确定第八半导体芯片38的应力敏感区149，并随后可将应力均衡芯片布置为覆盖所确定的应力敏感区149。
在本发明构思的示例性实施例中，应力状况可有效地提高载流子迁移率。PMOS晶体管中的压应变明显提高空穴迁移率。NMOS晶体管中的拉应变明显提高电子迁移率。可通过设计的位置和诸如PMOS晶体管等的子装置的密度来确定应力敏感区149的位置。
参照图2，应力均衡芯片139的横向宽度(例如，在y方向上的长度)可小于多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度。应力均衡芯片139的一个侧表面可与第八半导体芯片38的一个侧表面基本共面(例如，沿着x/z方向)。
参照图3，应力均衡芯片139的横向宽度(例如，在y方向上的长度)可与多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度不同。应力均衡芯片139的横向宽度可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度。应力均衡芯片139可与第八半导体芯片38中的至少一个应力敏感区149重叠。
在一个实施例中，多个互连部分45可布置在应力均衡芯片139、所述多个半导体芯片31、32、33、34、35、36、37和38与衬底21之间。所述多个互连部分45可接触应力均衡芯片139中的至少一个芯片焊盘43。应力均衡芯片139可经由所述多个互连部分45电连接至所述多个半导体芯片31、32、33、34、35、36、37和38以及衬底21。应力均衡芯片139可包括与所述多个半导体芯片31、32、33、34、35、36、37和38不同类型的芯片。例如，所述多个半导体芯片31、32、33、34、35、36、37和38可包括诸如闪速存储器或磁阻随机存取存储器(MRAM)等的非易失性存储器、或者诸如动态随机存取存储器(DRAM)等的易失性存储器。应力均衡芯片139可包括诸如控制器、微处理器或应用处理器等的逻辑芯片。
图4和图5是用于描述根据示例实施例的半导体封装件的俯视图。
参照图4，根据本发明构思的示例实施例的半导体封装件可包括衬底21、芯片堆叠件30、多个互连部分45和应力均衡芯片139。衬底21可包括多个内部端子27。芯片堆叠件30可包括多个半导体芯片31、32、33、34、35、36、37和38。所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可包括至少一个应力敏感区149和多个芯片焊盘43。应力均衡芯片139可包括多个芯片焊盘43。
第一半导体芯片31可布置在衬底21上。第二半导体芯片32可偏移排列在第一半导体芯片31上。与第二半导体芯片32相似，第三半导体芯片33至第八半导体芯片38可按次序偏移排列在第二半导体芯片32上。应力均衡芯片139可在与所述多个半导体芯片31、32、33、34、35、36、37和38相同的方向上偏移排列在第八半导体芯片38上。
应力均衡芯片139的大小可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的大小。应力均衡芯片139的横向宽度(例如，在y方向上的长度)可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度。应力均衡芯片139的水平宽度(例如，在x方向上)可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的水平宽度。应力均衡芯片139可与第八半导体芯片38中的所述至少一个应力敏感区149重叠。
所述多个互连部分45可接触所述多个内部端子27和所述多个芯片焊盘43。所述多个半导体芯片31、32、33、34、35、36、37和38以及应力均衡芯片139可经由所述多个互连部分45电连接至衬底21。应力均衡芯片139可经由所述多个互连部分45电连接至所述多个半导体芯片31、32、33、34、35、36、37和38以及衬底21。
参照图5，根据本发明构思的示例实施例的半导体封装件可包括衬底21、芯片堆叠件30、多个互连部分45、第九半导体芯片139A和应力均衡芯片139。第九半导体芯片139A可包括多个芯片焊盘43。
第九半导体芯片139A可与所述多个半导体芯片31、32、33、34、35、36、37和38在相同方向上偏移排列在第八半导体芯片38上。第九半导体芯片139A的大小可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的大小。第九半导体芯片139A的横向宽度可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度。第九半导体芯片139A的水平宽度可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的水平宽度。所述多个互连部分45可接触多个内部端子27和所述多个芯片焊盘43。第九半导体芯片139A可经由所述多个互连部分45电连接至所述多个半导体芯片31、32、33、34、35、36、37和38和衬底21。第九半导体芯片139A可替代地布置在第八半导体芯片38中的至少一个应力敏感区149上。
第九半导体芯片139A可包括与所述多个半导体芯片31、32、33、34、35、36、37和38不同类型的芯片。例如，所述多个半导体芯片31、32、33、34、35、36、37和38可包括诸如闪速存储器或MRAM等的非易失性存储器或者诸如DRAM等的易失性存储器。第九半导体芯片139A可包括诸如控制器、微处理器或应用处理器等的逻辑芯片。
应力均衡芯片139可在与所述多个半导体芯片31、32、33、34、35、36、37和38相同的方向上偏移排列在第八半导体芯片38上。应力均衡芯片139可布置为邻近于第九半导体芯片139A(例如，在x方向上)。应力均衡芯片139的大小可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的大小。应力均衡芯片139的横向宽度可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度。应力均衡芯片139的水平宽度可小于所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的水平宽度。应力均衡芯片139可与第八半导体芯片38中的所述至少一个应力敏感区149重叠。所述多个互连部分45不电连接至应力均衡芯片139。应力均衡芯片139可为大小与所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个的大小不同的虚设芯片，并且可与所述多个半导体芯片31、32、33、34、35、36、37和38或衬底21电绝缘(并因此不与其电连接)。
图6至图17是用于描述根据示例实施例的半导体封装件的剖视图。
参照图6，应力均衡芯片139的上表面可暴露于半导体封装件的外部。密封剂56的上表面和应力均衡芯片139的上表面基本共面。应力均衡芯片139可为与多个半导体芯片31、32、33、34、35、36、37和38中的每一个具有基本相同的大小的虚设芯片。
参照图7，应力均衡芯片139的上表面可暴露于半导体封装件外部。密封剂56的上表面和应力均衡芯片139的上表面基本共面。应力均衡芯片139可为横向宽度大于多个半导体芯片31、32、33、34、35、36、37和38中的每一个的横向宽度的虚设芯片。在示例实施例中，应力均衡芯片139的至少一个侧表面和密封剂56的至少一个侧表面基本共面。
参照图8，根据本发明构思的示例实施例的半导体封装件可包括衬底21、多个突出电极23、芯片堆叠件30、多个粘合剂41、多个互连部分45和46、密封剂56和应力均衡芯片139。衬底21可包括多个外部端子24、内部互连部分25和多个内部端子27和28。
第一半导体芯片31可布置在衬底21上。第二半导体芯片32可偏移排列在第一半导体芯片31上。例如，第二半导体芯片32可在第一横向方向上以预定距离偏移排列在第一半导体芯片31上。第二半导体芯片32可与第一半导体芯片31中的至少一个应力敏感区149重叠。与第二半导体芯片32相似，第三半导体芯片33和第四半导体芯片34可按次序偏移排列在第二半导体芯片32上。第一半导体芯片31至第四半导体芯片34中的每一个的至少一个芯片焊盘43可接触第一互连部分45。第一互连部分45的一端可接触第一内部端子27。
第五半导体芯片35可偏移排列在第四半导体芯片34上。例如，第五半导体芯片35可在第一横向方向上以预定距离偏移排列在第四半导体芯片34上。第五半导体芯片35可与第四半导体芯片34中的至少一个应力敏感区149重叠。第五半导体芯片35中的至少一个芯片焊盘43可布置在相对远离第一互连部分45的位置。
第六半导体芯片36可偏移排列在第五半导体芯片35上。例如，第六半导体芯片36可在与第一横向方向不同的第二横向方向上以预定距离偏移排列在第五半导体芯片35上。第二横向方向可与第一横向方向反向。第六半导体芯片36可与第五半导体芯片35中的所述至少一个应力敏感区149重叠。与第六半导体芯片36相似，第七半导体芯片37和第八半导体芯片38可按次序偏移排列在第六半导体芯片36上。第五半导体芯片35至第八半导体芯片38中的每一个的所述至少一个芯片焊盘43可接触第二互连部分46。第二互连部分46的一端可接触第二内部端子28。
应力均衡芯片139可在与第六半导体芯片36至第八半导体芯片38相同的方向上偏移排列在第八半导体芯片38上。应力均衡芯片139可与第八半导体芯片38中的所述至少一个应力敏感区149重叠。
参照图9，第二半导体芯片32可偏移排列在第一半导体芯片31上。例如，第二半导体芯片32可在第一横向方向上以预定距离偏移排列在第一半导体芯片31上。第一半导体芯片31中的至少一个芯片焊盘43可布置为相对靠近第一内部端子27。第二半导体芯片32中的至少一个芯片焊盘43可布置为相对靠近第二内部端子28。
第三半导体芯片33可偏移排列在第二半导体芯片32上。例如，第三半导体芯片33可在与第一横向方向不同的第二横向方向上以预定距离偏移排列在第二半导体芯片32上。第三半导体芯片33中的至少一个芯片焊盘43可布置为相对靠近第一内部端子27。
第四半导体芯片34可偏移排列在第三半导体芯片33上。例如，第四半导体芯片34可在第一横向方向上以预定距离偏移排列在第三半导体芯片33上。第四半导体芯片34中的至少一个芯片焊盘43可布置为相对靠近第二内部端子28。
第五半导体芯片35可偏移排列在第四半导体芯片34上。例如，第五半导体芯片35可在第二横向方向上以预定距离偏移排列在第四半导体芯片34上。第五半导体芯片35中的至少一个芯片焊盘43可布置为相对靠近第一内部端子27。
第六半导体芯片36可偏移排列在第五半导体芯片35上。例如，第六半导体芯片36可在第一横向方向上以预定距离偏移排列在第五半导体芯片35上。第六半导体芯片36中的至少一个芯片焊盘43可布置为相对靠近第二内部端子28。
第七半导体芯片37可偏移排列在第六半导体芯片36上。例如，第七半导体芯片37可在第二横向方向上以预定距离偏移排列在第六半导体芯片36上。第七半导体芯片37中的至少一个芯片焊盘43可布置为相对靠近第一内部端子27。
第八半导体芯片38可偏移排列在第七半导体芯片37上。例如，第八半导体芯片38可在第一横向方向上以预定距离偏移排列在第七半导体芯片37上。第八半导体芯片38中的至少一个芯片焊盘43可布置为相对靠近第二内部端子28。
第一半导体芯片31、第三半导体芯片33、第五半导体芯片35和第七半导体芯片37可竖直对齐。第一半导体芯片31的侧表面、第三半导体芯片33的侧表面、第五半导体芯片35的侧表面和第七半导体芯片37的侧表面可基本共面。第一互连部分45可接触第一半导体芯片31、第三半导体芯片33、第五半导体芯片35和第七半导体芯片37中的每一个的所述至少一个芯片焊盘43。第一半导体芯片31、第三半导体芯片33、第五半导体芯片35和第七半导体芯片37可经由第一互连部分45电连接至衬底21中的第一内部端子27。
第二半导体芯片32、第四半导体芯片34、第六半导体芯片36和第八半导体芯片38可竖直对齐。第二半导体芯片32的侧表面、第四半导体芯片34的侧表面、第六半导体芯片36的侧表面和第八半导体芯片38的侧表面可基本共面。第二互连部分46可接触第二半导体芯片32、第四半导体芯片34、第六半导体芯片36和第八半导体芯片38中的每一个的所述至少一个芯片焊盘43。第二半导体芯片32、第四半导体芯片34、第六半导体芯片36和第八半导体芯片38可经由第二互连部分46电连接至衬底21中的第二内部端子28。可将芯片堆叠件30理解为z字形堆叠件。
应力均衡芯片139可在第二横向方向上偏移排列在第八半导体芯片38上。应力均衡芯片139可与第八半导体芯片38中的所述至少一个应力敏感区149重叠。应力均衡芯片139可与第一半导体芯片31、第三半导体芯片33、第五半导体芯片35和第七半导体芯片37竖直地对齐。应力均衡芯片139的侧表面、第一半导体芯片31的侧表面、第三半导体芯片33的侧表面、第五半导体芯片35的侧表面和第七半导体芯片37的侧表面可基本共面。各个粘合剂41可具有相同厚度(例如，在竖直方向上)。
参照图10，第一半导体芯片31至第八半导体芯片38可按次序地且竖直地堆叠在衬底21上。多个粘合剂41可附着在衬底21与第一半导体芯片31之间以及第一半导体芯片31至第八半导体芯片38之间。第一半导体芯片31至第八半导体芯片38的侧表面可基本共面。多个互连部分45和46可穿过所述多个粘合剂41以接触第一半导体芯片31至第八半导体芯片38中的每一个的至少一个芯片焊盘43。
应力均衡芯片139可布置在第八半导体芯片38上。应力均衡芯片139可与第八半导体芯片38中的至少一个应力敏感区149重叠。在示例实施例中，应力均衡芯片139可与第一半导体芯片31至第八半导体芯片38竖直地对齐。应力均衡芯片139的侧表面和第一半导体芯片31至第八半导体芯片38的侧表面可基本共面。密封剂56可形成为覆盖芯片堆叠件30、应力均衡芯片139和所述多个互连部分45和46的侧表面和上部。
参照图11，应力均衡芯片139的横向宽度可小于第八半导体芯片38的横向宽度。应力均衡芯片139可与第八半导体芯片38中的至少一个应力敏感区149重叠。
参照图12，应力均衡芯片139的上表面可暴露于半导体封装件之外。应力均衡芯片139的上表面和密封剂56的上表面可基本共面。
参照图13，应力均衡芯片139的横向宽度可大于第八半导体芯片38的横向宽度。应力均衡芯片139的上表面和侧表面可暴露于半导体封装件之外。应力均衡芯片139的侧表面和密封剂56的侧表面可基本共面。
参照图14，根据本发明构思的示例实施例的半导体封装件可包括衬底21、多个突出电极23、芯片堆叠件30、多个粘合剂41、多个互连部分47和48、密封剂56和应力均衡芯片139。衬底21可包括多个外部端子24、内部互连部分25和多个内部端子29。所述多个互连部分47和48可包括多个导电凸块47和多个硅通孔(TSV)48。芯片堆叠件30可包括多个半导体芯片31、32、33、34、35、36、37和38。所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个可包括至少一个应力敏感区149。
第一半导体芯片31至第八半导体芯片38可按次序地且竖直地堆叠在衬底21上。第一半导体芯片31至第八半导体芯片38的侧表面可基本共面。所述多个粘合剂41可附着在衬底21与第一半导体芯片31之间、第一半导体芯片31至第八半导体芯片38之间以及第八半导体芯片38与应力均衡芯片139之间。所述多个粘合剂41可包括诸如非导电树脂的底填充物。所述多个TSV 48中的每一个可穿过所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个。所述多个导电凸块47可布置在衬底21与第一半导体芯片31之间、第一半导体芯片31至第八半导体芯片38之间以及第八半导体芯片38与应力均衡芯片139之间。所述多个导电凸块47可穿过所述多个粘合剂41，以接触所述多个内部端子29和所述多个TSV 48。所述多个半导体芯片31、32、33、34、35、36、37和38可经由所述多个互连部分47和48电连接至衬底21。
应力均衡芯片139可布置在第八半导体芯片38上。应力均衡芯片139可与第八半导体芯片38中的所述至少一个应力敏感区149重叠。在示例实施例中，应力均衡芯片139可与第一半导体芯片31至第八半导体芯片38竖直地对齐。应力均衡芯片139可具有与所述多个半导体芯片31、32、33、34、35、36、37和38中的每一个基本相同的横向宽度。应力均衡芯片139的侧表面和第一半导体芯片31至第八半导体芯片38的侧表面可基本共面。密封剂56可形成为覆盖芯片堆叠件30和应力均衡芯片139的侧表面和上部。
参照图15，应力均衡芯片139的上表面可暴露于半导体封装件外部。应力均衡芯片139的上表面和密封剂56的上表面可基本共面。
参照图16，应力均衡芯片139的横向宽度可大于第八半导体芯片38的横向宽度。应力均衡芯片139的上表面和侧表面可暴露于半导体封装件之外。应力均衡芯片139的侧表面和密封剂56的侧表面可基本共面。
参照图17，应力均衡芯片139的横向宽度可小于第八半导体芯片38的横向宽度。应力均衡芯片139可与第八半导体芯片38中的至少一个应力敏感区149重叠。
根据本发明构思的示例实施例，应力均衡芯片布置在具有多个半导体芯片的芯片堆叠件上。所述多个半导体芯片的最上面的半导体芯片可包括至少一个应力敏感区。应力均衡芯片可与所述至少一个应力敏感区重叠。应力均衡芯片可用于减小施加至所述多个半导体芯片中的每一个的应力的变化。由于应力均衡芯片的角色，所述多个半导体芯片的电特性分布可明显减小。因此，可实现具有高电特性的半导体封装件。
虽然已经参照附图描述了本发明构思的实施例，但是本领域技术人员应该理解，在不脱离本发明构思的范围并且不改变其基本特征的情况下，可做出各种修改。因此，应当仅按照描述性含义而不是出于限制的目的来看待上述实施例。

Claims (20)

1.一种半导体封装件，包括：
芯片堆叠件，其具有竖直地堆叠在封装件衬底上的多个半导体芯片；
应力均衡芯片，其布置在所述芯片堆叠件上，所述应力均衡芯片构造为减小所述多个半导体芯片之间的电特性的变化；以及
密封剂，其布置在所述封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分，
其中，所述多个半导体芯片中的每一个电连接至所述封装件衬底，并且所述应力均衡芯片不电连接至所述封装件衬底或所述多个半导体芯片。
2.根据权利要求1所述的半导体封装件，其中：
所述多个半导体芯片中的每一个包括至少一个应力敏感区；并且
所述多个半导体芯片包括下半导体芯片和布置在所述下半导体芯片上的上半导体芯片，
其中，所述上半导体芯片与所述下半导体芯片的所述至少一个应力敏感区重叠。
3.根据权利要求2所述的半导体封装件，其中：
所述多个半导体芯片包括布置在所述芯片堆叠件的最上层处的最上面的半导体芯片；并且
所述应力均衡芯片与所述最上面的半导体芯片的所述至少一个应力敏感区重叠。
4.根据权利要求1所述的半导体封装件，其中，所述应力均衡芯片和所述多个半导体芯片中的每一个在第一方向上具有相同宽度。
5.根据权利要求1所述的半导体封装件，其中，所述多个半导体芯片包括：
下半导体芯片，其布置在所述封装件衬底上；
中间半导体芯片，其沿着所述下半导体芯片的长度偏移地排列在所述下半导体芯片上；以及
最上面的半导体芯片，其沿着所述中间半导体芯片的长度偏移地排列在所述中间半导体芯片上，
其中，所述应力均衡芯片沿着所述最上面的半导体芯片的长度偏移地排列在所述最上面的半导体芯片上。
6.根据权利要求5所述的半导体封装件，其中：
所述最上面的半导体芯片按照与所述中间半导体芯片相对于所述下半导体芯片偏移地排列的方向相同的方向偏移地排列；并且
所述应力均衡芯片按照与所述最上面的半导体芯片相对于所述中间半导体芯片偏移地排列的方向相同的方向偏移地排列。
7.根据权利要求5所述的半导体封装件，其中：
所述最上面的半导体芯片相对于所述中间半导体芯片按照与所述中间半导体芯片相对于所述下半导体芯片偏移地排列的方向不同的方向偏移地排列；并且
所述应力均衡芯片相对于所述最上面的半导体芯片按照与所述最上面的半导体芯片相对于所述中间半导体芯片偏移地排列的方向不同的方向偏移地排列。
8.根据权利要求5所述的半导体封装件，其中，所述应力均衡芯片与所述最上面的半导体芯片之间的偏移距离和所述最上面的半导体芯片与所述中间半导体芯片之间的偏移距离相同。
9.根据权利要求5所述的半导体封装件，其中，所述应力均衡芯片在第一方向上的宽度小于所述下半导体芯片、所述中间半导体芯片和所述最上面的半导体芯片中的每一个在所述第一方向上的宽度。
10.根据权利要求1所述的半导体封装件，其中，第一粘合剂形成在所述应力均衡芯片之下，并且第二粘合剂形成在所述多个半导体芯片中的每一个之下，并且其中，所述第一粘合剂与所述第二粘合剂具有相同厚度。
11.根据权利要求1所述的半导体封装件，其中，所述密封剂覆盖所述应力均衡芯片的上表面和侧表面。
12.根据权利要求1所述的半导体封装件，其中，所述密封剂的上表面和所述应力均衡芯片的上表面共面，并且所述应力均衡芯片暴露于所述半导体封装件之外。
13.根据权利要求1所述的半导体封装件，其中，所述多个半导体芯片和所述应力均衡芯片按照楼梯结构排列。
14.根据权利要求13所述的半导体封装件，其中：
所述应力均衡芯片是不与所述多个半导体芯片或所述封装件衬底通信的虚设芯片，并且
所述应力均衡芯片与所述多个半导体芯片中的每个半导体芯片具有相同的宽度和长度。
15.一种半导体封装件，包括：
芯片堆叠件，其具有封装件衬底上的多个半导体芯片；
应力均衡芯片，其布置在所述芯片堆叠件上，所述应力均衡芯片为虚设芯片；以及
密封剂，其布置在所述封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分，
其中，所述多个半导体芯片包括布置在所述芯片堆叠件的最上层处的最上面的半导体芯片和所述最上面的半导体芯片下方的多个下半导体芯片，
其中，所述多个半导体芯片中的每个半导体芯片与邻近的半导体芯片分隔开第一竖直距离，并且
其中，所述应力均衡芯片与所述最上面的半导体芯片分隔开所述第一竖直距离。
16.根据权利要求15所述的半导体封装件，其中：
所述多个半导体芯片中的每一个具有相同的横向宽度和水平宽度；并且
所述应力均衡芯片与所述多个半导体芯片中的每一个具有相同的横向宽度和水平宽度。
17.根据权利要求15所述的半导体封装件，其中，所述应力均衡芯片不电连接至所述封装件衬底。
18.根据权利要求17所述的半导体封装件，其中，所述多个半导体芯片和所述应力均衡芯片按照楼梯结构排列。
19.一种半导体封装件，包括：
芯片堆叠件，其具有在封装件衬底上偏移地堆叠的多个半导体芯片；
虚设芯片，其堆叠在所述芯片堆叠件上，并且相对于所述多个半导体芯片中的最上面的半导体芯片偏移布置，并且与所述多个半导体芯片中的每一个具有相同的宽度和长度；以及
密封剂，其布置在所述封装件衬底上，并且被构造为覆盖所述芯片堆叠件的至少一部分，
其中，所述多个半导体芯片中的每一个包括非易失性存储器，并且
其中，所述虚设芯片包括半导体衬底、一个或多个金属层以及一个或多个绝缘层，构造为减小所述多个半导体芯片之间的电特性变化，并且所述虚设芯片不电连接至所述封装件衬底的电路。
20.根据权利要求19所述的半导体封装件，其中，所述多个半导体芯片和所述虚设芯片按照楼梯结构排列。
CN201910119871.8A 2018-07-13 2019-02-18 包括应力均衡芯片的半导体封装件 Pending CN110718541A (zh)

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