CN105321902B - 封装结构及其制法 - Google Patents
封装结构及其制法 Download PDFInfo
- Publication number
- CN105321902B CN105321902B CN201410362830.9A CN201410362830A CN105321902B CN 105321902 B CN105321902 B CN 105321902B CN 201410362830 A CN201410362830 A CN 201410362830A CN 105321902 B CN105321902 B CN 105321902B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- encapsulating structure
- opening
- conductive
- preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 claims abstract description 7
- 238000002360 preparation method Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 11
- 238000003384 imaging method Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 62
- 238000005538 encapsulation Methods 0.000 description 11
- 239000010949 copper Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1076—Shape of the containers
- H01L2225/1088—Arrangements to limit the height of the assembly
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种封装结构及其制法,该制法,先提供一具有多个焊垫的承载件,再压合一介电层于该承载件上,之后形成多个导电柱于该介电层中,最后移除该介电层的部分材质以形成一开口,使该些焊垫外露于该开口,且该些导电柱位于该开口周围,藉以达到简化制程的目的。本发明还提供该封装结构。
Description
技术领域
本发明有关一种封装结构,尤指一种能简化制程的封装结构及其制法。
背景技术
随着半导体封装技术的演进,半导体装置(Semiconductor device)已开发出不同的封装型态,而为提升电性功能及节省封装空间,遂堆加多个封装件以形成封装堆迭结构(Package on Package,POP),此种封装方式能发挥系统封装(SiP)异质整合特性,可将不同功用的电子元件,例如:记忆体、中央处理器、绘图处理器、影像应用处理器等,藉由堆迭设计达到系统的整合,适合应用于轻薄型各种电子产品。
一般封装堆迭结构(PoP)仅以焊锡球(solder ball)堆迭与电性连接上、下封装件,但随着产品尺寸规格与线距越来越小,该些焊锡球之间容易发生桥接(bridge)现象,将影响产品的良率。
于是,遂发展出一种封装堆迭结构,其以铜柱(Cu pillar)作支撑,以增加隔离(stand off)效果,可避免发生桥接现象。图1A及图1B为现有封装堆迭结构1的制法的剖面示意图。
如图1A所示,先提供一具有相对的第一及第二表面11a,11b的第一基板11,且于该第一基板11的第一表面11a上形成多个铜柱13。
如图1B所示,设置一电子元件15于该第一表面11a上且以覆晶方式电性连接该第一基板11,再迭设一第二基板12于该铜柱13上,之后形成封装胶体16于该第一基板11的第一表面11a与该第二基板12之间。具体地,该第二基板12藉由多个导电元件17结合该铜柱13,且该导电元件17由金属柱170与焊锡材料171构成。
然而,现有封装堆迭结构1中,该铜柱13以电镀形成,致使其尺寸变异不易控制,故容易发生各铜柱13的高度不一致的情况,因而产生接点偏移的问题,致使该些导电元件17与该些铜柱13接触不良,而造成电性不佳,因而影响产品良率。
因此,如何克服上述现有技术的问题,实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失,本发明提供一种封装结构及其制法,以达到简化制程的目的。本发明还提供该封装结构。
本发明的封装结构,包括:承载件,其具有多个焊垫;介电层,其具有相对的第一表面与第二表面,该介电层以其第一表面设于该承载件上,以令该介电层覆盖该些焊垫,且该介电层的第二表面上具有至少一开口,使该些焊垫外露于该开口;以及多个导电柱,其形成于该介电层中,且该些导电柱位于该开口周围。
本发明还提供一种封装结构的制法,包括:提供一具有多个焊垫的承载件、及一具有相对的第一表面与第二表面的介电层;将该介电层藉其第一表面压合于该承载件上,以令该介电层覆盖该些焊垫;形成多个导电柱于该介电层中;以及于该介电层的第二表面形成至少一开口,使该些焊垫外露于该开口,且该些导电柱位于该开口周围。
前述的制法中,于压合该介电层与该承载件之前,该介电层的第二表面上具有导电层,以利用该导电层制作该导电柱。
前述的制法中,该导电柱的步骤先形成贯穿该介电层的多个穿孔,再于该些穿孔中填充导电材料以作为该导电柱。
前述的制法中,还包括设置堆迭件至该介电层的第二表面上,且该堆迭件电性连接该导电柱。例如,该堆迭件为封装基板、半导体晶片、中介板或封装件。
前述的封装结构及其制法中,该承载件为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。
前述的封装结构及其制法中,该介电层的第二表面上还具有电性连接该导电柱的线路层。
前述的封装结构及其制法中,该介电层为感光介质。例如,形成该开口的制程为使用曝光显影制程。
另外,前述的封装结构及其制法中,还包括设置电子元件于该开口中,且该电子元件电性连接该些焊垫。
由上可知,本发明的封装结构及其制法,主要藉由在该承载件上压合介电层以制作导电柱,而能增加隔离效果及避免桥接现象。
此外,藉由该些穿孔控制各该导电柱的尺寸,使各该导电柱的高度一致,以避免接点偏移的问题,故相较于现有技术,后续制程的导电元件与该些导电柱不会发生接触不良或短路的问题,因而能有效提高产品良率。
附图说明
图1A至图1B为现有堆迭式封装结构的制法的剖视示意图;以及
图2A至图2G为本发明的堆迭式封装结构的制法的剖视示意图。
符号说明
1 封装堆迭结构
11 第一基板
11a,22a 第一表面
11b,22b 第二表面
12 第二基板
13 铜柱
15,28 电子元件
16 封装胶体
17,291 导电元件
170 金属柱
171 焊锡材料
2,3 封装结构
21 承载件
210 焊垫
211 电性连接垫
211’ 线路部
212 导电盲孔
213 介电部
214 金属层
22 介电层
220 开口
23 导电层
25,25’ 线路层
26 导电柱
260 穿孔
27 绝缘保护层
281 导电凸块
29 堆迭件
30 封装材
A 承载区。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用于配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用于限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”、及“一”等用语,也仅为便于叙述的明了,而非用于限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2G为本发明的封装结构2,3的制法的剖视示意图。
如图2A所示,提供一具有多个焊垫210与多个电性连接垫211的承载件21。
于本实施例中,该承载件21为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。例如,图2A所示,该承载件21为无核心层(coreless)封装基板,其由多个介电部213、线路部211’与导电盲孔212构成,且于该承载件21下侧具有如铜的金属层214。
此外,该承载件21定义有一承载区A,使该些焊垫210位于该承载区A内,而该电性连接垫211位于该承载区A外。
如图2B所示,压合一具有导电层23的介电层22于该承载件21上,再以激光钻孔方式于对应该电性连接垫211的位置上形成贯穿该介电层22与该导电层23的多个穿孔260。
于本实施例中,该介电层22具有相对的第一表面22a与第二表面22b,且该介电层22以其第一表面22a压合于该承载件21上,以令该介电层22覆盖该些焊垫210,且该导电层23设于该介电层22的第二表面22b上。
此外,该介电层22的材质为感光介质(photo imageable dielectric,简称PID),且该导电层23为铜层。
又,藉由将该介电层22与该承载件21以热压合直接压合,使制程简化。
如图2C所示,利用该导电层23,于该介电层22的第二表面22b上制作一线路层25,且于该些穿孔260中形成导电材料以作为导电柱26,且藉由该些导电柱26电性连接该线路层25与该些电性连接垫211。
于本实施例中,该线路层25并未形成于对应该承载区A的第二表面22b上。
此外,利用该承载件21下侧的金属层214制作另一线路层25’。
如图2D所示,使用曝光显影制程,形成一开口220于该介电层22的第二表面22b上,使该些焊垫210外露于该开口220,且该些导电柱26位于该开口220周围。
于本实施例中,该承载件21于该承载区A的表面亦外露于该开口220。
如图2E所示,可于该介电层22的第二表面22b、该承载件21下侧与该线路层25,25’上分别形成一绝缘保护层27,且该些绝缘保护层27外露出部分该线路层25,25’,供后续制程中接置其它外部元件。
如图2F所示,于该开口220内设置至少一电子元件28,且该电子元件28以多个导电凸块281电性连接该些焊垫210。
如图2G所示,设置一堆迭件29于该线路层25上,以令该堆迭件29迭设于该介电层22的第二表面22b上,且覆盖该开口220与该电子元件28,以制得本发明的封装结构3的另一实施例。
于本实施例中,该堆迭件29为封装基板、半导体晶片、晶圆、中介板或封装件,且该堆迭件29藉由多个如焊锡材料或金属柱的导电元件291电性结合至该线路层25与该导电柱26。
此外,形成封装材30于该堆迭件29与承载件21之间,以包覆该些导电凸块281。
本发明还提供一种封装结构2,包括:一承载件21、一介电层22以及多个导电柱26。
所述的承载件21为封装基板,其具有多个焊垫210。
所述的介电层22为感光介质,其具有相对的第一表面22a与第二表面22b,该介电层22以其第一表面22a设于该承载件21上,以令该介电层22覆盖该些焊垫210,且该介电层22的第二表面22b上具有开口220,使该些焊垫210外露于该开口220,又该介电层22的第二表面22b上还具有电性连接该导电柱26的线路层25。
所述的导电柱26设于该介电层22中,且该些导电柱26位于该开口220周围。
于一实施例中,所述的封装结构2还包括电子元件28,其设于该开口220中,且该电子元件28电性连接该些焊垫210。
综上所述,本发明封装结构2及其制法中,藉由在承载件21上形成一介电层22,使该导电柱26嵌入该介电层22中,再于该介电层22上接置该堆迭件29,藉以增加隔离(standoff)各该导电柱26的效果、及避免各该导电柱26之间发生桥接现象。
此外,藉由该些穿孔260控制各该导电柱26的尺寸,使各该导电柱26的高度一致,以令该些导电元件291的接置处高度一致,因而能避免接点偏移的问题,故该些导电元件291与该些导电柱26不会发生接触不良或短路(short)的问题,因而能有效提高产品良率。
又,藉由该介电层22具有感光性,故能使用曝光显影制程形成该开口220,以简化制程。
上述实施例仅用于例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (13)
1.一种封装结构,包括:
承载件,其具有多个焊垫;
介电层,其具有相对的第一表面与第二表面,该介电层以其第一表面设于该承载件上,以令该介电层覆盖所述焊垫,且该介电层的第二表面上具有至少一开口,使所述焊垫外露于该开口;
电子元件,其设于该开口中,且该电子元件电性连接所述焊垫;以及
多个导电柱,其形成于该介电层中,且所述导电柱位于该开口周围。
2.如权利要求1所述的封装结构,其特征为,该承载件为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。
3.如权利要求1所述的封装结构,其特征为,该介电层的第二表面上还具有电性连接该导电柱的线路层。
4.如权利要求1所述的封装结构,其特征为,该介电层为感光介质。
5.一种封装结构的制法,其包括:
提供一具有多个焊垫的承载件、及一具有相对的第一表面与第二表面的介电层,该承载件由介电部、线路部与导电盲孔构成;
将该介电层通过其第一表面压合于该承载件上,以令该介电层覆盖所述焊垫;
形成多个导电柱于该介电层中;
于该介电层的第二表面形成至少一开口,使所述焊垫外露于该开口,且所述导电柱位于该开口周围;以及
设置电子元件于该开口中,且该电子元件电性连接所述焊垫。
6.如权利要求5所述的封装结构的制法,其特征为,该承载件为封装基板、半导体晶片、晶圆、中介板、经封装或未经封装的半导体元件。
7.如权利要求5所述的封装结构的制法,其特征为,于压合该介电层与该承载件之前,该介电层的第二表面上具有导电层,以利用该导电层制作该导电柱。
8.如权利要求5所述的封装结构的制法,其特征为,该导电柱的步骤先形成贯穿该介电层的多个穿孔,再于所述穿孔中填充导电材料以作为该导电柱。
9.如权利要求5所述的封装结构的制法,其特征为,该介电层的第二表面上还具有电性连接该导电柱的线路层。
10.如权利要求5所述的封装结构的制法,其特征为,该介电层为感光介质。
11.如权利要求10所述的封装结构的制法,其特征为,形成该开口的制程使用曝光显影制程。
12.如权利要求5所述的封装结构的制法,其特征为,该制法还包括设置堆迭件至该介电层的第二表面上,且该堆迭件电性连接该导电柱。
13.如权利要求12所述的封装结构的制法,其特征为,该堆迭件为封装基板、半导体晶片、中介板或封装件。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103123899 | 2014-07-11 | ||
TW103123899A TWI660476B (zh) | 2014-07-11 | 2014-07-11 | 封裝結構及其製法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105321902A CN105321902A (zh) | 2016-02-10 |
CN105321902B true CN105321902B (zh) | 2018-07-27 |
Family
ID=55068141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410362830.9A Active CN105321902B (zh) | 2014-07-11 | 2014-07-28 | 封装结构及其制法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20160013123A1 (zh) |
CN (1) | CN105321902B (zh) |
TW (1) | TWI660476B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103857210A (zh) * | 2012-11-28 | 2014-06-11 | 宏启胜精密电子(秦皇岛)有限公司 | 承载电路板、承载电路板的制作方法及封装结构 |
US10068181B1 (en) | 2015-04-27 | 2018-09-04 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafer and methods for making the same |
TWI605557B (zh) * | 2015-12-31 | 2017-11-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法與基板結構 |
US11355427B2 (en) * | 2016-07-01 | 2022-06-07 | Intel Corporation | Device, method and system for providing recessed interconnect structures of a substrate |
TWI610402B (zh) * | 2016-08-24 | 2018-01-01 | 矽品精密工業股份有限公司 | 電子封裝結構及其製法 |
US11121301B1 (en) | 2017-06-19 | 2021-09-14 | Rigetti & Co, Inc. | Microwave integrated quantum circuits with cap wafers and their methods of manufacture |
CN109216214B (zh) * | 2017-07-07 | 2021-03-30 | 欣兴电子股份有限公司 | 半导体封装结构及其制作方法 |
CN110769598B (zh) * | 2018-07-27 | 2021-11-16 | 宏启胜精密电子(秦皇岛)有限公司 | 内埋式电路板及其制作方法 |
TWI657516B (zh) * | 2018-07-27 | 2019-04-21 | 矽品精密工業股份有限公司 | 承載結構及封裝結構 |
CN111816569B (zh) * | 2020-07-28 | 2022-04-08 | 珠海越亚半导体股份有限公司 | 封装框架及其制作方法和基板 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101599476A (zh) * | 2008-06-04 | 2009-12-09 | 台湾应解股份有限公司 | 薄型双面封装基板及其制造方法 |
CN102915983A (zh) * | 2011-08-05 | 2013-02-06 | 欣兴电子股份有限公司 | 嵌埋有中介层的封装基板及其制法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
TW511405B (en) * | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
US7049170B2 (en) * | 2003-12-17 | 2006-05-23 | Tru-Si Technologies, Inc. | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
JP2006019441A (ja) * | 2004-06-30 | 2006-01-19 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
US8101868B2 (en) * | 2005-10-14 | 2012-01-24 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
US8022552B2 (en) * | 2006-06-27 | 2011-09-20 | Megica Corporation | Integrated circuit and method for fabricating the same |
JP5280014B2 (ja) * | 2007-04-27 | 2013-09-04 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US20080315407A1 (en) * | 2007-06-20 | 2008-12-25 | Vertical Circuits, Inc. | Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication |
US7842541B1 (en) * | 2008-09-24 | 2010-11-30 | Amkor Technology, Inc. | Ultra thin package and fabrication method |
KR20100037300A (ko) * | 2008-10-01 | 2010-04-09 | 삼성전자주식회사 | 내장형 인터포저를 갖는 반도체장치의 형성방법 |
US7858441B2 (en) * | 2008-12-08 | 2010-12-28 | Stats Chippac, Ltd. | Semiconductor package with semiconductor core structure and method of forming same |
US20100327419A1 (en) * | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
CN102201382B (zh) * | 2010-03-26 | 2013-01-23 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
KR101067109B1 (ko) * | 2010-04-26 | 2011-09-26 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
CN102751254A (zh) * | 2012-07-18 | 2012-10-24 | 日月光半导体制造股份有限公司 | 半导体封装件、应用其的堆迭封装件及其制造方法 |
US9214454B2 (en) * | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
-
2014
- 2014-07-11 TW TW103123899A patent/TWI660476B/zh active
- 2014-07-28 CN CN201410362830.9A patent/CN105321902B/zh active Active
- 2014-12-08 US US14/562,972 patent/US20160013123A1/en not_active Abandoned
-
2017
- 2017-06-28 US US15/636,217 patent/US20170301658A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101599476A (zh) * | 2008-06-04 | 2009-12-09 | 台湾应解股份有限公司 | 薄型双面封装基板及其制造方法 |
CN102915983A (zh) * | 2011-08-05 | 2013-02-06 | 欣兴电子股份有限公司 | 嵌埋有中介层的封装基板及其制法 |
Also Published As
Publication number | Publication date |
---|---|
TWI660476B (zh) | 2019-05-21 |
US20170301658A1 (en) | 2017-10-19 |
US20160013123A1 (en) | 2016-01-14 |
TW201603215A (zh) | 2016-01-16 |
CN105321902A (zh) | 2016-02-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105321902B (zh) | 封装结构及其制法 | |
US9899249B2 (en) | Fabrication method of coreless packaging substrate | |
CN107424970B (zh) | 半导体装置封装及其制造方法 | |
CN105097750A (zh) | 封装结构及其制法 | |
KR20130090143A (ko) | 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법 | |
CN105097759A (zh) | 封装堆栈结构及其制法暨无核心层式封装基板及其制法 | |
TW201517240A (zh) | 封裝結構及其製法 | |
CN105405775B (zh) | 封装结构的制法 | |
KR20190133907A (ko) | Pop형 반도체 패키지 및 그 제조 방법 | |
TWI582861B (zh) | 嵌埋元件之封裝結構及其製法 | |
CN105514053B (zh) | 半导体封装件及其制法 | |
TWI556402B (zh) | 封裝堆疊結構及其製法 | |
TWI550744B (zh) | 單層線路式封裝基板及其製法、單層線路式封裝結構及其製法 | |
CN105304583B (zh) | 封装结构的制法 | |
CN104979219B (zh) | 封装结构及其制法 | |
CN102956547B (zh) | 半导体封装结构及其制作方法 | |
CN105428326A (zh) | 封装结构及其制法 | |
CN106298728A (zh) | 封装结构及其制法 | |
CN107546189B (zh) | 封装堆迭结构 | |
KR101607989B1 (ko) | 패키지 온 패키지 및 이의 제조 방법 | |
CN104810339A (zh) | 封装基板及其制法暨半导体封装件及其制法 | |
TWI557860B (zh) | 半導體封裝件及其製法 | |
TW201508877A (zh) | 半導體封裝件及其製法 | |
JP2016225484A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2019057741A (ja) | 半導体装置および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |