CN104979219B - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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CN104979219B
CN104979219B CN201410164603.5A CN201410164603A CN104979219B CN 104979219 B CN104979219 B CN 104979219B CN 201410164603 A CN201410164603 A CN 201410164603A CN 104979219 B CN104979219 B CN 104979219B
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layer
preparation
load
bearing part
encapsulating structure
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CN104979219A (zh
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陈嘉成
孙铭成
沈子杰
邱士超
萧惟中
白裕呈
江东昇
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

一种封装结构及其制法，该制法先提供一具有多个焊垫的承载件，再压合一压合体于该承载件上，该压合体包含增层部与尺寸小于该增层部的离型部，该离型部覆盖该些焊垫，且该增层部压合于该离型部与该承载件上，之后形成多个导电柱于该增层部中，最后移除该离型部及其上的增层部，以形成开口于该压合体上，使该些焊垫外露于该开口，且该些导电柱位于该开口周围，藉以简化制程。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构及其制法，尤指一种能简化制程的封装结构的制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂堆加多个封装件以形成封装堆栈结构(Package on Package，POP)，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子组件，例如：内存、中央处理器、绘图处理器、影像应用处理器等，藉由堆栈设计达到系统的整合，适合应用于轻薄型各种电子产品。
一般封装堆栈结构(PoP)仅以焊锡球(solder ball)堆栈与电性连接上、下封装件，但随着产品尺寸规格与线距越来越小，该些焊锡球之间容易发生桥接(bridge)现象，将影响产品的良率。
于是，遂发展出一种封装堆栈结构，其以铜柱(Cu pillar)作支撑，以增加隔离(stand off)效果，可避免发生桥接现象。图1A及图1B为现有封装堆栈结构1的制法的剖面示意图。
如图1A所示，先提供一具有相对的第一及第二表面11a,11b的第一基板11，且于该第一基板11的第一表面11a上形成多个铜柱13。
如图1B所示，设置一电子组件15于该第一表面11a上且以覆晶方式电性连接该第一基板11，再叠设一第二基板12于该铜柱13上，之后形成封装胶体16于该第一基板11的第一表面11a与该第二基板12之间。具体地，该第二基板12藉由多个导电组件17结合该铜柱13，且该导电组件17由金属柱170与焊锡材料171构成。
然而，现有封装堆栈结构1中，该铜柱13以电镀形成，致使其尺寸变异不易控制，所以容易发生各铜柱13的高度不一致的情况，因而产生接点偏移的问题，致使该些导电组件17与该些铜柱13接触不良，而造成电性不佳，因而影响产品良率。
因此，如何在克服现有技术中的问题，实为业界迫切待解的课题。
发明内容
鉴于上述现有技术的缺失，本发明的目的为提供一种封装结构的制法，以简化制程。
本发明的封装结构的制法，包括：提供一具有多个焊垫的承载件；压合一压合体于该承载件上，该压合体包含增层部与尺寸小于该增层部的离型部，该离型部覆盖该些焊垫，且该增层部压合于该离型部与该承载件上；形成多个导电柱于该增层部中；以及移除该离型部及其上的增层部，以形成开口于该压合体上，使该些焊垫外露于该开口，且该些导电柱位于该开口周围。
本发明的封装结构，包括：承载件，具有多个焊垫；以及增层部，设于该承载件上，具有外露出各该焊垫的开口，其中，该增层部中具有多个导电柱，且各该导电柱位于该开口周围。
前述的封装结构中，该封装结构还包括绝缘保护层，设于该增层部上，且外露该导电柱。
前述的封装结构及其制法中，该承载件为预浸材、聚丙烯基板、树脂玻璃纤维基板或聚醯亚胺基板。
前述的制法中，该离型部包含相叠的第一金属层与第二金属层，且该第一金属层结合至该些焊垫与该承载件上。例如，该第一金属层与第二金属层之间物理性靠合，且该第二金属层在该承载件上的投影面积小于该第一金属层在该承载件上的投影面积。
前述的制法中，该导电柱的形成步骤包括先形成贯穿该增层部的多个穿孔，再于该些穿孔中填充导电材料以作为该导电柱。
前述的封装结构及其制法中，该增层部还具有电性连接该导电柱的线路层。
前述的封装结构及其制法中，设置堆栈件至该增层部上，且该堆栈件电性连接该导电柱，例如，该堆栈件为基板、半导体芯片、硅中介板、经封装或未经封装的半导体组件。
前述的制法中，移除该离型部及其上的增层部的步骤包括：激光切割该增层部，以移除部分该离型部与其上的增层部；以及蚀刻移除剩余的该离型部。
另外，前述的封装结构及其制法中，还包括设置电子组件于该开口中，且该电子组件电性连接该些焊垫。
前述的封装结构及其制法中，该增层部还包括：介电层，与该承载件接触，并具有外露出各该焊垫的开口；以及板体，形成于该介电层上。
由上可知，本发明封装结构及其制法，主要藉由在该承载件上压合该增层部以制作导电柱，而能增加隔离效果及避免桥接现象。
此外，藉由该些穿孔控制各该导电柱的尺寸，使各该导电柱的高度一致，以避免接点偏移的问题，所以相较于现有技术，后续制程的导电组件与该些导电柱不会发生接触不良或短路的问题，因而能有效提高产品良率。
附图说明
图1A至图1B为现有封装堆栈结构的制法的剖视示意图；以及
图2A至图2G为本发明封装结构的制法的剖视示意图。
符号说明
1 封装堆栈结构
11 第一基板
11a,250a 第一表面
11b,250b 第二表面
12 第二基板
13 铜柱
15,28 电子组件
16 封装胶体
17,291 导电组件
170 金属柱
171 焊锡材料
2 封装结构
21 承载件
21a 表面
210 焊垫
211 电性连接垫
22 压合体
22a 增层部
22b 离型部
220 开口
23 介电层
241 第一金属层
242 第二金属层
25 支撑板
250 板体
251 导体层
251’ 线路层
26 导电柱
260 穿孔
27 绝缘保护层
280 底胶
281 导电凸块
29 堆栈件
A 承载区
B 投影面积
S 切割路径。
具体实施方式
以下藉由特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。本发明也可藉由其它不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本创作可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本创作所能产生的功效及所能达成的目的下，均应仍落在本创作所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如「第一」、「第二」、「上」及「一」等用语，也仅为便于叙述的明了，而非用于限定本创作可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2F为显示本发明的封装结构的制法示意图。
如图2A所示，提供一压合体22、及一具有多个焊垫210与多个电性连接垫211的承载件21。
于本实施例中，该承载件21为预浸材、聚丙烯基板、树脂玻璃纤维基板或聚醯亚胺基板，且该承载件21定义有一承载区A，使该些焊垫210位于该承载区A内，而该电性连接垫211位于该承载区A外。
此外，该压合体22包含一增层部22a与一离型部22b。
所述的增层部22a具有一支撑板25与一可外露该承载区A的介电层23，该支撑板25包括一具有相对的第一表面250a与第二表面250b的板体250、及设于该第一表面250a上的导体层251。具体地，该介电层23的材质为预浸材(prepreg,PP)，该板体250为双顺丁烯二酸醯亚胺/三氮阱(Bismaleimide Triazine,BT)的树脂与玻纤布，该导体层251为铜层。
所述的离型部22b包含第一金属层241与第二金属层242，且该第一金属层241与第二金属层242之间仅物理性靠合，例如，该第一金属层241与第二金属层242为铜层，但不限于此。具体地，于压合制程前，该第一金属层241结合至该些焊垫210与该承载件21的表面21a上，而该第二金属层242结合至该板体250的第二表面250b上。另外，该第二金属层242在该承载件21上的投影面积B小于该第一金属层241在该承载件21上的投影面积(如该承载区A)。
如图2B所示，将该压合体22压合于该承载件21的表面21a上，该离型部22b覆盖该些焊垫210，且该增层部22a压合于该离型部22b与该承载件21上。
于本实施例中，藉由将该增层部22a、该离型部22b与该承载件21以热压合直接压合，使制程简化，且藉由该第一金属层241得以避免热压合制程中发生该介电层23的溢流问题。
此外，该离型部22b藉由该介电层23与该板体250夹固，使该第一金属层241与第二金属层242不会移动。
如图2C所示，以激光钻孔方式于对应该电性连接垫211的位置上形成贯穿该介电层23与该板体250的多个穿孔260。
如图2D所示，利用该导体层251，于该板体250上制作线路层251’，且于该些穿孔260中形成导电材料以作为导电柱26，且藉由该导电柱26电性连接该线路层251’与该些电性连接垫211。接着，还可于该板体250的第一表面250a与该线路层251’上形成绝缘保护层27，且该绝缘保护层27外露出该线路层251’，供后续制程中接置其它外部组件。
于本实施例中，该线路层251’与该绝缘保护层27并未形成于对应该承载区A的第一表面250a上。
如图2E所示，移除对应该承载区A的板体250、第二金属层242与部分该介电层23。
于本实施例中，先以激光切割方式沿该承载区A的边缘切割该板体250与部分该介电层23，如图2C所示的切割路径S，即切割深度至该第一金属层241，再利用该第一金属层241与第二金属层242之间的物理性靠合，当取出该该板体250与部分该介电层23时，一并以剥离方式取出该第二金属层242。
如图2F所示，移除该第一金属层241，以形成一开口220于该压合体22上，使该承载件21于该承载区A的表面21a与该些焊垫210外露于该开口220，且该些导电柱26位于该开口220周围。
于本实施例中，以蚀刻方式移除该第一金属层241，但不限于此。
如图2G所示，于该开口220内设置电子组件28，且该电子组件28以多个导电凸块281电性连接该些焊垫210并以底胶280包覆该些导电凸块281。接着，设置一堆栈件29于该线路层251’上，以令该堆栈件29叠设于该增层部22a上，且覆盖该开口220与该电子组件28，以制得本发明的封装结构2。
于本实施例中，该堆栈件29为封装基板、半导体芯片、晶圆、硅中介板或封装件，且该堆栈件29藉由多个如焊锡材料的导电组件291电性结合至该线路层251’。
综上所述，本发明封装结构的制法中，藉由在承载件21上形成增层部22a(即该介电层23、支撑板25与导电柱26)，使该导电柱26嵌入该介电层23与支撑板25中，再于该增层部22a上接置该堆栈件29，藉以增加隔离(stand off)各该导电柱26的效果、及避免各该导电柱26之间发生桥接现象。
此外，藉由该些穿孔260控制各该导电柱26的尺寸，使各该导电柱26的高度一致，以令该些导电组件291的接置处高度一致，因而能避免接点偏移的问题，所以该些导电组件291与该些导电柱26不会发生接触不良或短路(short)的问题，因而能有效提高产品良率。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (8)

1.一种封装结构的制法，包括：
提供一具有多个焊垫的承载件；
压合一压合体于该承载件上，该压合体包含增层部与尺寸小于该增层部的离型部，该离型部覆盖所述焊垫，且该增层部压合于该离型部与该承载件上，其中，该离型部包含相叠的第一金属层与第二金属层，且该第一金属层结合至所述焊垫与该承载件上，该增层部包括：
介电层，与该承载件接触；
板体，具有相对的第一表面与第二表面，并形成于该介电层上，且该离型部的第二金属层结合至该板体的第二表面上；以及
导体层，直接形成于该板体的第一表面上；
形成多个贯穿该增层部的导电柱于该增层部中；
利用该导体层，于该板体上制作线路层，且该线路层电性连接该导电柱；
激光切割该增层部，以移除部分该离型部与其上的增层部，以形成开口于该压合体上；以及
蚀刻移除剩余的该离型部，使所述焊垫外露于该开口，且所述导电柱位于该开口周围。
2.如权利要求1所述的封装结构的制法，其特征在于，该承载件为预浸材、聚丙烯、树脂玻璃纤维或聚醯亚胺。
3.如权利要求1所述的封装结构的制法，其特征在于，该第一金属层与第二金属层之间物理性靠合。
4.如权利要求1所述的封装结构的制法，其特征在于，该第二金属层在该承载件上的投影面积小于该第一金属层在该承载件上的投影面积。
5.如权利要求1所述的封装结构的制法，其特征在于，该导电柱的形成步骤包括先形成贯穿该增层部的多个穿孔，再于所述穿孔中填充导电材料以作为该导电柱。
6.如权利要求1所述的封装结构的制法，其特征在于，该制法还包括设置堆栈件至该增层部上，且该堆栈件电性连接该导电柱。
7.如权利要求6所述的封装结构的制法，其特征在于，该堆栈件为封装基板、半导体芯片、硅中介板或封装件。
8.如权利要求1所述的封装结构的制法，其特征在于，该制法还包括设置电子组件于该开口中，且该电子组件电性连接所述焊垫。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599476A (zh) * 2008-06-04 2009-12-09 台湾应解股份有限公司 薄型双面封装基板及其制造方法
CN102201382A (zh) * 2010-03-26 2011-09-28 日月光半导体制造股份有限公司 半导体封装件及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
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US8810025B2 (en) * 2011-03-17 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcement structure for flip-chip packaging
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599476A (zh) * 2008-06-04 2009-12-09 台湾应解股份有限公司 薄型双面封装基板及其制造方法
CN102201382A (zh) * 2010-03-26 2011-09-28 日月光半导体制造股份有限公司 半导体封装件及其制造方法

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