US20160013123A1 - Package structure and fabrication method thereof - Google Patents

Package structure and fabrication method thereof Download PDF

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Publication number
US20160013123A1
US20160013123A1 US14/562,972 US201414562972A US2016013123A1 US 20160013123 A1 US20160013123 A1 US 20160013123A1 US 201414562972 A US201414562972 A US 201414562972A US 2016013123 A1 US2016013123 A1 US 2016013123A1
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United States
Prior art keywords
dielectric layer
conductive posts
cavity
bonding pads
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US14/562,972
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English (en)
Inventor
Yu-Cheng Pai
Chun-Hsien Lin
Shih-Chao Chiu
Wei-Chung Hsiao
Ming-Chen Sun
Tzu-Chieh Shen
Chia-Cheng Chen
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD. reassignment SILICONWARE PRECISION INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, CHIA-CHENG, CHIU, SHIH-CHAO, HSIAO, WEI-CHUNG, LIN, CHUN-HSIEN, PAI, YU-CHENG, SHEN, TZU-CHIEH, SUN, MING-CHEN
Publication of US20160013123A1 publication Critical patent/US20160013123A1/en
Priority to US15/636,217 priority Critical patent/US20170301658A1/en
Abandoned legal-status Critical Current

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    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components

Definitions

  • the present invention relates to package structures and fabrication methods thereof, and more particularly, to a package structure and a fabrication method thereof having simplified processes.
  • PoP package on package
  • SiP system-in-package
  • PoP structure At least two packages are stacked on one another and electrically connected through a plurality of solder balls.
  • solder bridging easily occurs between the solder balls, thus adversely affecting the product yield.
  • FIGS. 1A and 1B are schematic cross-sectional views showing a method for fabricating a PoP structure 1 according to the prior art.
  • a first substrate 11 having a first surface 11 a with a plurality of copper pillars 13 and a second surface 11 b opposite to the first surface 11 a is provided.
  • an electronic element 15 is disposed on the first surface 11 a and electrically connected to the first substrate 11 in a flip-chip manner.
  • a second substrate 12 is stacked on the first substrate 11 through the copper pillars 13 .
  • the second substrate 12 is bonded to the copper pillars 13 through a plurality of conductive elements 17 .
  • Each of the conductive elements 17 consists of a metal pillar 170 and a solder material 171 formed on the metal pillar 170 .
  • an encapsulant 16 is formed between the first surface 11 a of the first substrate 11 and the second substrate 12 .
  • the size of the copper pillars 13 is difficult to control and the copper pillars 13 tend to have uneven heights. As such, a positional deviation easily occurs to the joints between the conductive elements 17 and the copper pillars 13 and hence a poor bonding easily occurs therebetween, thereby reducing the electrical performance and the product yield of the PoP structure 1 .
  • the present invention provides a package structure, which comprises: a carrier having a plurality of bonding pads; a dielectric layer having opposite first and second surfaces and formed on the carrier via the first surface thereof, wherein at least a cavity is formed in the second surface of the dielectric layer to expose the bonding pads; and a plurality of conductive posts formed in the dielectric layer and positioned around a periphery of the cavity.
  • the present invention further provides a method for fabricating a package structure, which comprises the steps of: providing a carrier having a plurality of bonding pads and a dielectric layer having opposite first and second surfaces; laminating the dielectric layer on the carrier via the first surface thereof, wherein the bonding pads are covered by the dielectric layer; forming a plurality of conductive posts in the dielectric layer; and forming at least a cavity in the second surface of the dielectric layer so as to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity.
  • the second surface of the dielectric layer can have a conductive layer used for forming the conductive posts.
  • forming the conductive posts can comprise: forming a plurality of through holes penetrating the dielectric layer; and filling a conductive material in the through holes to form the conductive posts.
  • the above-described method can further comprise stacking a stack member on the second surface of the dielectric layer, wherein the stack member is electrically connected to the conductive posts.
  • the stack member can be a packaging substrate, a semiconductor chip, an interposer or a package.
  • the carrier can be a packaging substrate, a semiconductor chip, a wafer, an interposer, or a packaged or unpackaged semiconductor element.
  • a circuit layer can be formed on the second surface of the dielectric layer and electrically connected to the conductive posts.
  • the dielectric layer can be made of a photo imageable dielectric material.
  • the cavity can be formed by exposure and development.
  • the above-described structure and method can further comprise disposing an electronic element in the cavity, wherein the electronic element is electrically connected to the bonding pads.
  • a dielectric layer is laminated on a carrier and a plurality of conductive posts are formed in the dielectric layer so as to achieve a preferred stand-off effect and prevent bridging from occurring between the conductive posts.
  • the size of the conductive posts can be controlled through the through holes so as to cause the conductive posts to have a uniform height. Therefore, the present invention overcomes the conventional drawback of joint deviation and ensures a reliable bonding between the conductive posts and the conductive elements to be formed later, thereby improving the product yield.
  • FIGS. 1A and 1B are schematic cross-sectional views showing a method for fabricating a PoP structure according to the prior art.
  • FIGS. 2A to 2G are schematic cross-sectional views showing a method for fabricating a PoP structure according to the present invention.
  • FIGS. 2A to 2G are schematic cross-sectional views showing a method for fabricating a package structure according to the present invention.
  • a carrier 21 having a plurality of first bonding pads 210 and a plurality of second bonding pads 211 is provided.
  • the carrier 21 is a packaging substrate, a semiconductor chip, a wafer, an interposer, or a packaged or unpackaged semiconductor element.
  • the carrier 21 is a coreless packaging substrate, which has a plurality of dielectric layers 213 and a plurality of circuit layers 211 ′ alternately stacked on one another and a plurality of conductive vias 212 penetrating the dielectic layers 213 and electrically connected to the circuit layers 211 ′.
  • a metal layer 214 made of such as copper is formed on a lower side of the carrier 21 .
  • a carrying area A is defined on the carrier 21 .
  • the first bonding pads 210 are positioned inside the carrying area A and the second bonding pads 211 are positioned outside the carrying area A.
  • a dielectric layer 22 having a conductive layer 23 thereon is laminated on the carrier 21 to cover the first and second bonding pads 210 , 211 . Then, by performing a laser drilling process, a plurality of through holes 260 are formed to penetrate the dielectric layer 22 and the conductive layer 23 corresponding in position to the second bonding pads 211 .
  • the dielectric layer 22 has opposite first and second surfaces 22 a , 22 b .
  • the conductive layer 23 is formed on the second surface 22 b of the dielectric layer 22 , and the dielectric layer 22 is laminated on the carrier 21 via the first surface 22 a thereof.
  • the dielectric layer 22 is made of a photo imageable dielectric (PID) material and the conductive layer 23 is a copper layer.
  • PID photo imageable dielectric
  • the present invention simplifies the fabrication process.
  • a circuit layer 25 is formed on the second surface 22 b of the dielectric layer 22 and a conductive material is filled in the through holes 260 to form a plurality of conductive posts 26 electrically connecting the circuit layer 25 and the second bonding pads 211 .
  • the circuit layer 25 is not formed on the second surface 22 b of the dielectric layer 22 corresponding in position to the carrying area A.
  • the metal layer 214 on the lower side of the carrier 21 is patterned to form a circuit layer 25 ′.
  • a cavity 220 is formed in the second surface 22 b of the dielectric layer 22 to expose the first bonding pads 210 .
  • the conductive posts 26 are positioned around a periphery of the cavity 220 . As such, a package structure 2 is formed.
  • an upper side of the carrier 21 in the carrying area A is also exposed from the cavity 220 .
  • an insulating layer 27 is formed on the second surface 22 b of the dielectric layer 22 and the lower side of the carrier 21 , and portions of the circuit layers 25 , 25 ′ are exposed from the insulating layer 27 for mounting external elements in subsequent processes.
  • At least an electronic element 28 is disposed in the cavity 220 and electrically connected to the first bonding pads 210 through a plurality of conductive bumps 281 .
  • a stack member 29 is stacked on the exposed portions of the circuit layer 25 and covers the cavity 220 and the electronic element 28 . As such, a package structure 3 is formed.
  • the stack member 29 is a packaging substrate, a semiconductor chip, a wafer, a silicon interposer or a package.
  • the stack member 29 is electrically connected to the circuit layer 25 and the conductive posts 26 through a plurality of conductive elements 291 made of such as a solder material or metal posts.
  • an encapsulant 30 is formed between the stack member 29 and the carrier 21 for encapsulating the conductive bumps 281 .
  • the present invention further provides a package structure 2 , which has: a carrier 21 having a plurality of bonding pads 210 ; a dielectric layer 22 having opposite first and second surfaces 22 a , 22 b and disposed on the carrier 21 via the first surface 22 a thereof, wherein at least a cavity 220 is formed in the second surface 22 b of the dielectric layer 22 to expose the bonding pads 210 ; and a plurality of conductive posts 26 formed in the dielectric layer 22 and positioned around a periphery of the cavity 220 .
  • the carrier 21 can be a packaging substrate, and the dielectric layer 22 can be made of a photo imageable dielectric material.
  • a circuit layer 25 can be formed on the second surface 22 b of the dielectric layer 22 and electrically connected to the conductive posts 26 .
  • the package structure 2 further has an electronic element 28 disposed in the cavity 220 and electrically connected the bonding pads 210 .
  • a dielectric layer 22 is formed on a carrier 21 , a plurality of conductive posts 26 are embedded in the dielectric layer 22 and a stack member 29 is stacked on the dielectric layer 22 and electrically connected to the conductive posts 26 .
  • the present invention achieves a preferred stand-off effect between the conductive posts 26 so as to prevent bridging from occurring between the conductive posts 26 .
  • the size of the conductive posts 26 can be controlled through the through holes 260 so as to cause the conductive posts 26 to have a uniform height. Therefore, the present invention overcomes the conventional drawback of joint deviation and ensures a reliable bonding between the conductive posts 26 and conductive elements 291 , thus improving the product yield.
  • the cavity 220 can be formed in the dielectric layer 22 by exposure and development, thereby simplifying the fabrication process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US14/562,972 2014-07-11 2014-12-08 Package structure and fabrication method thereof Abandoned US20160013123A1 (en)

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TW103123899A TWI660476B (zh) 2014-07-11 2014-07-11 封裝結構及其製法

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US20200037450A1 (en) * 2018-07-27 2020-01-30 HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd. Embedded circuit board and method of making same
US10769546B1 (en) * 2015-04-27 2020-09-08 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
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TWI610402B (zh) * 2016-08-24 2018-01-01 矽品精密工業股份有限公司 電子封裝結構及其製法
CN109216214B (zh) * 2017-07-07 2021-03-30 欣兴电子股份有限公司 半导体封装结构及其制作方法
TWI657516B (zh) * 2018-07-27 2019-04-21 矽品精密工業股份有限公司 承載結構及封裝結構
CN111816569B (zh) * 2020-07-28 2022-04-08 珠海越亚半导体股份有限公司 封装框架及其制作方法和基板

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Also Published As

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US20170301658A1 (en) 2017-10-19
CN105321902B (zh) 2018-07-27
TW201603215A (zh) 2016-01-16
CN105321902A (zh) 2016-02-10

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