TWI550803B - 封裝半導體裝置 - Google Patents

封裝半導體裝置 Download PDF

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Publication number
TWI550803B
TWI550803B TW104105505A TW104105505A TWI550803B TW I550803 B TWI550803 B TW I550803B TW 104105505 A TW104105505 A TW 104105505A TW 104105505 A TW104105505 A TW 104105505A TW I550803 B TWI550803 B TW I550803B
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Taiwan
Prior art keywords
layer
metal layer
under
ball
conductive bump
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TW104105505A
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English (en)
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TW201631721A (zh
Inventor
黃春福
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南茂科技股份有限公司
百慕達南茂科技股份有限公司
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Priority to TW104105505A priority Critical patent/TWI550803B/zh
Priority to CN201510448508.2A priority patent/CN105895604B/zh
Priority to US14/845,826 priority patent/US20160240500A1/en
Publication of TW201631721A publication Critical patent/TW201631721A/zh
Application granted granted Critical
Publication of TWI550803B publication Critical patent/TWI550803B/zh

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Description

封裝半導體裝置
隨著半導體科技的日新月異,電子產業經歷了由厚膜至薄膜的快速變革,以及從不停歇的微小化製程改良。半導體封裝是一門建立半導體元件之間連結以形成一電路的科學,也因應半導體與電子產業的不斷進步而快速發展。
在半導體封裝製程中,銲球與晶片或其他元件的接合須有一定的可靠度,以避免在完成封裝後產生電性失效或故障。在大部分的情形下,主要是附著在如銲墊或導電柱上,然而,在實際狀況,卻常發生銲球脫落或無法有效附著的情形而導致良率無法有效地提升。
因此,如何增加銲球與半導體元件間的附著力以提高其可靠度實為一重要的課題。
本發明之一實施例提供一種封裝半導體裝置,該封裝半導體裝置包括一基板,其中該基板包含一接墊;以及一鈍化層配置於該基板上方,其中該鈍化層係局部覆蓋該接墊:一球下金屬層,配置於該基板上方,其中該球下金屬層係與該接墊耦合;一導電凸塊,配置於該球下金屬層之上方,其中該導電凸塊,包含:一柱體,係連接該球下 金屬層;一帽體,配置於該柱體的頂部,其中,該帽體包含一底部截面積係大於該柱體的截面積,該帽體之底部距離該鈍化層之上表面具有一間隔;以及一銲球,係包覆該導電凸塊。
在一實施例中,該帽體包含一底部寬度係大於該球下金屬層的寬度。
在一實施例中,該銲球係包覆該柱體之側壁及該間隔。
在一實施例中,該帽體之頂面係為一曲面,該帽體的中心部分之厚度大於該帽體的邊緣部分之厚度。
在一實施例中,該導電凸塊之材質選自於金、銅、鎳、銀或其合金。
在一實施例中,該球下金屬層之材質選自為鈦/銅、鈦/鎢/金或含銀合金。
本發明之一實施例提供一種封裝半導體裝置,該封裝半導體裝置包括一基板,其中該基板包含一接墊;以及一鈍化層配置於該基板上方並暴露出該接墊之部份:一重佈層配置於該鈍化層上,並與該接墊之該部份耦合;一保護層配置於該重佈層上,並且暴露出該重佈層之部分;一球下金屬層配置於該保護層上,其中該球下金屬層係與該該重佈層之該部分耦合;一導電凸塊,配置於該球下金屬層之上方,其中該導電凸塊,包含:一柱體,係連接該球下金屬層;一帽體,配置於該柱體的頂部,其中,該帽體包含一底部截面積係大於該柱體的截面積,且該帽體之底部距離該保護層之上表面具有一間隔;以及一銲球,係包覆該導電凸塊。
前文已頗為廣泛地概述本發明之特徵及技術優勢以便可更好地理解隨後的本發明之詳細描述。本發明之額外特徵及優勢將在下文中加以描述,且形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解,所揭示之概念及特定實施例可易於用作修改或設計其他結構或 程序以用於進行本發明之同樣目的之基礎。熟習此項技術者亦應認識到,此等等效構造並不脫離如隨附申請專利範圍中所闡明之本發明之精神及範疇。
10‧‧‧基板
20‧‧‧接墊
30‧‧‧鈍化層
40‧‧‧球下金屬層
31‧‧‧開孔
50‧‧‧導電凸塊
41‧‧‧側壁
52‧‧‧帽體
51‧‧‧柱體
54‧‧‧厚度
53‧‧‧頂面
56‧‧‧間隔
55‧‧‧側壁
58‧‧‧底部
57‧‧‧側壁
60‧‧‧銲球
62‧‧‧圖案化光阻層
64‧‧‧開孔
71‧‧‧鈍化層
72‧‧‧重佈層
74‧‧‧保護層
76‧‧‧球下金屬層
78‧‧‧側壁
80‧‧‧導電凸塊
82‧‧‧銲球
85‧‧‧帽體
86‧‧‧頂面
87‧‧‧側壁
88‧‧‧柱體
89‧‧‧側壁
90‧‧‧間隔
91‧‧‧金屬層
92‧‧‧圖案化層
95‧‧‧底部
94‧‧‧開孔
200‧‧‧半導體結構
100‧‧‧半導體結構
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意,根據產業之標準實施方式,各種特徵並非依比例繪示。實際上,為了清楚討論,可任意增大或縮小各種特徵的尺寸。
圖1A-1B係根據本申請案揭示內容之一些實施例說明封裝半導體裝置之橫切面圖。
圖2係根據本申請案揭示內容之一些實施例說明封裝半導體裝置之橫切面圖。
圖3A-3B係根據本申請案揭示內容之一些實施例說明製造封裝半導體裝置之方法的橫切面圖。
上文已經概略地敍述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應可瞭解,下文揭示之概念與特定實施例可作為基礎而相當輕易地予以修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應可瞭解,這類等效的建構並無法脫離後附之申請專利範圍所提出之本揭露的精神和範圍。
以下揭示內容提供許多不同的實施方式或範例,用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下,以簡化本申請案之揭示內容。當然,這些僅為範例,並非用於限制本申請案。例 如,以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施方式,亦可包含在該第一與第二特徵之間形成其他特徵的實施方式,因而該第一與第二特徵並非直接接觸。此外,本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的,而非支配不同實施方式與/或所討論架構之間的關係。
再者,本申請案可使用空間對應語詞,例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明,以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外,裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向),並且可相應解釋本申請案使用的空間對應描述。
隨著及元件的微縮,如何增加銲球與半導體元件間的附著力以提高其可靠度實為一重要的課題。其附著關係例如銲球附著於球下金屬層(underbump metallization,UBM)上方、銲球附著於重分佈層(redistribution layer,RDL)上方或是銲球附著於導電柱上方。現有技術中,銲球底部可形成一球下金屬層,使錫球坐落於該球下金屬層上方,通常的狀況下,銲球底部側壁與球下金屬層的邊緣側壁切齊,或是銲球底部與球下金屬層的接觸面積小於球下金屬層的面積,使得球下金屬層的邊緣側壁或是部分球下金屬層仍外露於錫球外部。如此一來,由於銲球僅依靠金屬接合坐落於球下金屬層上,仍有脫落銲球的可能性。
本申請案提供一種利用球下金屬層的邊緣延伸至銲球內部,藉以使銲球可以完全包覆球下金屬層,使得銲球的結構更加穩固不容易掉球,可以達到增加結合穩固性的效果。
圖1A係依據本發明部分實施例所載之半導體結構100。半導體結 構100係包含基板10、接墊20、鈍化層30、球下金屬層40、導電凸塊50、銲球60,其中:基板10,為一半導體材料,例如是矽晶圓、玻璃、陶瓷或其它類似之半導體材料,該基板10具有一主動面及一與其相對之被動面;接墊20係設置於半導體基板10之主動面上,該接墊20之材質較佳可選自於金、銀、銅、鋁或其合金等材料,以作為半導體基板10與外界電性傳導的接點。鈍化層30係設置於半導體基板10之主動面上,並相對該接墊20位置定義出一開孔31以暴露出接墊20之一部分。
球下金屬層40設置在暴露於開孔31中之接墊20上與接墊20形成電連接,其中,該球下金屬層40包括至少兩層金屬層(未繪示),即黏接層例如鈦層、銅層以及鎳層;與晶種層位於該黏接層上且由金、銅、鎳、銀或其合金組成。另有許多合適的球下金屬層40材料與層次配置,例如鈦/銅、鈦/鎢/金、含銀合金、鉻/鉻銅合金/銅/金、鈦/鈦鎢/銅之配置或是銅/鎳/金之配置。球下金屬層40係由金屬濺鍍程序、物理或化學氣相沈積程序形成。之後,在球下金屬層40的上方形成導電凸塊50,導電凸塊50包含一柱體51與一帽體52。柱體51連接底下的球下金屬層40且支撐上方的帽體52。進一步而言,柱體51的寬度等於球下金屬層40的寬度(兩側壁41之間距離),使得柱體51的側壁57與球下金屬層40的側壁41切齊。此外,帽體52底部截面積(以切線AA'為基準)大於柱體51的截面積,於其一可行之實施例中,該柱體51截面積約為帽體52底部截面積5%-25%,且帽體52具有一厚度54,厚度54係量自帽體52之頂面53最高點至帽體52之底部58的厚度數值,厚度54為高度H(帽體52最頂部至鈍化層30上表面的高度)的約10%-40%。從側面觀之,帽體52之底部58的寬度(兩側壁55之間的距離)大於球下金屬層40的寬度(兩側壁41之間的距離),等同帽體52的邊緣水平突出於柱體51之外,使得帽體52的底部58與鈍化層30上表面之間 產生一間隔56。
最後,於導電凸塊50上設置一銲球60,銲球60之材料例如是金/錫或錫/銀等材料,該銲球60包覆了導電凸塊50的頂面53、帽體52之側壁55、間隔56以及柱體51之側壁57,其中,銲球60不但包覆導電凸塊50整體且進一步包覆球下金屬層40的側壁41。更進一步來說,導電凸塊50之間隔56的形成使得部分銲球60材料能填充於間隔56中,當銲球60迴銲並且固化後,銲球60可完全包覆住間隔56,如同銲球材料嵌人間隔56中,間隔56與帽體52形成如同一卡榫或倒勾的裝置,係利用結構力學方式增加銲球60與導電凸塊50的附著力,藉以防止銲球60自導電凸塊50上脫落。此外,水平突出的帽體52相較於原本單純僅球下金屬層的連接方式具有更大的接觸面積,銲球60與導電凸塊50之間的接觸面積增加,使得有效地提升兩者之間的附著力。間隔56的高度(由帽體52之底部58至鈍化層30上表面)約為5-9微米,係約為高度H(帽體52最頂部至鈍化層30上表面的高度)的60%-90%。在一實施例中,頂面53係為一平面,故頂面53具有同一高度;另一實施例中,頂面53為一曲面,例如一凹面(該帽體52的中心部分之厚度小於該帽體52的邊緣部分之厚度)或一凸面(該帽體52的中心部分之厚度大於該帽體52的邊緣部分之厚度);另一實施例中,頂面53為一粗糙面,非平面狀態的頂面53能增加銲球60與導電凸塊50之間的接觸面積,進而增加銲球60與導電凸塊50的黏著程度。
藉由上述導電凸塊50之柱體51與帽體52的比例,同時讓銲球60包覆間隔56、球下金屬層40的側壁41與導電凸塊50整體,使得銲球60與導電凸塊50之間的接觸面積增加,有效地提升兩者之間的附著力,能防止掉球的狀況。
值得一提的是,如圖1B所示,導電凸塊50的形成方式可在沉積球下金屬層40後,成長一圖案化光阻層62,該圖案化光阻層62具有一 開孔64位於接墊20上方並且暴露出部分球下金屬層40。特別地,該圖案化光阻層62的厚度大約為5至8微米(μm),形成圖案化光阻層62後進行電鍍步驟以形成導電凸塊50。特別地,讓電鍍金屬材料填滿開孔64後,刻意讓金屬材料逸出於開孔64外,讓外溢的金屬材料形成一帽體52。形成導電凸塊50的方法另包含進行物理、化學氣相沉積。導電凸塊50包含金、銀、銅、鋁、鎢、鎳、鈷的金屬合金,以及/或類似物。在一實施例中,導電凸塊50係與球下金屬層40最上層(例如晶種層)之金屬材料相同,等同球下金屬層40往上方延伸,可視為球下金屬層40之一部分,之後,將圖案化光阻層62及部分球下金屬層40去除後,再於導電凸塊50上形成鍚球60,形成鍚球60的方式可採用電鍍、印刷或植球後再進行一道迴焊製程,使錫球60能完全包覆並固定於該導電凸塊50上(如圖1A所示)。
圖2係依據本發明部分實施例所載之半導體結構200。半導體結構200包含基板10、接墊20、重佈層72(redistribution layer,RDL)、保護層74或聚合物層、球下金屬層76、導電凸塊80、銲球82。鈍化層71覆蓋基板10之主動面上並且具有一開孔暴露出部分接墊20,重佈層72為一圖案化的金屬層,其係透過鈍化層71的開孔連接接墊20,提供接墊20與銲球82耦合的途徑。保護層74覆蓋鈍化層71與部分重佈層72,保護層74具有一開孔使得一部份重佈層72露出。球下金屬層76形成於保護層74的開孔中,且透過該開孔與重佈層72連接。導電凸塊80形成於球下金屬層76上方,導電凸塊80包含一帽體85與一柱體88。銲球82包覆導電凸塊80整體及球下金屬層76的側壁78,更明確地,銲球82包覆頂面86、帽體85之側壁87、柱體88之側壁89。帽體85的底部截面積(以切線BB'為基準)大於柱體88的截面積,從側面觀之,帽體85之底部95的寬度(兩側壁87的距離)大於球下金屬層76的寬度(兩側壁78的距離),帽體85邊緣係水平突出於柱體88之外,使得帽體85之底 部95與保護層74上表面之間產生一間隔90,使得部分銲球材料能填充於間隔90中,當銲球82迴銲並且固化後,銲球82可包覆間隔90、導電凸塊80與球下金屬層76的側壁78,間隔90與帽體85形成如同一卡榫或倒勾的裝置,係利用結構力學方式增加銲球82與導電凸塊80的附著力,能防止銲球82脫落。此外,銲球82與導電凸塊80之間的接觸面積增加,有效地提升兩者之間的附著力。
圖3A-3B係依據本發明部分實施例所載之半導體結構200之製造方法。如圖3A所示,保護層74經過圖案化處理後具有一開孔暴露部分的重佈層72,一金屬層91沈積於基板10上並且覆蓋保護層74與部分的重佈層72,金屬層91透過保護層74的開孔與重佈層72連接。接著,形成圖案化層92於金屬層91上,並具有一開孔94暴露出下方的金屬層91,於另一可行之實施例中,該圖案化層92的厚度大約為5至8微米(μm)。
如圖3B所示,利用電鍍方式將金屬材料沈積於開孔94中,特別地,讓金屬材料填滿開孔94並且溢出於開孔94之開口,使得部分金屬材料位於圖案化層92之上,而形成帽體85。一實施例中,控制電鍍成長讓帽體85之頂部具有一平面;一實施例中,控制電鍍成長讓帽體85之頂面具有一曲面例如:凹面或凸面。另一實施例中,亦可利用沈積方式形成導電凸塊80。其後,將圖案化層92移除且蝕刻移除該金屬層91,使原本在帽體85下方的圖案化層92與金屬層91之所在位置形成為間隔90,該間隔90的高度係等同原本圖案化層92及該金屬層91的厚度。其後,進行一形成銲球步驟銲球形成方式例如但不限於網版印刷、蒸鍍、電鍍、落球、噴球等。於一可行之實施例中,銲球82之形成方式可採用落球方式,於實施上配合一鋼版(Stencil)使用(未繪示),銲球82藉由鋼版輔助落球於球下金屬層76上,再利用迴銲步驟,使得銲球82包覆導電凸塊80整體與球下金屬層76之側壁78,包含 導電凸塊80與保護層71之間所形成之間隔90,由於間隔90的產生讓銲球82與導電凸塊80之間的接觸面積增加,導致附著力的提升而防止掉球的狀況。
前述內容概述一些實施方式的特徵,因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎,用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍,以及熟知此技藝之人士可進行各種變化、取代與替換,而不脫離本申請案揭示內容之精神與範圍。
10‧‧‧基板
20‧‧‧接墊
30‧‧‧鈍化層
31‧‧‧開孔
40‧‧‧球下金屬層
50‧‧‧導電凸塊
41‧‧‧側壁
52‧‧‧帽體
51‧‧‧柱體
54‧‧‧厚度
53‧‧‧頂面
56‧‧‧間隔
55‧‧‧側壁
58‧‧‧底部
57‧‧‧側壁
60‧‧‧銲球
100‧‧‧半導體結構

Claims (9)

  1. 一種封裝半導體裝置,該封裝半導體裝置包括一基板,其中該基板包含一接墊;以及一鈍化層配置於該基板上方,其中該鈍化層係局部覆蓋該接墊:一球下金屬層,配置於該基板上方,其中該球下金屬層係與該接墊耦合;一導電凸塊,配置於該球下金屬層之上方,其中該導電凸塊,包含:一柱體,係連接該球下金屬層;一帽體,配置於該柱體的頂部,其中,該帽體包含一底部截面積係大於該柱體的截面積,該帽體之底部距離該鈍化層之上表面具有一間隔,並且該帽體包含一底部寬度係大於該球下金屬層的寬度;以及一銲球,係包覆該導電凸塊。
  2. 如請求項1所述之封裝半導體裝置,其中該銲球係包覆該柱體之側壁及該間隔。
  3. 如請求項1所述之封裝半導體裝置,其中該帽體之頂面係為一曲面,該帽體的中心部分之厚度大於該帽體的邊緣部分之厚度。
  4. 如請求項1所述之封裝半導體裝置,其中該導電凸塊之材質選自於金、銅、鎳、銀或其合金。
  5. 如請求項1所述之封裝半導體裝置,其中該球下金屬層之材質選自為鈦/銅、鈦/鎢/金或含銀合金。
  6. 一種封裝半導體裝置,該封裝半導體裝置包括一基板,其中該基板包含一接墊;以及一鈍化層配置於該基板上方並暴露出該接墊之部份: 一重佈層配置於該鈍化層上,並與該接墊之該部份耦合;一保護層配置於該重佈層上,並且暴露出該重佈層之部分;一球下金屬層配置於該保護層上,其中該球下金屬層係與該該重佈層之該部分耦合;一導電凸塊,配置於該球下金屬層之上方,其中該導電凸塊,包含:一柱體,係連接該球下金屬層;一帽體,配置於該柱體的頂部,其中,該帽體包含一底部截面積係大於該柱體的截面積,且該帽體之底部距離該保護層之上表面具有一間隔;以及一銲球,係包覆該導電凸塊。
  7. 如請求項6所述之封裝半導體裝置,其中該帽體包含一底部寬度係大於該球下金屬層的寬度。
  8. 如請求項6所述之封裝半導體裝置,其中該銲球係包覆該柱體之側壁及該間距。
  9. 如請求項6所述之封裝半導體裝置,其中該導電凸塊之材質選自於金、銅、鎳、銀或其合金。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9960135B2 (en) * 2015-03-23 2018-05-01 Texas Instruments Incorporated Metal bond pad with cobalt interconnect layer and solder thereon
KR102601553B1 (ko) * 2016-12-08 2023-11-15 삼성전자주식회사 반도체 발광 소자
JP6680705B2 (ja) * 2017-02-10 2020-04-15 キオクシア株式会社 半導体装置及びその製造方法
TWI613768B (zh) * 2017-03-20 2018-02-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10297561B1 (en) 2017-12-22 2019-05-21 Micron Technology, Inc. Interconnect structures for preventing solder bridging, and associated systems and methods
US11133278B2 (en) * 2018-10-05 2021-09-28 Advanced Semiconductor Engineering, Inc. Semiconductor package including cap layer and dam structure and method of manufacturing the same
KR102617086B1 (ko) 2018-11-15 2023-12-26 삼성전자주식회사 Ubm을 포함하는 웨이퍼-레벨 반도체 패키지
TWI678743B (zh) * 2018-12-10 2019-12-01 南茂科技股份有限公司 半導體線路結構及其製作方法
US10811347B2 (en) * 2018-12-27 2020-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201143002A (en) * 2010-05-20 2011-12-01 Taiwan Semiconductor Mfg Semiconductor structure and method of forming semiconductor device
TW201208024A (en) * 2010-07-08 2012-02-16 Tessera Inc Microelectronic packages with dual or multiple-etched flip-chip connectors

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6871396B2 (en) * 2000-02-09 2005-03-29 Matsushita Electric Industrial Co., Ltd. Transfer material for wiring substrate
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
TWI281718B (en) * 2002-09-10 2007-05-21 Advanced Semiconductor Eng Bump and process thereof
US20050012225A1 (en) * 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
JP2004235420A (ja) * 2003-01-30 2004-08-19 Seiko Epson Corp 電子素子、電子素子の製造方法、回路基板、回路基板の製造方法、電子装置及び電子装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201143002A (en) * 2010-05-20 2011-12-01 Taiwan Semiconductor Mfg Semiconductor structure and method of forming semiconductor device
TW201208024A (en) * 2010-07-08 2012-02-16 Tessera Inc Microelectronic packages with dual or multiple-etched flip-chip connectors

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