JP6015240B2 - 端子構造及び半導体素子 - Google Patents
端子構造及び半導体素子 Download PDFInfo
- Publication number
- JP6015240B2 JP6015240B2 JP2012185042A JP2012185042A JP6015240B2 JP 6015240 B2 JP6015240 B2 JP 6015240B2 JP 2012185042 A JP2012185042 A JP 2012185042A JP 2012185042 A JP2012185042 A JP 2012185042A JP 6015240 B2 JP6015240 B2 JP 6015240B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- layer
- terminal structure
- tin
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemically Coating (AREA)
Description
図2は、本実施形態に係る端子構造の好適な形成工程を模式的に示す断面図である。まず、図2(a)に示すように、公知の工法を用いて、基材10上に外部電極20、及び外部電極上に開口を有する絶縁性被覆層30をそれぞれ形成する。なお、外部電極の厚み、外部電極のピッチPe(配置間隔)及び絶縁性被覆層の厚みは特に限定されるものではないが、これらの層形成の実施容易性とバンプの狭ピッチ化とを両立させるためには、それぞれ、1〜30μm、10〜150μm及び0.1〜50μmであることが好ましい。一方、開口の直径Lo及び隣接する開口の間隔Poは、外部電極とバンプとの電気的接続性、及び隣接するバンプ間の電気的絶縁性を向上する観点から、それぞれ3〜30μm及び5〜120μmであることが好ましい。なお、基材としては、シリコン基板、有機基板等が、外部電極としては、Cu、Cu合金、Al、Al合金等からなるものがそれぞれ好ましい態様として挙げられる。また、絶縁性被覆層は、例えば、基材表面及び外部電極表面を水分による腐食等から保護することができれば特に制限はされないが、ポリイミド、SiN等からなるものが挙げられる。
無電解ニッケルめっきは、ニッケル塩、錯化剤、還元剤を含むめっき液を用いることができる。無電解ニッケルめっきの作業性(浴安定性、析出速度)を良好にする観点から、還元剤として次亜リン酸を含むめっき液を用いることが好ましい。
電解ニッケルめっきは、例えば、公知のワット浴やスルファミン酸浴を用いることができる。ニッケルめっき被膜の柔軟性、低応力を得る観点から、スルファミン酸浴を用いることが好ましい。
還元型無電解スズめっきは、スズ化合物、有機錯化剤、有機イオウ化合物、酸化防止剤、及び還元剤として3価チタン化合物を含むめっき液を用いることが好ましい。これら構成成分の種類、濃度を好適に選択することで、UBM層上に安定的にスズを析出することが可能である。以下その詳細を示すが、種類、濃度、またそのメカニズムは記載したものに限定されない。
このようにして作製される端子構造は、半導体素子等に好適に適用することができる。例えば、半導体素子の場合、基材10としては、シリコン基板等の表面ないしは内部に半導体回路が形成されたものを適用することができる。また、外部電極20としては、半導体回路と電気的に接続されたものを適用することができる。このような半導体素子であれば、隣接するバンプ間隔が狭く、かつバンプ間隔を狭くしたとしても実装時にフィラーや樹脂等を充てんしやすいことから、半導体デバイスの微細化に対する要求に十分に対応することが可能である。
(基板の準備)
図2(a)に示すような、外部電極及び開口を有するSiN絶縁性被覆層が形成されたシリコン基板(5×5mm、厚み0.6mm)を準備した。なお、外部電極は銅で形成し、開口を互いに等間隔で10×10(個)となるように配置した。また、後述するヒートサイクル試験での導通性確認のため、実装時にデイジー回路を形成するように外部電極を予め配線するように作製した。
次に、SiN絶縁性被覆層の開口に露出した銅外部電極表面に対し、所定の前処理(脱脂、酸洗、活性化処理)を行った後、無電解ニッケルめっきを行い、開口を充てんしかつSiN絶縁性被覆層の一部を覆うUBM層を形成した(図2(b))。なお、無電解ニッケルめっきは公知の無電解ニッケル−リンめっき液(UBM層中リン濃度:10質量%)を用いた。また、めっき条件は、温度を85℃とし、時間は所定のニッケルめっき層厚みが得られるように調整した。
さらに、還元型無電解スズめっきを行い、上記のとおり形成されたUBM層全体を内包するようにして、UBM層及びSiN絶縁性被覆層の一部を覆うスズめっき層が形成された前駆体基板を得た(図2(c))。なお、還元型無電解スズめっき液の組成は、以下のとおりであった。また、めっき条件は、温度を60℃とし、時間は所定のスズめっき層高さが得られるように調整した。
スズ化合物(塩化第一スズ):10g/L(スズとして)
含リン有機錯化剤(水酸基含有ホスホン酸):100g/L
有機イオウ化合物(スルフィド基含有有機イオウ化合物):100ppm
酸化防止剤(亜リン酸化合物):40g/L
還元剤(三塩化チタン):5g/L(チタンとして)
このようにして得られた前駆体基板を、窒素雰囲気中(酸素濃度500ppm)にて、250℃で30秒間保持してスズめっき層を溶融し、さらにこれを急冷して凝固させることで、図2(d)に示すようなドーム状のスズバンプを有する端子構造を備えるシリコンTEG(Test Element Group)基板を得た。なお、各構成部分における厚み、ピッチ等は表1に示すとおりであった。
各構成の厚み、ピッチ等を表1のように変更したこと以外は、実施例1と同様にして端子構造を備えるシリコンTEG基板を得た。
無電解ニッケルめっきの代わりに、電解ニッケルめっきを行ったこと以外は、実施例1と同様にして端子構造を備えるシリコンTEG基板を得た。
外部電極をAl−0.5質量%Cu合金で形成し、また、外部電極表面に対し所定の前処理(脱脂、酸洗、ジンケート処理)を行ったこと以外は、実施例1と同様にして端子構造を備えるシリコンTEG基板を得た。
外部電極をAl−0.5質量%Cu合金で形成し、また、外部電極表面に対し所定の前処理(脱脂、酸洗、ジンケート処理)を行ったこと以外は、実施例4と同様にして端子構造を備えるシリコンTEG基板を得た。
還元型無電解スズめっきの代わりに、電解はんだめっきを行ったこと以外は、実施例7と同様にして端子構造を備えるシリコンTEG基板を得た。ただし、比較例3のみはドライフィルムを形成することができなかったため、端子構造を作製することはできなかった。そのため、後述する評価及び試験を行わなかった。
実施例及び比較例で得られた端子構造について、以下のようにしてバンプ形成性評価を行った。具体的には、10×10(個)の合計100個のバンプについて、隣接するバンプ同士が独立に形成されているか、を光学顕微鏡を用いて確認した。隣接するバンプ同士が独立して形成されておりショートしていなかったものをA評価、隣接するバンプ同士が一対でもショートしていたものをB評価とした。結果を表2に示す。なお、比較例2についてはショートが確認されたため、表1で示したバンプについての計測はおこなわなかった。
実施例及び比較例で得られた端子構造について、以下のようにしてヒートサイクル試験を行った。具体的には、デイジー回路を形成する二枚一対のシリコンTEG基板のバンプ(10×10(個))を、フリップチップ実装機によりFace to Faceで接合することでヒートサイクル試験試料を作製した。そして、−40℃〜120℃のヒートサイクルを1000サイクル加えながら、各試料のデイジー回路の導通性をモニターすることで評価を行った。ヒートサイクル試験後(1000サイクル後)も導通が確保されていたものをA評価、途中でデイジー回路が断絶したものをB評価とした。なお、隣接するバンプ同士がショートしていた比較例2については、ヒートサイクル試験を行わなかった。結果を表2に示す。
Claims (6)
- 基材と、
前記基材上に形成された電極と、
前記基材上及び前記電極上に形成され、前記電極の少なくとも一部を露出させる開口を有する絶縁性被覆層と、
該開口を充てんしかつ前記絶縁性被覆層の一部を覆うアンダーバンプ金属層と、
該アンダーバンプ金属層全体を内包するように、該アンダーバンプ金属層及び前記絶縁性被覆層の一部を覆うドーム状のバンプと、を備え、
積層方向に沿った断面において、前記バンプの最大径をとる高さが、前記アンダーバンプ金属層の最大高さよりも低い、
端子構造。 - 前記バンプの最大径が5〜40μmである、請求項1記載の端子構造。
- 前記バンプが主成分としてスズを含有する、請求項1又は2記載の端子構造。
- 前記アンダーバンプ金属層が主成分としてニッケルを含有する、請求項1〜3のいずれか一項記載の端子構造。
- 前記バンプがチタンを含有する、請求項1〜4のいずれか一項記載の端子構造。
- 請求項1〜5のいずれか一項記載の端子構造を備える半導体素子。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012185042A JP6015240B2 (ja) | 2012-08-24 | 2012-08-24 | 端子構造及び半導体素子 |
US13/960,228 US9070606B2 (en) | 2012-08-24 | 2013-08-06 | Terminal structure and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012185042A JP6015240B2 (ja) | 2012-08-24 | 2012-08-24 | 端子構造及び半導体素子 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014044986A JP2014044986A (ja) | 2014-03-13 |
JP6015240B2 true JP6015240B2 (ja) | 2016-10-26 |
Family
ID=50147290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012185042A Active JP6015240B2 (ja) | 2012-08-24 | 2012-08-24 | 端子構造及び半導体素子 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9070606B2 (ja) |
JP (1) | JP6015240B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016076533A (ja) * | 2014-10-03 | 2016-05-12 | イビデン株式会社 | バンプ付きプリント配線板およびその製造方法 |
US20170372998A1 (en) * | 2016-06-27 | 2017-12-28 | Yenhao Benjamin Chen | Sheet molding process for wafer level packaging |
KR101926713B1 (ko) | 2016-07-18 | 2018-12-07 | 엘비세미콘 주식회사 | 반도체 패키지 및 그 제조방법 |
JP6680705B2 (ja) * | 2017-02-10 | 2020-04-15 | キオクシア株式会社 | 半導体装置及びその製造方法 |
US11127704B2 (en) * | 2017-11-28 | 2021-09-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with bump structure and method of making semiconductor device |
CN115312408A (zh) * | 2021-05-04 | 2022-11-08 | Iqm 芬兰有限公司 | 用于竖直互连的电镀 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4205099A (en) | 1978-04-14 | 1980-05-27 | Sprague Electric Company | Method for making terminal bumps on semiconductor wafers |
JP2763020B2 (ja) | 1995-04-27 | 1998-06-11 | 日本電気株式会社 | 半導体パッケージ及び半導体装置 |
JPH09129647A (ja) | 1995-10-27 | 1997-05-16 | Toshiba Corp | 半導体素子 |
JP4462664B2 (ja) * | 1998-11-27 | 2010-05-12 | 三洋電機株式会社 | チップサイズパッケージ型の半導体装置 |
JP4564113B2 (ja) | 1998-11-30 | 2010-10-20 | 株式会社東芝 | 微粒子膜形成方法 |
JP2001085456A (ja) | 1999-09-10 | 2001-03-30 | Seiko Epson Corp | バンプ形成方法 |
KR100319813B1 (ko) * | 2000-01-03 | 2002-01-09 | 윤종용 | 유비엠 언더컷을 개선한 솔더 범프의 형성 방법 |
US6348399B1 (en) | 2000-07-06 | 2002-02-19 | Advanced Semiconductor Engineering, Inc. | Method of making chip scale package |
JP3682227B2 (ja) | 2000-12-27 | 2005-08-10 | 株式会社東芝 | 電極の形成方法 |
JP4656275B2 (ja) | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2002299366A (ja) | 2001-04-02 | 2002-10-11 | Hitachi Ltd | 半導体装置およびその製造方法 |
TW531873B (en) | 2001-06-12 | 2003-05-11 | Advanced Interconnect Tech Ltd | Barrier cap for under bump metal |
TWI239578B (en) | 2002-02-21 | 2005-09-11 | Advanced Semiconductor Eng | Manufacturing process of bump |
JP4267549B2 (ja) * | 2004-09-22 | 2009-05-27 | 株式会社フジクラ | 半導体装置およびその製造方法ならびに電子機器 |
TWI296843B (en) | 2006-04-19 | 2008-05-11 | Phoenix Prec Technology Corp | A method for manufacturing a coreless package substrate |
US20090174052A1 (en) | 2006-05-29 | 2009-07-09 | Nec Corporation | Electronic component, semiconductor package, and electronic device |
JP4980709B2 (ja) | 2006-12-25 | 2012-07-18 | ローム株式会社 | 半導体装置 |
TWI331797B (en) | 2007-04-18 | 2010-10-11 | Unimicron Technology Corp | Surface structure of a packaging substrate and a fabricating method thereof |
US7868453B2 (en) * | 2008-02-15 | 2011-01-11 | International Business Machines Corporation | Solder interconnect pads with current spreading layers |
US7952203B2 (en) * | 2008-08-29 | 2011-05-31 | Intel Corporation | Methods of forming C4 round dimple metal stud bumps for fine pitch packaging applications and structures formed thereby |
US8493746B2 (en) | 2009-02-12 | 2013-07-23 | International Business Machines Corporation | Additives for grain fragmentation in Pb-free Sn-based solder |
JP2011044496A (ja) * | 2009-08-19 | 2011-03-03 | Panasonic Corp | 半導体デバイス及びそれを用いた半導体装置 |
KR20110139983A (ko) * | 2010-06-24 | 2011-12-30 | 삼성전자주식회사 | 반도체 패키지 |
EP2629323A1 (en) | 2010-10-12 | 2013-08-21 | Kabushiki Kaisha Yaskawa Denki | Electronic device and electronic component |
US8409979B2 (en) * | 2011-05-31 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties |
JP6015239B2 (ja) * | 2012-08-24 | 2016-10-26 | Tdk株式会社 | 端子構造、並びにこれを備える半導体素子及びモジュール基板 |
-
2012
- 2012-08-24 JP JP2012185042A patent/JP6015240B2/ja active Active
-
2013
- 2013-08-06 US US13/960,228 patent/US9070606B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2014044986A (ja) | 2014-03-13 |
US20140054768A1 (en) | 2014-02-27 |
US9070606B2 (en) | 2015-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8970037B2 (en) | Terminal structure, and semiconductor element and module substrate comprising the same | |
JP6015240B2 (ja) | 端子構造及び半導体素子 | |
JP6326723B2 (ja) | 端子構造及び半導体素子 | |
US9257402B2 (en) | Terminal structure, and semiconductor element and module substrate comprising the same | |
CN102201351B (zh) | 半导体器件和形成用于无铅凸块连接的双ubm结构的方法 | |
US9177827B2 (en) | Etchant and method for manufacturing semiconductor device using same | |
US7800240B2 (en) | Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure | |
US20140361431A1 (en) | Semiconductor device and manufacturing method thereof | |
CN107507820B (zh) | 半导体器件及制造该半导体器件的方法 | |
TW201123388A (en) | Printed circuit board for semiconductor package and method of manufacturing the same | |
US20120164854A1 (en) | Packaging substrate and method of fabricating the same | |
CN111199946A (zh) | 铜柱凸点结构及其制造方法 | |
JP6485098B2 (ja) | 電子デバイス及びその製造方法 | |
CN103290440B (zh) | 金凸点形成用非氰系电解镀金浴及金凸点形成方法 | |
JP2004047510A (ja) | 電極構造体およびその形成方法 | |
CN101908516B (zh) | 倒装芯片锡银凸块结构及其制造方法 | |
JP2001352005A (ja) | 配線基板および半導体装置 | |
JP3308882B2 (ja) | 半導体装置の電極構造の製造方法 | |
KR101167815B1 (ko) | 반도체 패키지 구조 및 이의 제조 방법 | |
KR20150040577A (ko) | 패키지 기판 | |
JP2004193211A (ja) | 電子部品およびその製造方法 | |
JP2016082124A (ja) | バンプ電極、バンプ電極の製造方法 | |
TW201133664A (en) | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch | |
JPH021127A (ja) | バンプの形成方法 | |
JP2012038752A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150623 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160415 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160524 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160712 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160830 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160912 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6015240 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |