CN103325819B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN103325819B
CN103325819B CN201310053001.8A CN201310053001A CN103325819B CN 103325819 B CN103325819 B CN 103325819B CN 201310053001 A CN201310053001 A CN 201310053001A CN 103325819 B CN103325819 B CN 103325819B
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equal
interlayer dielectric
ratio
peak height
salient pole
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CN103325819A (zh
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宇佐美达矢
中村朝至
藤本直树
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明提供一种半导体器件，所述半导体器件包括：含有Si、O、C和H的层间绝缘膜；设置在所述层间绝缘膜上的且含有Ni的凸块下金属膜；以及设置在所述凸块下金属膜之上的凸块电极。在所述层间绝缘膜中，波数1270cm‑1附近的Si‑CH3的峰高与波数1030cm‑1附近的Si‑O的峰高的比值为大于等于0.15且小于等于0.27。波数1360cm‑1附近的Si‑CH2‑Si的峰高与波数1270cm‑1附近的Si‑CH3的峰高的比值大于等于0.031，所述比值通过傅里叶变换红外光谱FTIR获得。

Description

半导体器件及其制造方法
相关申请的交叉引用
2012年3月23日提交的日本专利申请第2012-066739号的全部内容（包括说明书、附图和摘要）通过引用并入本文。
技术领域
本发明涉及半导体器件及其制造方法。
背景技术
为了改善半导体器件的可靠性，近年来已提出了各种不同的半导体器件结构。
日本待审查专利申请公开（PCT申请的译文）第2008-530821号公开了一种用作如下所述的半导体器件的层间绝缘膜的电介质材料。所述电介质材料含有Si、C、O和H原子并且具有三维网络结构。通过傅里叶变换红外光谱（FTIR）得到的与CH2或CH3的扩展或收缩、SiH的扩展或收缩以及SiCH3化学键有关的峰面积落入通过电介质膜的厚度标准化的预定范围内。电介质材料的孔隙度超过20%。基于这个原因，人们认为可以提供表现出良好的电学和机械性能的低介电常数电介质膜。
日本待审查专利公开第2006-237278号公开了一种半导体器件，所述半导体器件包括如下所述的凸块电极。所述半导体器件包括焊盘电极、凸块下金属膜和Au凸块电极。凸块下金属膜包括TiW膜和Au膜。凸块下金属膜的TiW膜和Au膜的厚度符合预定公式。基于这个原因，人们认为可以控制倒装芯片接合步骤中凸块下金属膜中裂痕的发生率。
发明内容
施加于电极的应力可导致在电极下方的层间绝缘膜中产生诸如裂痕之类的缺陷。人们认为需要一种抵抗施加于电极的应力的且具有高强度的层间绝缘膜来解决这个问题。本发明的其他问题和新的特征通过本发明的具体实施方式和附图来进一步说明。
根据本发明的第一方面的半导体器件包括含有Si、O、C和H的层间绝缘膜，设置于所述层间绝缘膜上方的含有Ni的凸块下金属膜和设置于所述凸块下金属膜上方的凸块电极。在所述层间绝缘膜中，波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.15且小于等于0.27。波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值为大于等于0.031。所述比值通过FTIR得到。
根据本发明的第二方面的用于制造半导体器件的方法包括如下步骤：形成含有Si、O、C和H的层间绝缘膜（层间绝缘膜形成步骤），形成位于所述层间绝缘膜上方的含有Ni的凸块下金属膜，和形成位于所述凸块下金属膜上方的凸块电极。在所述层间绝缘膜形成步骤中，波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.15且小于等于0.27，并且波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值为大于等于0.031。所述比值通过FTIR得到。
根据本发明的第一方面，半导体器件可设置成包括具有较高强度的层间绝缘膜。
附图说明
图1为表示根据第一实施方式的半导体器件的结构的横截面图。
图2为图1的A部分的放大横截面图。
图3为表示根据第一实施方式的半导体器件的结构的横截面图。
图4为表示凸块下金属膜的厚度与电迁移寿命之间关系的图；
图5为表示在大于等于2700cm-1且小于等于3100cm-1的波数范围内SiCOH膜的FTIR光谱图的曲线图；
图6为表示在大于等于1240cm-1且小于等于1300cm-1的波数范围内SiCOH膜的FTIR光谱图的曲线图；
图7为表示在大于等于1345cm-1且小于等于1380cm-1的波数范围内SiCOH膜的FTIR光谱图的曲线图；
图8为表示当Si-CH3/Si-O的比值大于等于0.15且小于等于0.27时Si-CH2-Si/Si-CH3的比值与SiCOH膜的击穿电压之间关系的图；
图9A和图9B为表示SiCOH膜中的化学键的示意图；
图10为表示当Si-CH3/Si-O比值大于等于0.16且小于等于0.24时Si-CH2-Si/Si-CH3比值与击穿电压之间关系的图；以及
图11为表示凸块下金属膜的厚度与层间绝缘膜中出现的缺陷的发生率之间关系的图。
具体实施方式
现在，结合附图对本发明的实施方式进行描述。类似的部件在附图中标记相同的附图标记，并且适当地省略对其的描述。
第一实施方式
参考图1至图3，对根据第一实施方式的半导体器件SD的结构进行描述。半导体器件SD包括：含有Si、O、C和H的层间绝缘膜IL1；设置于所述层间绝缘膜IL1上方的且含有Ni的凸块下金属膜UBM，和设置于所述凸块下金属膜UBM上方的凸块电极BE。在层间绝缘膜IL1中，波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.15且小于等于0.27。波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值大于等于0.031。这些比值通过傅里叶变换红外光谱（FTIR）得到。下面进行详细描述。
图1和图3为表示根据第一实施方式的半导体器件SD的结构的横截面图。图1表示通过划片得到的半导体芯片SC的一部分。图2为图1的A部分的放大横截面图。图3表示被封装的半导体器件SD。
如图2所示，半导体衬底SUB具有元件隔离区DIR，每个元件隔离区具有孔隙（无附图标记）。例如，如后面将要描述的，在每个孔隙中形成金属绝缘半导体场效应晶体管（MISFET）。
例如，半导体衬底SUB为硅衬底。元件隔离区DIR由例如SiO2形成。尽管在本文中元件隔离区例如通过硅局部氧化（LOCOS）形成，但是，该元件隔离区可通过浅槽隔离（STI）形成。
半导体衬底SUB还具有位于俯视图中被分离的位置的源区SR和漏区DR。源极侧扩展区ER被形成为与源区SR接触；漏极侧扩展区ER被形成为与漏区DR接触。
栅极绝缘层GI设置在扩展区ER之间的区域上。栅极绝缘层GI由例如SiO2或SiON形成。可选地，栅极绝缘层GI可为例如含有Hf的具有高介电常数的膜。
栅电极GE设置于栅极绝缘层GI上。栅电极GE由例如多晶硅形成。可选地，栅电极GE可由例如Ti、Ta、Mo、这些金属的合金、这些金属的氮化物或者这些金属和硅的氮化物形成。
侧壁绝缘膜SWI围绕栅极绝缘层GI和栅电极GE的侧壁设置。此外，衬垫绝缘膜（未显示）可设置在半导体衬底SUB、栅电极GE和侧壁绝缘膜SWI上方。
如图2所示，下层绝缘膜ILU设置在半导体衬底SUB、元件隔离区DIR和栅电极GE上方。下层绝缘膜ILU可由不同于层间绝缘膜IL1（将在下面讨论）的材料形成。
下层绝缘膜ILU设置有例如与源区SR或漏区DR接触的接触塞VAU。进一步地，在未显示的区域中，下层绝缘膜ILU设置有与栅电极GE接触的接触塞VAU。例如，接触塞VAU含有钨（W）。接触塞VAU的侧面和底面设置有阻挡金属层（未显示）。
层间绝缘膜IL1设置在下层绝缘膜ILU上方。例如，层间绝缘膜IL1为SiCOH膜。层间绝缘膜IL1设置有例如通过单镶嵌安装的布线ICU。布线ICU通过接触塞VAU与源区SR、漏区DR或栅电极GE连接。布线ICU含有铜（Cu）。
多个层间绝缘膜IL1进一步设置在层间绝缘膜IL1上方。上层绝缘膜IL1设置有例如通过双镶嵌安装的布线IC1和通孔VA。布线IC1和通孔VA含有Cu。布线IC1和通孔VA的侧面和底面可设置有阻挡金属层（未显示）。
如图1所示，多层布线层在半导体衬底SUB的上方形成。所述多层布线层包括局部布线层LL和全局布线层GL。局部布线层LL为用于形成电路的布线层，全局布线层GL为用于安排供电布线和接地布线的路径的布线层。
局部布线层LL包括层间绝缘膜IL1。层间绝缘膜IL1在下面详细描述。局部布线层LL的层间绝缘膜IL1设置有布线IC1或通孔（未显示）。
抑制扩散层BL1可设置在局部布线层LL的布线层中。抑制扩散层BL1由例如SiCN、SiC、SiON、SiCO、SiCON或SiN形成。
全局布线层GL设置在局部布线层LL上。全局布线层GL包括层间绝缘膜IL2。层间绝缘膜IL2由例如密度比层间绝缘膜IL1的密度高的材料形成。例如，层间绝缘膜IL2由SiO2或SiOF形成。
全局布线层GL的层间绝缘膜IL2设置有布线IC2或通孔（未显示）。布线IC2通过例如通孔与局部布线层LL的布线IC1连接。抑制扩散层BL2可设置在全局布线层GL的布线层中。
在全局布线层GL中，至少位于最上层下方的布线IC2或通孔通过镶嵌形成。布线IC2和通孔含有Cu。
与电极（BE，等）接触的金属膜CML设置在全局布线层GL的最上层中。金属膜CML用作凸块电极BE的基底。金属膜CML含有例如Al。金属膜CML通过通孔与其下方的布线IC2连接。
保护层CPL设置在全局布线层GL上方。保护层CPL由例如聚酰亚胺形成。保护层CPL具有在俯视图中位于与金属膜CML重叠的位置的孔隙（无附图标记）。
所述孔隙设置有凸块下金属膜UBM。凸块下金属膜UBM由用于控制形成凸块电极BE的材料的迁移的材料形成。具体而言，凸块下金属膜UBM由例如Ni形成。
凸块电极BE设置在凸块下金属膜UBM上方。凸块电极BE由无Pb焊接材料形成。例如，凸块电极BE含有Sn和Ag。凸块电极BE的高度为大于等于50μm且小于等于100μm。由于凸块电极BE的上述结构，半导体芯片SC可稳定地以倒装法安装在电路基板IP上方。施加于位于凸块电极BE下方的层间绝缘膜IL1的应力取决于形成凸块电极BE的材料或凸块电极BE的高度（或体积）。假设凸块电极BE至少具有上述组成，本发明的发明人已确定：如果层间绝缘膜IL1含有下面讨论的组成，那么可控制在层间绝缘膜IL1中的缺陷的发生率。凸块电极BE的结构不限于上面所讨论的。即使凸块电极具有其他结构，也可获得与第一实施方式类似的优势。
如图3所示，半导体器件SD为例如，球栅阵列（BGA）封装。半导体芯片SC通过例如倒装安装法安装在电路基板IP上。将底部填充树脂UDF注入半导体芯片SC和电路基板IP之间。
具有凹槽的盖子LID设置在电路基板IP和半导体芯片SC上方。盖子LID的边缘与电路基板IP接触。盖子LID的凹槽的内表面与半导体芯片SC的顶面接触。使用粘合剂（未显示）将盖子LID固定至电路基板IP和半导体芯片SC。焊球SLB设置在电路基板IP的底面下方。
半导体器件SD的封装不需要一定为BGA型，可为其他类型。
参考图4，描述凸块下金属膜UBM的厚度。图4为表示凸块下金属膜UBM的厚度与电迁移寿命之间关系的图。图4表示在预定的条件下，在多个半导体器件SD上进行的电迁移测试的结果，所述多个半导体芯片包括具有不同厚度的凸块下金属膜UBM。
图4的横轴表示含有Ni的凸块下金属膜UBM的厚度。图4的纵轴表示当由于电迁移而产生缺陷的样品数占各个所测试半导体器件SD的总样品数的50%时的时间（T50，以任意单位计）。粗虚线表示用于预定产品的可靠性标准。
如图4所示，当凸块下金属膜UBM的厚度增加时，电迁移寿命（T50）趋于增加。在厚度较小的凸块下金属膜UBM中，形成凸块下金属膜UBM的材料在测试过程中易于迁移。因此，在凸块下金属膜UBM中产生裂缝。因此，厚度较小的凸块下金属膜UBM具有较短的电迁移寿命。相反，厚度较大的凸块下金属膜UBM的体积比厚度较小时大。因此，与出现裂缝有关的阻抗变化较小。厚度较大的凸块下金属膜UBM具有较长的电迁移寿命。
在第一实施方式中，凸块下金属膜UBM的厚度为例如，大于等于1.5μm且小于等于3.0μm。如果凸块下金属膜UBM的厚度大于等于1.5μm，那么电迁移寿命可与预定产品的可靠性标准相同或更长。如果凸块下金属膜UBM的厚度小于等于3.0μm，那么凸块电极BE和凸块电极BE下方的金属膜CML之间的接触阻抗可降低。
另一方面，本发明的发明人已发现当凸块下金属膜UBM的厚度较大时，施加于凸块电极BE的应力导致凸块电极BE下的层间绝缘膜IL1中产生如下所述的缺陷。凸块下金属膜UBM由比凸块电极BE更硬的材料形成。例如，当应力在安装过程中或安装之后施加于凸块电极BE时，凸块下金属膜UBM没有释放应力。因此，应力也被施加于层间绝缘膜IL1。这时，诸如裂缝之类的缺陷可在凸块电极BE下的层间绝缘膜IL1中产生。
例如，如果层间绝缘膜IL1具有较低的强度，即使凸块下金属膜UBM的厚度大于等于1.5μm，也可出现裂缝。而且，随着凸块下金属膜UBM的厚度增加，在层间绝缘膜IL1中缺陷的发生率趋于增加。
如上所述，既控制形成凸块电极BE的材料的迁移又控制层间绝缘膜IL1中缺陷的发生率是较为困难的。
鉴于上述内容，在根据第一实施方式的层间绝缘膜IL1中，Si-CH3/Si-O的比值和Si-CH2-Si/Si-CH3的比值分别落入预定范围内。这些比值通过FTIR得到并且会在后面描述。因此，可获得具有较高强度的层间绝缘膜。而且，即使当凸块下金属膜UBM的厚度为大于等于1.5μm且小于等于3.0μm时，也可降低由于施加于凸块电极BE的应力而在凸块电极BE下的层间绝缘膜中产生的诸如裂缝之类的缺陷的发生率。
接下来，详细描述根据第一实施方式的层间绝缘膜IL1的特征。层间绝缘膜IL1含有硅（Si）、氧（O）、碳（C）和氢（H）。层间绝缘膜IL1不是多孔膜。下文中，用作层间绝缘膜IL1的膜可称为“SiCOH膜”。
在第一实施方式中，用作层间绝缘膜IL1的SiCOH的相对介电常数为大于等于2.5且小于等于3.2。因此，可降低线间电容。
为了得到具有上述相对介电常数的SiCOH膜，层间绝缘膜IL1需要具有不少于预定的碳原子（C）含量。本发明的发明人已发现，符合上述相对介电常数的SiCOH膜具有如下所述FTIR光谱特征。具体而言，通过FTIR得到的波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值（Si-CH3/Si-O的比值）为大于等于0.15且小于等于0.27。因此，可得到相对介电常数大于等于2.5且小于等于3.2的层间绝缘膜IL1。
进一步地，通过FTIR光谱，本发明的发明人已发现可在如下所述的范围内获得具有较高强度（下面讨论击穿电压）的SiCOH膜。具体而言，通过FTIR得到的波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值（Si-CH2-Si/Si-CH3的比值）大于等于0.031。下面进行详细描述。
在下面对相对介电常数为大于等于2.5且小于等于3.2的SiCOH膜的描述中，具有较低强度的膜称为“对比实施例”，具有较高强度的膜称为“第一实施方式”。
图5至图7显示了在单层SiCOH膜上进行的FTIR测量的结果。图5为表示在大于等于2700cm-1且小于等于3100cm-1的波数范围内SiCOH膜的FTIR光谱图。如图5所示，由CH2或CH3产生的峰出现在波数2950cm-1附近。在该图中，第一实施方式的CH2或CH3的峰形与对比实施例中的峰形基本相同。
图6为表示在大于等于1240cm-1且小于等于1300cm-1的波数范围内SiCOH膜的FTIR光谱图的曲线图。如图6所示，由Si-CH3产生的峰出现在波数1270cm-1附近。在该图中，第一实施方式的Si-CH3的峰形与对比实施例的峰形基本相同。
图7表示在大于等于1345cm-1且小于等于1380cm-1的波数范围内SiCOH膜的FTIR光谱图的曲线图。如图7所示，由Si-CH2-Si产生的峰出现在波数1360cm-1附近。
由Si-CH2-Si产生的波数1360cm-1附近的峰没有在上述日本待审查专利公开（PCT申请的译文）第2008-530821中公开的介电膜中出现（参见，例如，上述专利公开的图7）。
对于Si-CH2-Si峰而言，第一实施方式与对比实施例之间具有明显区别。第一实施方式的Si-CH2-Si的峰高高于对比实施例的峰高。本发明的发明人发现Si-CH2-Si的峰高与SiCOH膜的强度有关。
图8为表示当Si-CH3/Si-O的比值为大于等于0.15且小于等于0.27时Si-CH2-Si/Si-CH3的比值与SiCOH膜的击穿电压之间关系的图。
图8的横轴表示通过FTIR获得的波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值（Si-CH2-Si/Si-CH3的比值）。该峰高比值由已消除背景的FTIR检测光谱得到。应当注意的是，所述比值不是峰面积比值。标出的点的值代表这些点处的Si-CH2-Si/Si-CH3的值。
图8的纵轴表示由纳米压痕测量的SiCOH膜的击穿电压Kc（单位为MPam1/2）。使用纳米压痕测量击穿电压Kc。在测量中使用单层SiCOH膜。
击穿电压Kc（单位为MPam1/2）可由下面的方程式（1）得到：
[方程式1]
在方程式（1）中，α代表纳米压痕的常数并且为Berkovich压痕0.016；E代表SiCOH膜的杨氏模量；H代表SiCOH的硬度；P代表纳米压痕的最大负载；c代表使用纳米压痕压出的在SiCOH膜中出现的裂缝的长度。
图5至图7中的对比实施例所示的SiCOH膜为图8中Si-CH2-Si/Si-CH3比值小于0.031的膜中的一种。另一方面，第一实施方式所示的SiCOH膜为Si-CH2-Si/Si-CH3的比值大于等于0.031的膜中的一种。
如图8所示，当Si-CH2-Si/Si-CH3的比值增加时，SiCOH膜的击穿电压增加。在Si-CH2-Si/Si-CH3的比值达到0.031之后，击穿电压急剧增加。Si-CH2-Si/Si-CH3的比值大于等于0.031时的击穿电压大于Si-CH2-Si/Si-CH3的比值小于0.031时的击穿电压。
参考图9A和图9B，描述击穿电压随Si-CH2-Si/Si-CH3比值增加而增加的机制。图9A和图9B为表示SiCOH膜中的化学键的示意图。图9A表示Si-CH3键合模型。图9B表示Si-CH2-Si键合模型。
在以如图9A所示的Si-CH3化学键为主的SiCOH膜中，例如，由Si原材料产生的甲基与Si连接并且以该甲基为末端。因此，在Si-CH3化学键为主的情况下，Si原子弱键合在SiCOH膜中。
如图9B所示，另一方面，在含有Si-CH2-Si化学键的SiCOH膜中，相邻的Si原子由其之间的CH2交联。因此，得到较强的稳定的SiCOH膜。这就是当Si-CH2-Si/Si-CH3的比值为大于等于0.031时，击穿电压较高的原因。
如上所述，在用作根据第一实施方式的层间绝缘膜IL1的SiCOH膜中，由FTIR获得的Si-CH2-Si/Si-CH3的比值大于等于0.031。因此，可获得具有较高强度的层间绝缘膜IL1。由此，可降低在凸块电极BE下方的层间绝缘膜IL1中出现的诸如裂缝之类的缺陷的发生率。
在半导体器件SD中，至少包括在局部布线层LL中的层间绝缘膜IL1优选地具有上述Si-CH2-Si/Si-CH3比值。包括在全局布线层GL中的层间绝缘膜IL2也可具有上述Si-CH2-Si/Si-CH3比值。
再次参考图1和图3，描述用于制造根据第一实施方式的半导体器件SD的方法。用于制造根据第一实施方式的半导体器件SD的方法包括如下步骤：形成含有Si，O，C和H的层间绝缘膜IL1（层间绝缘膜形成步骤），在层间绝缘膜IL1上方形成含有Ni的凸块下金属膜UBM，在凸块下金属膜UBM上方形成凸块电极BE。在层间绝缘膜形成步骤中，层间绝缘膜IL1以如下方式形成：使波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.15且小于等于0.27，以及使波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值为大于等于0.031。下面将进行详细描述。
首先，如图2所示，在半导体衬底SUB中形成具有孔隙的元件隔离区DIR。随后，在半导体衬底SUB上方形成栅极绝缘层GI和栅极GE。随后，使用栅极绝缘层GI和栅极GE作为掩膜进行离子注入以形成扩展区ER。随后，在栅极绝缘层GI和栅极GE的各个侧壁周围形成侧壁绝缘膜SWI。随后，使用侧壁绝缘膜SWI、栅极绝缘层GI和栅极GE作为掩膜进行离子注入以形成源区SR和漏区DR。
随后，例如，通过化学气相沉积（CVD）法，在半导体衬底SUB、元件隔离区DIR、侧壁绝缘膜SWI和栅电极GE上方形成下层绝缘膜ILU。随后，在下层绝缘膜ILU中形成接触孔（无附图标记）。随后，例如，通过CVD法，在接触孔中和下层绝缘膜ILU方上形成含有W的金属膜。随后，通过化学机械抛光（CMP）法，将下层绝缘膜ILU的顶部平坦化。由此，在下层绝缘膜ILU中形成接触塞VAU。
随后，如图1所示，形成包括布线IC1和通孔的局部布线层。这时，如下所述地（层间绝缘膜形成步骤）形成含有Si、O、C和H的层间绝缘膜。
在层间绝缘膜形成步骤中，例如，通过平行平板型等离子体CVD法，形成SiCOH膜作为层间绝缘膜IL1。Si原材料的实例包括但不限于三甲基硅烷。Si原材料可为四甲基硅烷、四乙基原硅酸盐等等。
层间绝缘膜形成步骤中的膜形成条件优选为低压或大功率。因此，使与Si原材料有关的功率效率增加。这时，Si原材料中的烃基分解，从而形成Si-CH2-Si化学键。因此，在低压或大功率条件下形成层间绝缘膜IL1可促进Si-CH2-Si化学键的形成。
进一步，优选地，Si原材料的流速与总气流流速的比值较高。因此，碳（C）原子被吸收的可能性可增加。此外，半导体衬底SUB可在膜形成过程中被加热。
通过调节层间绝缘膜形成步骤中的条件，使层间绝缘膜IL1在Si-CH3/Si-O的比值为大于等于0.15且小于等于0.27以及Si-CH2-Si/Si-CH3的比值为大于等于0.031的条件下形成。
随后，如图1所示，在层间绝缘膜IL1中形成通孔（未显示）或布线槽（未显示）。随后，在通孔或布线槽的侧面和底面以及层间绝缘膜IL1的上方形成阻挡金属层（未显示）。随后，例如，通过电镀，在所述阻挡金属层上方形成通孔（未显示）或布线IC1。如上所述，布线层通过镶嵌形成。
通过重复与上述内容类似的方法，形成局部布线层LL。抑制扩散层BL1可设置在局部布线层LL的布线层中。
随后，例如，通过CVD法，在局部布线层LL的层间绝缘膜IL1上形成层间绝缘膜IL2。通过镶嵌形成通孔或布线IC2。以这种方式，在局部布线层LL上方形成全局布线层GL。在全局布线层GL的布线层中可形成抑制扩散层BL2。
随后，在全局布线层GL的最上层中形成含有Al的金属膜CML。随后，在全局布线层GL上方形成保护层CPL。随后，在俯视图中的与保护层CPL中的金属膜CML重叠的位置上形成孔隙（无附图标记）。
随后，例如通过溅射，在孔隙处形成凸块下金属膜UBM。这时，形成厚度为例如大于等于1.5μm且小于等于3.0μm的凸块下金属膜UBM。
随后，例如通过电镀，在凸块下金属膜UBM上方形成含有Sn和Ag的凸块电极BE。可选地，可通过印刷形成凸块电极BE。随后，进行回流。因此，形成球形凸块电极BE。随后，将半导体衬底SUB划片成半导体芯片SC。
随后，如图3所示，将半导体芯片SC安装在电路基板IP上方（安装步骤）。在安装步骤中，半导体芯片SC被热压于电路基板IP上。由此，半导体芯片SC的凸块电极BE连接至电路基板IP的末端（未显示）。
随后，将底部填充树脂UDF注入半导体芯片SC和电路基板IP之间。随后，将具有凹槽的盖子LID连接至电路基板IP和半导体芯片SC。随后，在电路基板IP的底面下形成焊球SLB。
以该方式获得根据第一实施方式的半导体器件SD。
现在描述第一实施方式相对于对比实施例的优势。
作为对比实施例，考虑层间绝缘膜IL1的相对介电常数与第一实施方式相同，但是层间绝缘膜IL1的Si-CH2-Si/Si-CH3的比值小于0.031的半导体器件。如上所述，对比实施例具有较低的击穿电压。为此，在对比实施例中，由于例如当在安装步骤中对凸块电极BE进行热压时所施加的负载，可在凸块电极BE下面的层间绝缘膜IL1中出现裂缝。这些裂缝还可在将热应力施加于凸块电极时由于安装之后半导体衬底SUB和电路基板IP之间的热膨胀的差异而产生。
另一方面，在根据第一实施方式的层间绝缘膜IL1中，Si-CH3/Si-O的比值为大于等于0.15且小于等于0.27。Si-CH2-Si/Si-CH3的比值为大于等于0.031。这些比值通过FTIR获得。
因此，如图8所示，当层间绝缘膜IL1的Si-CH2-Si/Si-CH3的比值为大于等于0.031时，可使击穿电压增加。因此，不论凸块下金属膜UBM的厚度，可降低由于施加于凸块电极BE的应力而在层间绝缘膜IL1中出现的诸如裂缝之类的缺陷的发生率。
如上所述，根据第一实施方式，半导体器件SD可设置为包括具有较高强度的层间绝缘膜IL1。
第二实施方式
第二实施方式与第一实施方式类似，除了层间绝缘膜IL1的Si-CH3/Si-O的比值和Si-CH2-Si/Si-CH3的比值分别落在进一步限定的范围内。下面将进行详细描述。
本发明的发明人已发现，当Si-CH3/Si-O的比值和Si-CH2-Si/Si-CH3的比值分别落入进一步限定的范围内时，可获得具有显著较高的强度的层间绝缘膜IL1。具体而言，在层间绝缘膜IL1中，波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.16且小于等于0.24。波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值为大于等于0.033。这些比值通过FTIR获得。下面进行详细描述。
在第二实施方式中应当注意的是，用作层间绝缘膜IL1的SiCOH膜的相对介电常数为大于等于2.9且小于等于3.15。
图10为表示当Si-CH3/Si-O的比值为大于等于0.16且小于0.24时Si-CH2-Si/Si-CH3的比值与击穿电压之间关系的图。如图10所示，Si-CH2-Si/Si-CH3的比值大于等于0.033时的击穿电压显著高于Si-CH2-Si/Si-CH3的比值小于等于0.029时的击穿电压。具体而言，Si-CH2-Si/Si-CH3的比值大于等于0.033时的击穿电压为Si-CH2-Si/Si-CH3的比值小于等于0.029时的击穿电压的大约两倍或更大。
图11为表示凸块下金属膜UBM的厚度与层间绝缘膜IL1中出现的缺陷的发生率之间关系的图。图11的横轴代表半导体器件SD的凸块下金属膜UBM的厚度（μm）。图11的纵轴代表进行预先确定的热循环测试的层间绝缘膜IL1中出现的缺陷的发生率。如上所述，术语“缺陷”是指当将热应力施加于凸块电极时，在凸块电极BE下面的层间绝缘膜IL1中出现的裂缝。
在图11中，黑色菱形标识代表在层间绝缘膜IL1的Si-CH2-Si/Si-CH3的比值小于等于0.029的条件下，对比实施例的半导体器件SD的结果。空心矩形标识代表在层间绝缘膜IL1的Si-CH2-Si/Si-CH3的比值大于等于0.033的条件下，第二实施方式的半导体器件SD的结果。凸块下金属膜UBM含有Ni。
如图11所示，在层间绝缘膜IL1的Si-CH2-Si/Si-CH3的比值小于等于0.029的对比实施例的半导体器件SD中，当凸块下金属膜UBM的厚度增加时，缺陷发生率趋于增加。
如图4所示，为了使电迁移寿命符合预定产品的可靠性标准，需要使凸块下金属膜UBM的厚度大于等于1.5μm。然而，如图11所示，在对比实施例中，即使当凸块下金属膜UBM的厚度大于等于1.5μm时，也会在层间绝缘膜中出现裂缝。
另一方面，在层间绝缘膜IL1的Si-CH2-Si/Si-CH3的比值大于等于0.033的第二实施方式的半导体器件SD中，不论凸块下金属膜UBM的厚度如何，缺陷发生率都为0。这就是说，当凸块下金属膜UBM的厚度使电迁移寿命符合预定产品的可靠性标准时，诸如裂缝之类的缺陷不会在凸块电极BE下面的层间绝缘膜中出现。因此，在第二实施方式中，可控制形成凸块电极BE的材料的迁移，并且可显著控制层间绝缘膜IL1中的缺陷的发生率。
用于制造根据第二实施方式的半导体器件SD的方法与用于制造根据第一实施方式的半导体器件SD的方法类似，除了层间绝缘膜形成步骤中的膜形成条件落入进一步限定的范围内以外。
在根据第二实施方式的层间绝缘膜形成步骤中，例如，层间绝缘膜IL1在如下条件下形成。具体而言，例如，压力为大于等于2Torr且小于等于4Torr。RF功率为大于等于500W且小于等于1500W。应当注意的是，功率取决于装置，因此，不限于上述范围。Si原材料的流速与总气流流速的比值为大于等于0.5且小于等于0.7。衬底温度为大于等于330℃且小于等于400℃。
根据第二实施方式，可获得与第一实施方式类似的有益效果。进一步地，根据第二实施方式，不论凸块下金属膜UBM的厚度，可显著控制凸块电极BE下面的层间绝缘膜中出现的诸如裂缝之类的缺陷的发生率。
虽然基于实施方式对本发明进行了描述，但是本发明并不限于此。因此，可在不背离本发明的实质和范围的情况下对本发明的实施方式作出各种改变。

Claims (8)

1.一种半导体器件，所述半导体器件包括：
含有Si、O、C和H的层间绝缘膜；
设置在所述层间绝缘膜上方的含有Ni的凸块电极下金属膜；以及
设置在所述凸块电极下金属膜上方的凸块电极，
其中，在所述层间绝缘膜中，波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.15且小于等于0.27，并且，波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值大于等于0.031，所述比值通过傅里叶变换红外光谱FTIR获得。
2.如权利要求1所述的半导体器件，
其中，Si-CH3的峰高与Si-O的峰高的比值为大于等于0.16且小于等于0.24，并且
其中，Si-CH2-Si的峰高与Si-CH3的峰高的比值大于等于0.033。
3.如权利要求1所述的半导体器件，
其中，所述凸块电极下金属膜的厚度为大于等于1.5μm且小于等于3.0μm。
4.如权利要求1所述的半导体器件，
其中，所述凸块电极含有Sn和Ag。
5.如权利要求1所述的半导体器件，
其中，所述凸块电极的高度为大于等于50μm且小于等于100μm。
6.如权利要求1所述的半导体器件，
其中，所述层间绝缘膜的相对介电常数为大于等于2.5且小于等于3.2。
7.一种用于制造半导体器件的方法，所述方法包括如下步骤：
形成含有Si、O、C和H的层间绝缘膜，
形成位于所述层间绝缘膜上方的含有Ni的凸块电极下金属膜，以及
形成位于所述凸块电极下金属膜上方的凸块电极，
其中，在形成所述层间绝缘膜的步骤中，波数1270cm-1附近的Si-CH3的峰高与波数1030cm-1附近的Si-O的峰高的比值为大于等于0.15且小于等于0.27，并且，波数1360cm-1附近的Si-CH2-Si的峰高与波数1270cm-1附近的Si-CH3的峰高的比值大于等于0.031，所述比值通过傅里叶变换红外光谱FTIR获得。
8.如权利要求7所述的方法，其中，在形成凸块电极下金属膜的步骤中，所述凸块电极下金属膜的厚度为大于等于1.5μm且小于等于3.0μm。
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