CN106601622A - 接合结构及其形成方法 - Google Patents

接合结构及其形成方法 Download PDF

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Publication number
CN106601622A
CN106601622A CN201610643423.4A CN201610643423A CN106601622A CN 106601622 A CN106601622 A CN 106601622A CN 201610643423 A CN201610643423 A CN 201610643423A CN 106601622 A CN106601622 A CN 106601622A
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China
Prior art keywords
dielectric layer
layer
opening
conductive
conductive pole
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CN201610643423.4A
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CN106601622B (zh
Inventor
李明机
刘重希
古进誉
郭宏瑞
亚历山大·卡尔尼茨基
何明哲
吴逸文
陈清晖
刘国洲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括在导电焊盘上方形成第一介电层，在第一介电层上方形成第二介电层并且蚀刻第二介电层以形成第一开口，第一介电层的顶面暴露于第一开口。形成模板层以填充第一开口。然后，在模板层和第一介电层中形成第二开口，导电焊盘的顶面暴露于第二开口。在第二开口中形成导电柱。本发明的实施例还涉及接合结构及其形成方法。

Description

接合结构及其形成方法
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及接合结构及其形成方法。
背景技术
在集成电路的封装中，金属至金属接合(有时还称为直接接合)以及焊料接合为通常使用的接合方法。在直接接合中，两个晶圆或芯片的接合焊盘接合在一起而没有焊料设置在其间。例如，直接接合可以是铜至铜接合或金至金接合。在典型的直接接合工艺中，器件管芯的金属凸块与封装件衬底的金属凸块对准并且抵靠封装件衬底的金属凸块放置。施加压力以挤压器件管芯和封装件衬底彼此抵靠。在接合期间，还加热器件管芯和封装件衬底。利用压力和升高的温度，器件管芯和封装件衬底的金属凸块的表面部分相互扩散，从而形成接合件。
发明内容
本发明的实施例提供了一种方法，包括：在导电焊盘上方形成第一介电层；在所述第一介电层上方形成第二介电层；蚀刻所述第二介电层以形成第一开口，所述第一介电层的顶面暴露于所述第一开口；形成填充所述第一开口的模板层；在所述模板层和所述第一介电层中形成第二开口，所述导电焊盘的顶面暴露于所述第二开口；以及在所述第二开口中镀导电柱。
本发明的另一实施例提供了一种方法，包括：在导电焊盘上方形成第一介电层，而所述第一介电层是平坦层；在所述第一介电层上方形成第二介电层；蚀刻所述第二介电层以形成第一开口，其中，当暴露出所述第一介电层的顶面时，停止蚀刻所述第二介电层；形成延伸至所述第一开口的共形介电层；在所述共形介电层上方形成填充所述第一开口的模板层；在所述模板层上方形成图案化的光刻胶；蚀刻所述模板层、所述共形介电层和所述第一介电层以形成第二开口；在所述第二开口中镀导电柱，所述导电柱连接至所述导电焊盘；以及去除所述模板层。
本发明的又一实施例提供了一种结构，包括：导电焊盘；第一介电层，位于所述导电焊盘上方；第二介电层，位于所述第一介电层上方；第三介电层，延伸至所述第二介电层中的开口中，其中，所述第三介电层包括位于所述开口的侧壁上的侧壁部分以及接触所述第一介电层的顶面的底部；以及导电柱，贯穿所述第三介电层的底部和所述第一介电层，其中，所述导电柱与所述导电焊盘接触。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图16A示出了根据一些实施例的在接合结构的形成中的中间阶段的截面图。
图16B示出了根据一些实施例的导电柱和周围的开口的顶视图。
图17示出了根据一些实施例的与另一封装件组件的导电部件接触的导电柱。
图18示出了根据一些实施例的通过焊料接合接合至另一封装件组件的导电部件的导电柱。
图19示出了根据一些实施例的用于形成接合结构的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…下面”、“在…下方”、“下部”、“在…上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例，提供了接合结构和形成接合结构的方法。示出了根据一些实施例的形成接合结构的中间阶段。讨论了一些示例性实施例的变化。在各个视图和说明性实施例中，类似的参考标号用于标示类似的元件。
图1至图16A示出了根据一些实施例的在接合结构的形成中的中间阶段的截面图。在图1至图16A中所示的步骤也在图19所示的工艺流程400中示意性地示出。在随后的讨论中，参照图19中的工艺步骤讨论图1至图16A所示的工艺步骤。
图1示出了封装件组件100的截面图。根据本发明的一些实施例，封装件组件100是包括诸如晶体管和/或二极管的有源器件以及诸如电容器、电感器、电阻器等的可能的无源器件的器件晶圆。根据本发明的可选实施例，封装件组件100是可能或可能不包括有源器件和/或无源器件的插入件晶圆。根据本发明的又可选的实施例，封装件组件100是封装件衬底条，其可以是在其中具有核心的封装件衬底或无核的封装件衬底。在随后的讨论中，器件晶圆用作示例性封装件组件100。本发明的教导还可以应用于插入件晶圆、封装件衬底等。
根据本发明的一些实施例，示例性晶圆100包括半导体衬底20和在半导体衬底20的顶面处形成的部件。半导体衬底20可以包括晶体硅、晶体锗、硅锗和/或III-V族化合物半导体，诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等。半导体衬底20还可以是块状硅衬底或绝缘体上硅(SOI)衬底。在半导体衬底20中可以形成浅沟槽隔离(STI)区域(未示出)以隔离半导体衬底20中的有源区域。尽管未示出，可以形成贯通孔以延伸至半导体衬底20中，其中，使用贯通孔以电互连位于晶圆100的相对两侧上的部件。
根据本发明的一些实施例，晶圆100包括在半导体衬底20的顶面上形成的集成电路器件22。示例性集成电路器件22包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。在此未示出集成电路器件22的细节。根据可选实施例，晶圆100用于形成插入件，其中，衬底20可以是半导体衬底或及介电衬底。
层间电介质(ILD)24形成在半导体衬底20上方并且填充集成电路器件22中的晶体管(未示出)的栅极堆叠件之间的间隔。根据一些示例性实施例，ILD24包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等。可以使用旋涂、可流动化学汽相沉积(FCVD)等形成ILD24。根据本发明的可选实施例，使用诸如等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等的沉积方法形成ILD24。
接触插塞28形成在ILD24中，且用于将集成电路器件22电连接至上面的金属线、通孔和导电柱92(图16A)。根据本发明的一些实施例，接触插塞28由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层的导电材料形成。接触插塞28的形成可以包括：在ILD24中形成开口，在接触开口内填充导电材料，以及实施平坦化(诸如化学机械抛光(CMP))以使接触插塞28的顶面和ILD24的顶面齐平。
又如图1所示，在ILD24和集成电路器件22(如果有的话)上方形成蚀刻停止层27。蚀刻停止层27可以包括碳化硅、氮化硅、氮氧化硅、碳氮化硅等。蚀刻停止层27由相对于上面的介电层30具有高蚀刻选择性的材料形成，并且因此蚀刻停止层27可以用于停止介电层30的蚀刻。
图1中还示出了介电层30，其在下文中可选地称为金属间介电(IMD)层30。根据本发明的一些实施例，IMD层30由介电常数(k值)低于约3.0、低于约2.5或甚至更低的低k介电材料形成。IMD层30可以包括Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。IMD层30也可以具有低k值，低k值可以低于约3.0、2.5或2.0。根据本发明的一些实施例，IMD层30的形成包括沉积含致孔剂的介电材料以及然后实施固化工艺以驱除致孔剂，并且因此剩余的IMD层30是多孔的。
根据可选实施例，IMD层30由非低k介电材料形成，诸如氧化硅、氮化硅、碳化硅、氮氧化硅等。
在IMD层30中形成导电线32。根据一些实施例，金属线32包括扩散阻挡层34和位于扩散阻挡层34上方的含铜材料36。扩散阻挡层34可以包括钛、氮化钛、钽、氮化钽等，并且具有防止含铜材料36中的铜扩散到IMD层30内的功能。导电线32在下文中又称为金属线32。导电线32的形成可包括单镶嵌工艺。
参考图2，在IMD30和导电线32上方形成蚀刻停止层38和IMD层40。根据本发明的一些实施例，蚀刻停止层38由选自碳化硅、氮化硅、氮氧化硅、碳氮化硅等的介电材料形成。IMD层40可以由低k材料或非低k材料形成，并且IMD层40的材料可以选自用于形成IMD30的备选材料的相同组。
参照图3，在IMD层40中形成沟槽42和通孔开口44。根据本发明的一些实施例，形成工艺包括使用光刻工艺以蚀刻IMD层40，从而形成初始的通孔开口，其中，初始的通孔开口从IMD层40的顶面延伸至位于IMD层40的顶面和底面之间的中间水平面。接下来，形成和图案化金属硬掩模(未示出)以限定沟槽42的图案。然后实施各向异性蚀刻以蚀刻IMD层40，从而形成沟槽42。在形成沟槽42的同时，初始的通孔开口向下延伸至蚀刻停止层38，从而形成通孔开口44。可以使用时间模式实施用于形成沟槽42的蚀刻。根据可选实施例，在单独的光刻工艺中形成通孔开口44和沟槽42。例如，在第一光刻工艺中，形成向下至蚀刻停止层38的通孔开口44。在第二光刻工艺中，形成沟槽42。然后使蚀刻停止层38暴露以暴露出下面的导电线32。
使用包括氟和碳的工艺气体实施IMD层40的蚀刻，其中，氟用于蚀刻，而碳具有保护产生的通孔开口44和沟槽42的侧壁的效果。例如，用于蚀刻的工艺气体包括诸如C4F8、CH2F2和/或CF4的含氟和碳的气体以及诸如N2的载体气体。在具有适当的氟碳比率的情况下，通孔开口44和沟槽42可以具有期望的轮廓。
图4和图5示出了在通孔开口44(图3)中形成导电通孔50以及在沟槽42中形成导电线52。图4示出了导电通孔50和导电线52的形成中的中间阶段。根据本发明的一些实施例，通孔50和导电线52的形成包括实施毯式沉积以形成导电衬垫46，沉积铜或铜合金的薄晶种层(未示出)，以及例如通过电镀、化学镀、沉积等利用导电材料48填充剩余的通孔开口44和沟槽42。导电衬垫46可以是扩散阻挡层、粘合层等。导电衬垫46可以包括钛、氮化钛、钽、氮化钽或其他替代物。导电材料48可以包括铜、铜合金、银、金、钨、铝等。接下来，如图5所示，实施诸如CMP的平坦化以使衬垫46的表面和导电材料48齐平，并且从IMD层40的顶面去除过量的材料。
图6示意性地示出多个介电(IMD)层53以及在介电层53中的各自导电线和通孔(未示出)的形成。根据一些示例性实施例，IMD层53的数量是基于封装件组件100的布线需求确定的且其范围可以从0至7或更多。IMD层53的数量等于0意味着随后形成的蚀刻停止层54和介电层56直接形成在IMD层40上方而其间没有附加的介电层和导电线。IMD层53中的导电线和通孔(未示出)电连接至集成电路器件22。
又如图6所述，在介电层53上方形成蚀刻停止层54和IMD层56。根据本发明的一些实施例，蚀刻停止层54由选自用于形成蚀刻停止层27的备选材料的相同组的介电材料形成，其中，备选材料可以包括碳化硅、氮化硅、氮氧化硅、碳氮化硅等。IMD层56还可以由低k材料或非低k材料形成，并且IMD层56的材料可以选自用于形成IMD30和40的备选材料的相同组。
图7至图9示出了导电焊盘和连接通孔的形成。相应的步骤示出为图19中示出的工艺流程图中的步骤402。参照图7，在IMD层56中形成沟槽58和通孔开口60。形成工艺可以与如图3中所示的沟槽42和通孔开口44的形成相同。在随后的工艺步骤中，如图8所示，形成导电衬垫62，接下来利用导电材料64填充沟槽58和通孔开口60。衬垫62和导电材料64的材料可以分别地选自下面的衬垫46和导电材料48(图4)的备选材料。接下来，实施平坦化工艺以去除导电衬垫62和导电材料64的高于IMD层56的顶面的部分，从而得到通孔66和导电部件68，如图9所示。通孔66和导电部件68可以电连接至集成电路器件22。
导电部件68包括导电焊盘68A、并且包括连接至导电焊盘68A的导电线68B。如图9所示，根据一些示例性实施例，导电焊盘68A可以通过导电线68B连接至通孔66。根据一些实施例，导电焊盘68A还可以具有接触通孔66的顶面的底面。
参考图10，形成介电层70和72。相应的步骤示出为图19中示出的工艺流程图中的步骤404。根据一些示例性实施例，介电层70和72中的每个由包括氮化硅、氧化硅、碳化硅、氮氧化硅、氮碳化硅、它们的组合或它们的多层的非低k介电材料形成。根据一些示例性实施例，介电层70由氮化硅形成。介电层70的厚度T1可以在介于约和约之间的范围内。应当理解，整个说明书中记载的值是实例，并且可以使用不同的值。
介电层72可以是单层或可以是包括多个(子)介电层的复合层。当介电层72是复合层时，介电层72中的相邻的介电层是由不同的介电材料形成的。介电层72中的介电层的数量可以是1、2、3或更多。根据一些示例性实施例，如图10所示，介电层72包括介电层70上方的介电层74、介电层74上方的介电层76以及介电层76上方的介电层78。根据一些示例性的实施例，介电层74可以由氧化硅(SiO2)形成。根据一些示例性的实施例，介电层76可以由氮化硅形成。根据一些示例性的实施例，介电层78可以由氧化硅(SiO2)形成。介电层74的厚度T2可以在介于约和约之间的范围内。介电层76的厚度T3可以在介于约和约之间的范围内。介电层78的厚度T4可以在介于约和约之间的范围内。介电层70、74、76、78可以形成为贯穿整个封装件部件100均平坦的平坦层。层70、74、76、78的形成方法可以是诸如等离子体增强化学汽相沉积(PECVD)或低压化学汽相沉积(LPCVD)的化学汽相沉积(CVD)方法。
参照图11，在介电层72上方形成光刻胶80，并且图案化光刻胶80以形成开口82。接下来，将光刻胶80用作蚀刻掩模以蚀刻下面的介电层72。相应的步骤示出为图19中示出的工艺流程图中的步骤406。蚀刻是各向异性的并且可以使用干蚀刻实施蚀刻。用于蚀刻氧化硅层(诸如层74和78)的工艺气体可以包括氨(NH3)和三氟化氮(NF3)的混合气体，其称为SiCoNiTM。用于蚀刻氮化硅的工艺气体可以包括CF4和H2的混合物，CF4、O2和N2的混合物，SF6、O2和N2的混合物，SF6、CH4和N2的混合物或SF6、CH4、N2和O2的混合物。还可以调整工艺的构成以具有充分的蚀刻选择性，例如，大于约30，从而不蚀刻穿过介电层70。如图11所示，蚀刻的结果，开口82贯穿介电层72并且略延伸至介电层70中。在一些实施例中，开口82可以在介电层70内延伸大于约的深度D1。
根据一些实施例，开口82的侧壁82A是基本上垂直的，而侧壁82A的倾斜角度α介于约85度和约90度之间。在开口82形成之后，去除光刻胶80。
接下来，如图12所示，形成介电层84。相应的步骤示出为图19中示出的工艺流程图中的步骤408。介电层84具有位于介电层72上方的第一部分和延伸至开口82中的第二部分。介电层84可以是具有水平部分和垂直部分的共形层，水平部分和垂直部分具有相同的厚度或基本上相同的厚度。根据一些实施例，例如，水平部分的厚度T5和垂直部分的厚度T6可以具有差(T5-T6)，且比率(T5-T6)/T5可以小于约0.2、或小于约0.1。可以使用诸如原子层沉积(ALD)的共形沉积方法形成介电层84。例如，介电层84的厚度T5和T6可以在介于约和约之间的范围内。根据一些示例性实施例，介电层84包括氧化铝(Al2O3)。
参考图13，形成模板层86以填充开口82(图12)。相应的步骤示出为图19中示出的工艺流程图中的步骤410。模板层86的顶面高于介电层84的顶面。模板层86可以由氧化硅形成，可以使用诸如TEOS和臭氧的前体形成模板层86。形成方法可以包括PECVD、次大气压化学汽相沉积(SACVD)等。可以实施诸如CMP的平坦化步骤以使模板层86的顶面齐平。
参照图14，在模板层86上方形成光刻胶88，并且图案化光刻胶88。接下来，将光刻胶88用作蚀刻掩模以蚀刻下面的模板层86、介电层84和介电层70以形成开口90。相应的步骤示出为图19中示出的工艺流程图中的步骤412。结果，暴露导电焊盘68A。蚀刻是各向异性的并且可以使用干蚀刻实施蚀刻。根据一些实施例，用于蚀刻模板层86的工艺气体还可以包括SiCoNiTM。用于蚀刻氧化铝(层84)的工艺气体可以包括O2、BCl3和Ar的混合物。蚀刻的结果，开口90贯穿层86、84和70并且可以略延伸至导电焊盘68A中。开口90的水平尺寸较小，例如，小于约3μm。其中在介电层70中具有底切的情况下(由对应于相同的蚀刻剂的不同的材料的不同蚀刻速率造成)，控制底切小于约0.5μm。
然后，去除光刻胶88，并且产生出的结构示出在图15中。接下来，使用模板层86作为模板，例如通过电化学镀或化学镀在开口90中形成导电柱92。相应的步骤示出为图19中示出的工艺流程图中的步骤414。根据一些实施例，由于导电焊盘68A用作用于镀的晶种层，没有形成毯式晶种层。导电柱92可以是金属柱并且可以具有单层结构或多层结构。导电柱92的材料可以选自Cu、Ni、Pd、Au、Sn、SnAg、Co、它们的组合和它们的多层。根据一些示例性实施例，导电柱92包括镍层92A和位于镍层92A上方的金层92B。
然后，如图16A所示，去除模板层86，留下导电柱92。相应的步骤示出为图19中示出的工艺流程图中的步骤416。导电柱92在开口82中具有可以是多数的部分和高于介电层84的顶面84A的部分。导电柱92的顶面93和层84的顶面84A具有可以小于约的高度差ΔH。高度差ΔH还可以在介于约和约之间的范围内。
图16B示出了在图16A中的接合结构的顶视图。图16B示出了导电柱92由开口82环绕。此外，导电柱92落在导电焊盘68A上，而导电焊盘68A扩展超过导电柱92的边缘。在随后的工艺中，如图16A示出的晶圆100可以锯切为管芯102或在随后的步骤中仍然是未锯切的晶圆。
图17示出了管芯102或晶圆100(以下称为管芯/晶圆102/100)与封装件组件200接触。封装件组件200可以是器件管芯或晶圆、插入件管芯或晶圆、封装件衬底或封装件。导电柱92可以在封装件组件200的表面处与金属部件204物理接触。由于导电柱突出高于介电层84的表面84A，介电层84与封装件组件200中的介电层206分隔开。
根据示例性实施例，可以实施管芯102或晶圆100与封装件组件200的接触以用于共同地测试管芯/晶圆102/100和封装件组件200中的电路。在随后的步骤中，管芯/晶圆102/100与封装件组件200分隔开。由于介电层84不与介电层206物理接触，所以没有粘附力防止管芯/晶圆102/100与封装件组件200分隔开。
图18示出了一个步骤，其中，管芯/晶圆102/100接合至可以是器件管芯/晶圆、插入件管芯/晶圆、封装件衬底或封装件的封装件组件300。根据一些实施例，焊料区域308将导电柱92接合至封装件组件300中的导电部件304。根据一些实施例，介电层84还可以与封装件组件300中的表面介电层306分隔开。管芯/晶圆102/100和封装件组件300之间的间隙可以利用底部填充物(未示出)填充，或在最终产品中仍然是未填充的(当使用它时)。根据一些实施例，焊料区域308可以完全地或部分地填充开口82(图16A和图16B)。焊料区域308可以接触导电柱92的侧壁。
本发明的实施例具有一些有利的特征。通过使用模板层作为镀模板以形成导电柱，不需要使用光刻胶作为镀模板。相应地，可以显著地减小导电柱的水平尺寸，例如，小于约3μm，这如果使用光刻胶作为镀模板来形成导电柱则不能实现。此外，不需要晶种层来镀导电柱，并且因此不再需要去除晶种层的不期望的部分。此外，例如在图17中所示的步骤，通过在开口中形成导电柱，导电柱受到保护以免受颗粒的污染，并且受到保护以免受可能的机械损伤。
根据本发明的一些实施例，一种方法包括在导电焊盘上方形成第一介电层，在第一介电层上方形成第二介电层并且蚀刻第二介电层以形成第一开口，从而第一介电层的顶面暴露于第一开口。形成模板层以填充第一开口。然后，在模板层和第一介电层中形成第二开口，从而导电焊盘的顶面暴露于第二开口。在第二开口中形成导电柱。
在上述方法中，还包括形成延伸至所述第一开口中的共形介电层，所述共形介电层接触所述第一介电层的所述顶面，其中，所述第二开口贯穿所述共形介电层。
在上述方法中，还包括形成延伸至所述第一开口中的共形介电层，所述共形介电层接触所述第一介电层的所述顶面，其中，所述第二开口贯穿所述共形介电层，使所述导电柱与封装件组件接触，而所述共形介电层与所述封装件组件间隔开；以及将所述导电柱与所述封装件组件分离。
在上述方法中，还包括：蚀刻所述模板层以再次暴露出所述第一开口，其中，所述导电柱的侧壁暴露于所述第一开口。
在上述方法中，还包括：在所述模板层上方形成图案化的光刻胶，其中，使用所述图案化的光刻胶作为蚀刻掩模以蚀刻所述模板层；以及去除所述图案化的光刻胶。
在上述方法中，还包括：通过焊料区域将所述导电柱接合至导电部件，其中，所述焊料区域填充所述第一开口并且接触所述导电柱的侧壁。
在上述方法中，其中，实施镀所述导电柱而不形成毯式晶种层。
根据本发明的一些实施例，一种方法包括在导电焊盘上方形成第一介电层，而第一介电层是平坦层，在第一介电层上方形成第二介电层，而第一介电层和第二介电层均为平坦层，并且蚀刻第二介电层以形成第一开口。当暴露出第一介电层的顶面时，停止蚀刻第二介电层。该方法进一步包括形成延伸至第一开口中的共形介电层，在共形介电层上方形成填充第一开口的模板层，以及在模板层上方形成图案化的光刻胶。蚀刻模板层、共形介电层和第一介电层以形成第二开口。在第二开口中镀导电柱，从而导电柱连接至导电焊盘。然后去除模板层。
在上述方法中，其中，使用正硅酸乙酯(TEOS)作为前体形成所述模板层。
在上述方法中，还包括：使所述导电柱的顶面与封装件组件中的导电部件的表面接触，而所述共形介电层与所述封装件组件间隔开；以及在所述接触之后，将所述导电柱与所述封装件组件分离。
在上述方法中，其中，在去除所述模板层之后，再次暴露出所述第一开口的部分，并且所述导电柱的侧壁暴露于所述第一开口。
在上述方法中，其中，所述导电柱包括：接触所述导电焊盘的所述顶面的第一金属材料；以及位于所述第一金属材料上方且接触所述第一金属材料的第二金属材料。
在上述方法中，还包括：通过焊料区域将所述导电柱接合至导电部件，其中，所述焊料区域填充所述第一开口并且接触所述导电柱的侧壁。
在上述方法中，其中，实施镀所述导电柱而不形成毯式晶种层。
根据本发明的一些实施例，一种结构包括导电焊盘、导电焊盘上方的第一介电层以及第一介电层上方的第二介电层。共形介电层延伸至第二介电层中的开口中。共形层具有开口的侧壁上的侧壁部分和接触第一介电层的顶面的底部。导电柱贯穿共形介电层的底部和第一介电层。导电柱与导电焊盘接触。
在上述结构中，其中，所述导电柱的底面与所述导电焊盘的顶面物理接触。
在上述结构中，还包括低k介电层，所述导电焊盘位于所述低k介电层中，其中，所述第一介电层的底面接触所述低k介电层的顶面。
在上述结构中，还包括：位于所述开口中且接触所述导电柱的侧壁和所述第三介电层的所述侧壁部分的焊料区域。
在上述结构中，其中，所述第三介电层还包括接触所述第二介电层的顶面的水平部分。
在上述结构中，其中，所述导电柱延伸至所述第一介电层中。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成接合结构的方法，包括：
在导电焊盘上方形成第一介电层；
在所述第一介电层上方形成第二介电层；
蚀刻所述第二介电层以形成第一开口，所述第一介电层的顶面暴露于所述第一开口；
形成填充所述第一开口的模板层；
在所述模板层和所述第一介电层中形成第二开口，所述导电焊盘的顶面暴露于所述第二开口；以及
在所述第二开口中镀导电柱。
2.根据权利要求1所述的方法，还包括形成延伸至所述第一开口中的共形介电层，所述共形介电层接触所述第一介电层的所述顶面，其中，所述第二开口贯穿所述共形介电层。
3.根据权利要求2所述的方法，还包括：
使所述导电柱与封装件组件接触，而所述共形介电层与所述封装件组件间隔开；以及
将所述导电柱与所述封装件组件分离。
4.根据权利要求1所述的方法，还包括：蚀刻所述模板层以再次暴露出所述第一开口，其中，所述导电柱的侧壁暴露于所述第一开口。
5.根据权利要求1所述的方法，还包括：
在所述模板层上方形成图案化的光刻胶，其中，使用所述图案化的光刻胶作为蚀刻掩模以蚀刻所述模板层；以及
去除所述图案化的光刻胶。
6.根据权利要求1所述的方法，还包括：通过焊料区域将所述导电柱接合至导电部件，其中，所述焊料区域填充所述第一开口并且接触所述导电柱的侧壁。
7.根据权利要求1所述的方法，其中，实施镀所述导电柱而不形成毯式晶种层。
8.一种形成接合结构的方法，包括：
在导电焊盘上方形成第一介电层，而所述第一介电层是平坦层；
在所述第一介电层上方形成第二介电层；
蚀刻所述第二介电层以形成第一开口，其中，当暴露出所述第一介电层的顶面时，停止蚀刻所述第二介电层；
形成延伸至所述第一开口的共形介电层；
在所述共形介电层上方形成填充所述第一开口的模板层；
在所述模板层上方形成图案化的光刻胶；
蚀刻所述模板层、所述共形介电层和所述第一介电层以形成第二开口；
在所述第二开口中镀导电柱，所述导电柱连接至所述导电焊盘；以及
去除所述模板层。
9.根据权利要求8所述的方法，其中，使用正硅酸乙酯(TEOS)作为前体形成所述模板层。
10.一种接合结构，包括：
导电焊盘；
第一介电层，位于所述导电焊盘上方；
第二介电层，位于所述第一介电层上方；
第三介电层，延伸至所述第二介电层中的开口中，其中，所述第三介电层包括位于所述开口的侧壁上的侧壁部分以及接触所述第一介电层的顶面的底部；以及
导电柱，贯穿所述第三介电层的底部和所述第一介电层，其中，所述导电柱与所述导电焊盘接触。
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