TWI809823B - 半導體元件的製作方法 - Google Patents

半導體元件的製作方法 Download PDF

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TWI809823B
TWI809823B TW111114545A TW111114545A TWI809823B TW I809823 B TWI809823 B TW I809823B TW 111114545 A TW111114545 A TW 111114545A TW 111114545 A TW111114545 A TW 111114545A TW I809823 B TWI809823 B TW I809823B
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Taiwan
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wafer
depositing
layer
sublayer
protective layer
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TW111114545A
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TW202320173A (zh
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周家政
柯忠祁
李資良
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台灣積體電路製造股份有限公司
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Abstract

一種包含將第一晶圓接合至第二晶圓，及在第一晶片上進行修整製程的方法。去除第一晶圓的邊緣部分。在修整製程之後，第一晶圓具有從第二晶圓的第二側壁橫向地凹陷的第一側壁。沉積保護層並接觸第一晶圓的側壁，該沉積製程包含沉積與第一側壁接觸的非含氧材料。該方法進一步包含去除與第一晶圓重疊的保護層的水平部分，並在第一晶圓之上形成互連接結構。互連接結構電性地連接至第一晶圓中的積體電路元件。

Description

半導體元件的製作方法
本揭露是有關於一種半導體元件的製作方法。
載體晶圓通常被使用於積體電路的封裝，作為支持機構。舉例而言，當形成具穿透裝置晶圓的基材的貫穿通孔的裝置晶圓時，將裝置晶圓接合至載體晶圓，以便薄化裝置晶圓，並可在基材的後側上形成電性連接器。
根據本揭露內容的一些實施例，半導體元件的製作方法包括以下步驟：將晶圓接合至第二晶圓；在第一晶圓上進行修整製程，其中第一晶片的邊緣部分被去除，並且在修整製程之後，第一晶圓具有從第二晶圓的第二側壁橫向地凹陷的第一側壁；沉積與第一晶圓的側壁接觸的保護層，其中沉積保護層之步驟包括沉積與第一側壁接觸的非含氧材料之步驟；去除與第一晶圓重疊的保護層的水平部 分；及在第一晶圓之上形成互連接結構，其中互連接結構電性地連接至第一晶圓中的積體電路元件。
根據本揭露內容的一些實施例，半導體元件的製作方法包括以下步驟：將元件晶圓接合在載體晶圓之上；薄化元件晶圓的半導體基材；修整元件晶圓，其中修整元件晶圓的邊緣部分；在元件晶圓及載體晶圓上沉積保護層，其中沉積保護層之步驟包括以下步驟：沉積包括第一材料的第一子層；及沉積包括不同於第一材料的第二材料的第二子層；露出元件晶圓的頂部表面；及在元件晶圓之上形成互連接結構，其中互連接結構電性地連接至元件晶圓中的積體電路元件。
根據本揭露內容的一些實施例，半導體元件的製作方法包括以下步驟：在載體晶圓之上接合元件晶圓，其中元件晶圓中的第一介電層接合至載體晶圓中的第二介電層；修整元件晶圓，其中元件晶圓中的第一半導體基材的一部分被修整，且載體晶圓中的第二基材的頂部表面被暴露；在元件晶圓及載體晶圓上沉積保護層，其中沉積保護層的步驟使用其中不含氧製程氣體進行；從元件晶圓及載體晶圓去除保護層的水平部分；及去除第二基材。
T2:厚度
W1:修整寬度
20:載體晶圓
22,32:基材
24,54:接合層
30:元件晶圓
30’:元件裸晶
34:積體電路元件
36,46:層間介電質
38:接觸柱塞
40:互連接結構
42:金屬線路
44,65:通孔
50:頂部金屬焊墊
52,58:聚合物層
60:凹陷
62:保護層
62A:下子層
62B:上子層
63:虛線區
64:介電層
65:貫穿通孔
68:後側互連接結構
70:重佈線層
72:介電層
76,78:電性連接器
80:封裝
82:元件裸晶
84:封裝劑
86:底部填充物
88:封裝組件
200:製程流程圖
202~228:製程
當與隨附圖示一起閱讀時，可由以下實施方式最佳地理解本揭露內容的態樣。應注意到根據此產業中之標準 實務，各種特徵並未按比例繪製。實際上，為論述的清楚性，可任意增加的或減少各種特徵的尺寸。
第1至11圖例示根據一些實施例，晶圓接合製程的中間階段及封裝的形成。
第12至14圖例示根據一些實施例，晶圓接合製程的中間階段及封裝的形成。
第15圖例示根據一些實施例，用於形成封裝的製程流程圖。
以下揭露內容提供用於實行本揭露的不同特徵之許多不同實施例、或範例。後文描述組件及佈置之特定範例以簡化本揭露內容。當然，此等僅為範例且未意圖具限制性。舉例而言，在後文的描述中，在第二特徵之上或上之第一特徵的形成可包含其中以直接接觸方式形成第一特徵及第二特徵的實施例，且亦可包含其中在第一特徵與第二特徵間形成額外特徵，使得第一特徵及第二特徵可不直接接觸之實施例。此外，在各種範例中，本揭露內容可能重複元件符號及/或字母。此重複係出於簡單及清楚的目的，且重複本身並不規範所論述的各種實施例及/或配置間之關係。
進一步地，為便於描述，本文中可使用諸如「在...之下」、「在...下方」、「較低」、「在...上方」、「較高」、及類似者的空間相對術語，以描述圖示中所例示之 一個元件或特徵與另一元件(等)或特徵(等)的關係。除圖示中所描繪之定向之外，空間相對術語亦預期涵蓋元件在使用或操作中之不同定向。設備能以其他方式定向(旋轉90度或以其他定向)，且本文中使用之空間相對描述語可同樣以相應的方式解釋。
提供一種封裝及其形成方法。根據本揭露內容的一些實施例，將裝置晶圓接合至載體晶圓。薄化裝置晶圓，接著進行邊緣修整製程。在裝置晶圓的側壁上形成保護層。根據一些實施例，保護層包括非含氧層諸如氮化矽層。保護層可進一步為雙層，包含非含氧層及具有良好濕氣隔離能力的層。通過使用非含氧層，減少對低k值介電層及低k值介電層中的金屬特徵的氧化，避免由氧化致使的裝置劣化。在本文中論述的實施例將提供範例以使得可實現製成或使用本揭露內容的標的，且熟習此項技藝者將輕易地瞭解，在落在在不同實施例的考量範圍之內的同時，可進行的修改。貫穿各種視圖及例示性實施例，類似元件符號被使用以指代類似元素。儘管可將方法實施例論述為以特定順序進行，但能以任何邏輯性順序進行其他方法實施例。
第1至11圖例示根據本揭露內容的一些實施例，將裝置晶圓接合至載體晶圓及在裝置晶圓的後側形成後側互連接結構的中間階段的截面視圖。對應的製程亦示意性地反映在製程流程圖中，如第15圖中所圖示。
參照第1圖，形成晶圓20。根據一些實施例，晶圓20為載體晶圓，因此稱作載體晶圓20。載體晶圓20 可具有圓形俯視圖形狀。根據一些實施例，載體晶圓20包含基材22。可由與元件晶圓30中的基材32相同的材料形成基材22(隨後論述)，以便在後續的封裝製程中，歸因於載體晶圓20與元件晶圓30之間的熱膨脹係數(CTE)值不匹配而導致的翹曲減少。可由矽形成基材22或基材包括矽，同時亦可使用諸如陶瓷、玻璃、矽酸鹽玻璃、或類似物的其他材料。根據一些實施例，由均質材料形成整個基材22，其中沒有與均質材料不同的其他材料。舉例而言，可由矽(摻雜或無摻雜)形成整個載體晶圓20，其中不存在金屬區、介電區等。
根據替代實施例，晶圓20為其中包含有源元件(諸如電晶體)及/或無源元件(諸如電容器、電阻器、電感應器、及/或類似物)的元件晶圓。晶圓20，當其為元件晶圓時，亦可為未鋸切晶圓，包含連續延伸至晶圓中所有晶圓裸晶中的半導體基材，或可為包含封裝在封裝劑中的分立元件裸晶的重構晶圓(諸如模塑化合物)。
在基材22上沉積接合層24。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程202。根據一些實施例，由介電材料形成接合層24或接合層包括介電材料，該介電材料可為矽基的介電材料，諸如氧化矽(SiO2)、SiN、SiON、SiOCN、SiC、SiCN、或類似物，或其等的組合。根據一些實施例，接合層24具有在約1000Å與約10000Å之間的範圍內的厚度。
根據本揭露內容的一些實施例，使用高密度電漿化 學氣相沉積(HDPCVD)、電漿增強化學氣相沉積(PECVD)、化學氣相沉積(CVD)、低壓力化學氣相沉積(LPCVD)、原子層沉積(ALD)、或類似物形成接合層24。
根據一些實施例，接合層24與基材22物理接觸。根據替代實施例，載體晶圓20包含接合層24與基材22之間的複數個層(未圖示)。舉例而言，可存在由基於氧化物材料(氧化物材料可亦為基於氧化矽)，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、摻氟矽酸鹽玻璃(FSG)、或類似物，形成的基於氧化物層。亦可存在由氮化矽形成或包括氮化矽的基於氮化物層，同時它亦可由諸如氧氮化矽(SiON)其他材料形成或包括其他材料。根據本揭露內容的一些實施例，可使用PECVD、CVD、LPCVD、ALD、或類似物形成基材22與接合層24之間的層。亦可在接合層24與基材22間形成對準標記。對準標記可形成為金屬柱塞，其可通過鑲嵌製程形成。
進一步參照第1圖，形成元件晶圓30，元件晶圓30可為未鋸切的晶圓，且如第8圖中所圖示的接合製程為晶圓對晶圓的接合製程。根據一些實施例，元件晶圓30包含基材32。可有從前側(例示的頂部表面)延伸至基材32中的基材貫穿通孔(未圖示)。根據替代實施例，在此階段處不形成通孔，並在如第8圖中所圖示的製程中形成貫穿通孔。基材32可為半導體基材，諸如矽基材。根據其他實 施例，基材32可包含其他半導體材料，諸如矽鍺、碳摻雜矽或類似物。基材32可為塊狀基材，或可具有分層結構，舉例而言，包含矽基材及矽基材之上的矽鍺層。
根據一些實施例，元件晶圓30包含元件裸晶，其可包含邏輯裸晶、記憶體裸晶、輸入-輸出裸晶、積體無源元件(IPD)、或類似物，或其等的組合。舉例而言，元件晶圓30中的邏輯元件裸晶可為中央處理單元(CPU)裸晶、圖形處理單元(GPU)裸晶、行動應用裸晶、微控制單元(MCU)裸晶、基帶(BB)裸晶、應用處理器(AP)裸晶，或類似者。元件晶圓30中的記憶體裸晶可包含靜態隨機存取記憶體(SRAM)裸晶、動態隨機存取記憶體(DRAM)裸晶、或類似者。元件晶圓30可為簡單的元件晶圓，包含在整個元件晶圓30中連續延伸的半導體基材，或可為包含封裝在其中的元件裸晶的重構晶圓、包含積體成系統的複數個積體電路(或元件裸晶)的晶片上系統(SoC)裸晶、或類似者。
根據本揭露內容的一些實施例，在半導體基材32的頂部表面上形成積體電路元件34。範例積體電路元件34可包含互補金屬氧化物半導體(CMOS)電晶體、電阻器、電容器、二極體、或類似物。本文中未例示積體電路元件34的細節。根據替代實施例，元件晶圓30被使用於形成插入件，其中基材32可為半導體基材或介電基材。
在半導體基材22之上形成層間介電質(ILD)36，並填充積體電路元件34中電晶體(未圖示)的閘極堆疊之 間的空間。根據一些範例實施例，由氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、氟摻雜矽酸鹽玻璃(FSG)、或類似物形成ILD36或ILD包括氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、氟摻矽酸鹽玻璃(FSG)、或類似物。可使用旋塗、可流動化學氣相沉積(FCVD)、化學氣相沉積(CVD)、或類似物形成ILD36。根據本揭露內容的一些實施例，使用諸如PECVD、LPCVD、或類似物的沉積方法形成ILD 36。
在ILD 36中形成接觸柱塞38，並將接觸柱塞使用於將積體電路元件34電性地連接至上層金屬線路及通孔。根據本揭露內容的一些實施例，由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、以上組合之合金、及/或其等的多層的導電材料形成接觸柱塞38。接觸柱塞38的形成可包含在ILD 36中形成接觸開口，將導電材料填充至接觸開口中，並進行平坦化製程(諸如化學機械拋光(CMP)製程)以使接觸柱塞38的頂部表面與ILD 36的頂部表面齊平。
在ILD 36及接觸柱塞38上存在互連接結構40。互連接結構40包含在介電層46中形成的金屬線路42及通孔44。在下文中，介電層46可包含金屬間介電(IMD)層46。根據本揭露內容的一些實施例，由具有低於約3.0的介電常數值(k值)的低k值介電材料形成一些介電層46。可由Black Diamond(應用材料公司的註冊商標)、含碳 低k值介電材料、Hydrogen SilsesQuioxane(HSQ)、MethylSilsesQuioxane(MSQ)、或類似物形成介電層46。根據本揭露內容的一些實施例，介電層46的形成包含沉積含有致孔劑的介電材料，且接著進行固化製程以驅除致孔劑，且因此其餘的介電層46為多孔的。根據本揭露內容的替代實施例，一些或全部介電層46由非低k值介電材料形成，諸如氧化矽、碳化矽(SiC)、碳氮化矽(SiCN)、氧碳氮化矽(SiOCN)、或類似物。可在介電層46間形成由碳化矽、氮化矽、氧氮化矽、鋁、氧化物、氮化鋁、或類似物或其多層形成的蝕刻停止層(未圖示)，且為簡單起見並未圖示。
在介電層46中形成金屬線路42及通孔44。下文將同一階層的金屬線路42統稱作金屬層。根據本揭露內容的一些實施例，互連接結構40包含通過貫通通孔44互連接的複數個金屬層。基於佈線要求決定MD層數量。舉例而言，可能有5至15個之間的IMD層。
可由銅或銅合金形成金屬線路42及通孔44，且它們亦可由其他金屬形成。形成製程可包含單一鑲嵌製程及雙鑲嵌製程。在範例單一鑲嵌製程中，首先在其中一個介電層46中形成溝槽，接著採用導電材料填充溝槽。接著進行平坦化製程諸如CMP製程以去除高於IMD層頂部表面的導電材料的多餘部分，在溝槽中保留金屬線路。在雙鑲嵌製程中，在IMD層中形成溝槽及通孔開口二者均，通孔開口位於溝槽下層並連接至溝槽。接著將導電材料填充 至溝槽及通孔開口中以分別形成金屬線路及通孔。導電材料可包含擴散阻擋層及擴散阻擋層之上的含銅金屬材料。擴散阻擋層可包含鈦、氮化鈦、鉭、氮化鉭、或類似者。
介電層46可進一步包含在低k值介電層之上的鈍化層。舉例而言，在鑲嵌金屬線路42及通孔44之上可能有無摻雜的矽酸鹽玻璃(USG)層、氧化矽層、氮化矽層等。鈍化層比低k值介電層更密集，並具有將低k值介電層與有害化學物質及氣體諸如濕氣隔離的功能。
根據一些實施例，可在互連接結構40之上形成頂部金屬焊墊50，並通過金屬線路42及通孔44電性地連接至積體電路裝置34。可由銅、鎳、鈦、鈀、或類似物、或其等的合金形成頂部金屬焊墊50或頂部金屬焊墊包括可由銅、鎳、鈦、鈀、或類似物、或其等的合金。根據一些實施例，頂部金屬焊墊50在鈍化層52中。根據替代實施例，可形成聚合物層52(其可為聚酰亞胺、聚苯並噁唑(PBO)、或類似物)，頂部金屬焊墊50位於聚合物層中。
在元件晶圓30的頂部上沉積接合層54，因此為元件晶圓30的頂部表面層。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程204。可由選自用於形成接合層24的同一組候選材料的材料形成接合層54。舉例而言，接合層54可選自氧化矽(SiO2)、SiN、SiON、SiOCN、SiC、SiCN、或類似物，或其等的組合。接合層24及54的材料可彼此相同或彼此不同。根據一些實施例，接合層54具有在約1000Å與約10000Å之間的範 圍內的厚度。
參照第2圖，將元件晶圓30翻轉，並接合至載體晶圓20，將接合層54接合至接合層24。可通過熔融進行接合。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程206。根據一些實施例，元件晶圓30與載體晶圓20的接合包括在包含氧氣(O2)及/或氮氣(N2)的製程氣體中預處理接合層24及54，進行將接合層24及54結合在一起的預接合製程，並在預接合製程之後進行退火製程。根據一些實施例，在預接合製程期間，元件晶圓30與載體晶圓20接觸，施加壓力以將元件晶圓30壓制靠著在載體晶圓20。
在預鍵合製程之後，進行退火製程。可形成Si-O-Si鍵以將接合層24及54結合在一起，以便將接合層24及54以高接合強度彼此接合。根據一些實施例，退火製程在約250℃與約400℃之間的溫度下進行。退火持續時間可在約30分鐘與約60分鐘之間的範圍內。根據一些實施例，如第2中所圖示，元件晶圓30在下方的載體晶圓20之上並接合至下層的載體晶圓。根據替代實施例，元件晶圓30位於上層載體晶圓20下層並接合至上層的載體晶圓，在接合之後，將接合結構翻轉，第2圖中圖示所得的結構。
參照第3圖，將聚合物層58分配至基材22與基材32之間的間隙中，及互連接結構40的側壁上。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的 製程208。根據一些實施例，由聚酰亞胺、PBO、或類似物形成聚合物層58或聚合物層包括聚酰亞胺、PBO、或類似物。以可流動的形式分配聚合物層58，接著固化並固態化。進一步地，聚合物層58分配持完全地環繞基材22與基材32之間的區的環。
參照第4圖，從元件晶圓30的後側進行後側研磨製程，並將基材32薄化。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程210。可通過CMP製程或機械拋光製程進行後側研磨製程。在後側研磨製程中，聚合物層58具有防止元件晶圓30從載體晶圓20剝離的功能。此外，研磨製程及後續的清潔製程可能涉及使用水，且聚合物層58可阻止濕氣從介電層46的側壁穿透至互連接結構40中，並可防止元件晶圓30中的介電層及金屬特徵的劣化。
接著進行邊緣修整製程以去除聚合物層58及元件晶圓30的邊緣部分。亦可去除載體晶圓10的一些邊緣部分。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程212。所得結構如第5圖中所圖示，其中晶圓30的側壁從晶圓20的相應邊緣橫向地凹陷。根據一些實施例，修整寬度W1可在約2mm與約4mm之間的範圍內。進一步地，在修整製程中，可修整基材22的頂部部分形成為延伸至基材22中的凹陷60。凹陷60的深度D1可在約50μm與約200μm之間的範圍內。凹陷60形成環繞基材22頂部部分的凹陷環。
在後續的製程中，可進一步薄化基材32。根據替代實施例，跳過基材32的進一步薄化。根據一些實施例，在乾式蝕刻製程中薄化基材32，該製程可為各向異性蝕刻製程或各向同性蝕刻製程。根據替代實施例，可通過乾式蝕刻製程接著為濕式蝕刻製程進行蝕刻。舉例而言，可使用包含氟(F2)、氯(Cl2)、氯化氫(HCl)、溴化氫(HBr)、溴(Br2)、C2F6、CF4、SO2、混合物的蝕刻氣體進行乾式蝕刻製程。HBr、Cl2、及O2的混合物，或HBr、Cl2、O2、及CH2F2等的混合物。若有的話，可使用KOH、四甲基氫氧化銨(TMAH)、CH3COOH、NH4OH、H2O2、異丙醇(IPA)、HF、HNO3、H2O、或類似物的溶液進行濕式蝕刻製程。
根據替代實施例，可通過CMP製程或機械研磨製程進行基材32的薄化。在先前已形成通孔65(第8圖)以延伸至半導體基材32中的實施例中，通過薄化製程暴將露貫穿通孔65。
第6圖例示保護層62的形成，該保護層亦為隔離層。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程214。根據一些實施例，保護層62包括下子層62A，並可或可不包含上子層62B。將與元件晶圓30及載體晶圓20物理接觸的下子層62A形成為無氧層，其可為無氧介電層。用於形成下子層62A的前驅物亦不含氧及水。根據一些實施例，由SiN、SiC、SiCN、或類似物形成下子層62A或下子層包括SiN、SiC、SiCN、或 類似物。
下子層62A的形成可包含似型沉積製程諸如CVD、ALD、或類似者。據此，將下子層62A形成為似型層，舉例而言，下子層62A的不同部分具有小於約20百分比的變化。下子層62A的厚度T1可足夠大，以便它可充當阻擋層以防止氧及濕氣在上子層62B的形成期間穿透通過下子層。根據一些實施例，下子層62A的厚度T1可大於約100Å，並可在約100Å與約1000Å之間的範圍內。下子層62A對晶圓20及30具有良好的黏附性。
根據一些實施例，在下子層62A上沉積上子層62B。將上子層62B形成為含氧層，其可為含氧介電層。根據一些實施例，由SiO2、SiOC、SiON、SiOCN、或類似物形成上子層62B或上子層包括SiO2、SiOC、SiON、SiOCN、或類似物。用於形成上子層62B的前驅物可包含諸如矽烷、乙矽烷、或類似物的含矽前驅物，及諸如O2、臭氧、或類似物的含氧前驅物。形成製程可包含似型沉積製程，諸如CVD、ALD、或類似者。據此，將上子層62B形成為似型層，舉例而言，上子層62B的不同部分具有小於約20百分比的變化。上子層62B的厚度T2可足夠大，以便它可充當阻擋層以防止外側環境中的氧氣及濕氣穿透通過上子層。根據一些實施例，上子層62B可具有大於大約100Å的厚度T2，且厚度T2可在約100Å與約1000Å之間的範圍內。
上子層62B，當為含氧層諸如氧化矽層時，具有 良好的阻氧能力，可阻擋空氣中的氧氣及濕氣到達互連接結構40。另一方面，用於形成上子層62B的前驅物可包含氧，因此上子層62B的形成可能致使介電層46的劣化且可能氧化元件晶圓30中的金屬特徵。因此形成下子層62A以防止形成上子層62B中的含氧前驅物到達元件晶圓30。據此，隨著雙層保護層62的形成，元件晶圓30在隔離層62形成期間及之後二者均與氧氣及濕氣隔離。
根據一些實施例，下子層62A及上子層62B中的每個均具有均勻的組成，這意指當沉積時，下子層62A及上子層62B中的每個中的元素的原子百分比為均勻的。據此，下子層62A及上子層62B中的每個中的對應前驅物的流動速率為均勻的。根據替代實施例，在上子層62B與下子層62A之間，形成第三(中間)子層。第三子層具有從下子層62A的組成逐漸過渡至上子層62B的組成的逐漸改變的組成。舉例而言，當下子層62A為氮化矽層且上子層62B為氧化矽層時，在進行第三子層的沉積製的進行期間，在第三子層的沉積中，用於沉積下子層62A的含氮前驅物的流動速率逐漸減少，而用於沉積上子層62B的含氧前驅物的流動速率逐漸增加，直到某一點，含氮前驅物關閉。由此一點開始，開始沉積上子層62B。
根據一些實施例，與上子層62B相比，下子層62A具有較低的氧原子百分比及較高的氮或碳原子百分比。上子層62B具有比下子層62A更好的隔離能力。根據一些實施例，下子層62A及上子層62B中的每個可包括SiOC 或SiON，除了下子層62A中的氧原子百分比低於上子層62B中的氧原子百分比。
第7圖例示保護層62的水平部分的去除，以便元件晶圓30的頂部表面被暴露。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程216。根據一些實施例，進行CMP製程以去除與元件晶圓30重疊的保護層62的第一部分。可進行蝕刻製程以去除與載體晶圓20中，重疊並接觸基材22的保護層62的第二部分。根據替代實施例，並未去除保護層62的第二部分，而是留在元件晶圓20上。將虛線區63例示成顯示，保護層62的第二部分可能存在或可能不存在於該區中。根據替代實施例，通過一個或複數個各向異性蝕刻製程進行保護層62的水平部分的去除。根據此等實施例，與元件晶圓30重疊的保護層62的水平部分及與載體晶圓20重疊的保護層62的水平部分二者均被去除。
其餘的保護層62形成環繞並接觸元件晶圓30的完整的環。保護層62具有防止元件晶圓30中的層剝離的功能。此外，保護層62防止濕氣及氧氣從它們的側壁穿透至元件晶圓30中。
參照第8圖，舉例而言，在似型沉積製程中形成介電層64，該製程可為ALD製程、CVD製程、或類似者。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程218。根據一些實施例，由氧化矽、氮化矽、氧化矽、氧氮化矽、或類似物形成介電層64或介電層包括 氧化矽、氮化矽、氧化矽、氧氮化矽、或類似物。可形成貫穿通孔65以穿透基材32，並電性地連接至積體電路裝置34。形成製程可包含蝕刻介電層64及基材32以形成貫穿開口。可在互連接結構40中的金屬焊墊上停止蝕刻。接下來，形成隔離層以圍繞每個貫穿開口。形成製程可包含沉積延伸至貫穿開口中的似型介電層，接著進行各向異性蝕刻製程以重新暴露金屬焊墊。接著沉積導電材料以填充貫穿開口，接著進行平坦化製程以去除貫穿開口之外的多餘導電材料。導電材料(等)的其餘部分為貫穿通孔65。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程220。
根據替代的實施例，已在先前形成貫穿通孔65(舉例而言，在第1圖中所圖示的製程中)。據此，在第8圖中所圖示的製程中，可對基材32進行後側研磨製程及回蝕製程，以便貫穿通孔65的頂部部分突出高於基材32的凹陷頂部表面。接著沉積介電層64，隨後進行光CMP製程以重新暴露貫穿通孔65。
如第8圖中所圖示，介電層64在保護層62的外側壁上延伸。介電層64可進一步延伸並接觸基材22的頂部表面。反之，當並未去除保護層62的此等部分時，介電層64在虛線區63(第7圖)中的保護層62的水平部分上延伸並接觸其頂部表面。
參照第9圖，形成後側互連接結構68，其包含一個或複數個介電層72及一個或複數個層的重佈線層 (RDL)70。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程222。根據一些實施例，通過鑲嵌製程形成重佈線層70，其包含沉積對應的介電層72，在介電層72中形成溝槽及通孔開口，及採用金屬材料填充溝槽與通孔開口以形成重佈線層70。可由無機介電材料形成介電層72或介電層包括無機介電材料，諸如氧化矽、氮化矽、氧氮化矽、或類似物。
根據替代實施例，可由聚合物形成介電層72，該聚合物可為光敏感的，且RDL層的形成製程可包含沉積金屬種子層，在金屬種子層上形成及圖案化鍍覆遮罩，進行鍍覆製程以形成RDL，去除鍍覆遮罩以暴露金屬種子層的下層部分，並蝕刻金屬種子層的暴露部分。
根據一些實施例，在元件晶圓30的後表面上形成電性連接器76。電性連接器76可包含金屬凸塊、金屬焊墊、焊料區、或類似物。根據一些實施例，電性連接器76突出高於表面介電層72的頂部表面。根據替代實施例，電性連接器76的頂部表面與表面介電層72共平面。
根據一些實施例，去除載體晶圓20。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程224。根據一些實施例，將第9圖中所圖示結構的頂部側表面黏附至膠帶，且上下翻轉倒置該結構。接著去除基材22，這可通過CMP製程、機械研磨製程、蝕刻製程、或其等的組合。可去除，或可不去除接合層24。當去除接合層24時，將暴露接合層54。第10圖例示所得的結構。
亦如第10圖中所圖示，在元件晶圓30的前側上形成電性連接器78。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程226。形成製程可包含蝕刻接合層54以形成開口，以便暴露金屬焊墊50，及形成延伸至開口中以電性地連接至金屬焊墊50的電性連接器78。
根據一些實施例，元件晶圓30可在裸晶鋸切製程中單片化以形成分立元件裸晶30’。藉由裸晶鋸切製程去除保護層62，且不存在於所得元件裸晶30'中。根據替代實施例，另一元件晶圓接合至晶圓30以形成重構晶圓，其被單片化以將元件裸晶30'彼此分離，其中每個元件裸晶30'與另一個裝置中的一個或複數個其他元件晶圓接合。
第11圖例示包含與元件裸晶82接合的元件裸晶30’的封裝80。將相應的製程例示成如第15圖中所圖示的製程流程圖200中的製程228。可分配封裝劑84以封裝元件裸晶82。封裝劑84可為模塑化合物、模塑底部填充物、或類似物。將封裝組件88接合至元件裸晶30’。封裝組件88可為印刷電路板、封裝基材、或類似物。可將底部填充物86設置在元件裸晶30’和封裝組件88之間。
根據替代實施例，元件裸晶82不為在去除基材22(第9圖)之後接合至元件裸晶30’，而是在去除基材22之前接合至未鋸切元件晶圓30中的元件裸晶30’。據此，如第11圖中所圖示的元件裸晶82可被接合至第9圖中所圖示的結構，接著進行封裝製程以形成重構晶圓，其包含 載體晶圓20、元件晶圓30、元件裸晶82、及封裝劑84(第11圖)。接著可進行後續製程以形成第11圖中所圖示的結構。
第12圖至第14圖例示根據本揭露內容的替代實施例，封裝的形成中的中間階段的截面視圖。此等實施例類似於第1圖至第11圖中所示的實施例，除了不同之處在於保護層62為單層。除非另作說明，此等實施例中的組件的材料及形成製程與第1圖至第11圖中所圖示的前述實施例中的類似部件大致上相同，此等組件用相同的元件符號表示。因此可在前述實施例的論述中發現關於第12圖至第14圖中所圖示的組件的形成製程及材料的細節。
此等實施例的最初製程與第1圖至第5圖中所圖示的大致上相同。接下來，如第12圖中所圖示，沉積保護層62。根據一些實施例，保護層62為均質層，整個保護層62由均質材料所形成。由無氧材料形成保護層62，前驅物亦不含氧。舉例而言，可使用與形成下子層62A(第6圖)大致上相同的方法形成保護層62。由於保護層62的形成不含氧，在保護層62的形成中，不會有含氧製程氣體穿透並劣化元件晶圓30。
第13圖例示保護層62的水平部分的去除，這可通過平坦化製程、各向異性蝕刻製程、或兩者兼而有之。第14圖例示在元件晶圓30的後側上，後側互連接結構的形成。相應製程與參照第9圖所論述者大致上相同。後續製程與參照第10及11圖所論述者大致上相同，在本文中 不再贅述。
本揭露內容的實施例具有一些有利的特徵。藉由形成包含兩個或更多個子層的雙層保護層或更多層保護層，保護層的下層不含氧，且其形成(製程)不會劣化在元件晶圓中的低k值介電層及金屬特徵。上層具有良好的氧氣及濕氣隔離能力，且可阻止氧氣及濕氣在後續製程中穿透至元件晶圓中。據此，改善保護層的氧氣及濕氣隔離能力。
根據本揭露內容的一些實施例，方法包括以下步驟：將晶圓接合至第二晶圓；在第一晶圓上進行修整製程，其中第一晶片的邊緣部分被去除，並且在修整製程之後，第一晶圓具有從第二晶圓的第二側壁橫向地凹陷的第一側壁；沉積與第一晶圓的側壁接觸的保護層，其中沉積保護層之步驟包括沉積與第一側壁接觸的非含氧材料之步驟；去除與第一晶圓重疊的保護層的水平部分；及在第一晶圓之上形成互連接結構，其中互連接結構電性地連接至第一晶圓中的積體電路元件。
在實施例中，沉積保護層之步驟包括沉積由非含氧材料形成的第一子層之步驟；及在第一子層上沉積第二子層之步驟，其中第二子層由不同於非含氧材料的材料形成。在實施例中，沉積第二子層之步驟包括沉積含氧材料之步驟。在實施例中，沉積第一子層之步驟包包括沉積氮化矽之步驟，及沉積第二子層包括沉積氧化矽之步驟。在實施例中，方法進一步包括以下步驟：在沉積第一子層之步驟與沉積第二子層之步驟之間，沉積第三子層，其中在沉積 第三子層期間，製程氣體逐漸從用於沉積第一子層的第一製程氣體轉變成用於沉積第二個子層的第二製程氣體。
在實施例中，整個保護層包括非含氧材料。在實施例中，方法進一步包括以下步驟：在形成互連接結構之後，從第一晶圓去除第二晶圓。在實施例中，方法進一步包括以下步驟：在第一晶圓上進行單片化製程以將第一晶圓分離成複數個元件裸晶。在實施例中，複數個元件裸晶不含保護層的其餘部分。在實施例中，保護層形成為似型層。在實施例中，去除保護層的水平部分之步驟包括進行各向異性蝕刻製程之步驟。在實施例中，去除保護層的水平部分之步驟包括進行拋光製程之步驟。
根據本揭露內容的一些實施例，方法包括以下步驟：將元件晶圓接合在載體晶圓之上；薄化元件晶圓的半導體基材；修整元件晶圓，其中修整元件晶圓的邊緣部分；在元件晶圓及載體晶圓上沉積保護層，其中沉積保護層之步驟包括以下步驟：沉積包括第一材料的第一子層；及沉積包括不同於第一材料的第二材料的第二子層；露出元件晶圓的頂部表面；及在元件晶圓之上形成互連接結構，其中互連接結構電性地連接至元件晶圓中的積體電路元件。
在實施例中，第一子層具有比第二子層更低的氧原子百分比。在實施例中，第二子層具有比第一子層具有更好的氧阻擋能力。在實施例中，方法進一步包括以下步驟：在沉積保護層之後，形成穿透半導體基材的貫穿通孔以電性地連接至半導體基材下層的導電特徵。在實施例中，形 成互連接結構之步驟包括以下步驟：在元件晶圓上沉積介電層，其中介電層在保護層的側壁上延伸。
根據本揭露內容的一些實施例，方法包括以下步驟：在載體晶圓之上接合元件晶圓，其中元件晶圓中的第一介電層接合至載體晶圓中的第二介電層；修整元件晶圓，其中元件晶圓中的第一半導體基材的一部分被修整，且載體晶圓中的第二基材的頂部表面被暴露；在元件晶圓及載體晶圓上沉積保護層，其中沉積保護層的步驟使用其中不含氧製程氣體進行；從元件晶圓及載體晶圓去除保護層的水平部分；及去除第二基材。在實施例中，沉積保護層之步驟包括沉積氮化矽層之步驟。在實施例中，沉積保護層之步驟進一步包括在氮化矽層之上沉積氧化矽層之步驟。
上述概述數種實施例的特徵，以便熟習此項技藝者可更瞭解本揭露內容的態樣。熟習此項技藝者應當理解，熟習此項技藝者可輕易地使用本揭露內容作為設計或修改其他製程及結構之基礎，以實現本文中所介紹之實施例的相同目的及/或達成相同優點。熟習此項技藝者亦應當認知，此均等構造不脫離本揭露內容的精神及範圍，且在不脫離本揭露內容之精神及範圍之情況下，熟習此項技藝者可在本文中進行各種改變、替換、及變更。
20:載體晶圓
22,32:基材
24,54:接合層
30:元件晶圓
34:積體電路元件
36,46:層間介電質
38:接觸柱塞
40:互連接結構
42:金屬線路
44,65:通孔
50:頂部金屬焊墊
52:聚合物層
62:保護層
63:虛線區
64:介電層
65:貫穿通孔
68:後側互連接結構
70:重佈線層
72:介電層
76,78:電性連接器

Claims (10)

  1. 一種半導體元件的製作方法，包括以下步驟：將一第一晶圓接合至第二晶圓；在該第一晶圓上進行一修整製程，其中第一晶片的邊緣部分被去除，並且在修整製程之後，該第一晶圓具有從一第二晶圓的一第二側壁橫向地凹陷的一第一側壁；沉積與該第一晶圓的一側壁接觸的一保護層，其中該沉積該保護層之步驟包括沉積與該第一側壁接觸的一非含氧材料之步驟，且其中該沉積該保護層之步驟包括以下步驟：沉積由該非含氧材料形成的一第一子層；及在該第一子層上沉積一第二子層，其中該第二子層由不同於該非含氧材料的一材料形成；去除與該第一晶圓重疊的該保護層的一水平部分；及在該第一晶圓之上形成一互連接結構，其中該互連接結構電性地連接至該第一晶圓中的一積體電路元件。
  2. 如請求項1所述之方法，進一步包括以下步驟：在形成該互連接結構之後，從該第一晶圓去除該第二晶圓。
  3. 如請求項1所述之方法，其中該沉積該第二子層之步驟包括一沉積含氧材料之步驟。
  4. 如請求項3所述之方法，其中該沉積該第一子層之步驟包包括沉積氮化矽之步驟，及該沉積該第二子層包括沉積氧化矽之步驟。
  5. 如請求項1所述之方法，進一步包括以下步驟：在該沉積該第一子層之步驟與該沉積該第二子層之步驟之間，沉積一第三子層，其中在該沉積該第三子層期間，製程氣體逐漸從用於沉積第一子層的第一製程氣體轉變成用於沉積該第二個子層的第二製程氣體。
  6. 一種半導體元件的製作方法，包括以下步驟：將一元件晶圓接合在一載體晶圓之上；薄化該元件晶圓的一半導體基材；修整該元件晶圓，其中修整該元件晶圓的一邊緣部分；在該元件晶圓及該載體晶圓上沉積一保護層，其中該沉積該保護層之步驟包括以下步驟：沉積包括一第一材料的一第一子層；及沉積包括不同於該第一材料的一第二材料的一第二子層；露出該元件晶圓的一頂部表面；及在該元件晶圓之上形成該互連接結構，其中該互連接結構電性地連接至該元件晶圓中的積體電路元件。
  7. 如請求項6所述之方法，其中該第一子層具有比該第二子層更低的一氧原子百分比。
  8. 一種半導體元件的製作方法，包括以下步驟：在一載體晶圓之上接合一元件晶圓，其中該元件晶圓中的一第一介電層接合至該載體晶圓中的一第二介電層；修整該元件晶圓，其中該元件晶圓中的一第一半導體基材的一部分被修整，且該載體晶圓中的一第二基材的一頂部表面被暴露；在該元件晶圓及該載體晶圓上沉積一保護層，其中該沉積該保護層的步驟使用其中不含氧製程氣體進行；從該元件晶圓及該載體晶圓去除該保護層的一水平部分；及去除該第二基材。
  9. 如請求項8所述之方法，其中該沉積該保護層之步驟包括沉積一氮化矽層之步驟。
  10. 如請求項9所述之方法，其中該沉積該保護層之步驟進一步包括在該氮化矽層之上沉積一氧化矽層之步驟。
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TW202137394A (zh) * 2019-10-31 2021-10-01 台灣積體電路製造股份有限公司 積體晶片結構及其形成方法以及形成多維積體晶片的方法
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