CN115763263A - 形成半导体结构的方法 - Google Patents
形成半导体结构的方法 Download PDFInfo
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- CN115763263A CN115763263A CN202210553351.XA CN202210553351A CN115763263A CN 115763263 A CN115763263 A CN 115763263A CN 202210553351 A CN202210553351 A CN 202210553351A CN 115763263 A CN115763263 A CN 115763263A
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Abstract
一种形成半导体结构的方法,包括将第一晶圆接合至第二晶圆,以及对第一晶圆执行修整工艺。去除第一晶圆的边缘部分。在修整工艺之后,第一晶圆具有从第二晶圆的第二侧壁横向凹进的第一侧壁。沉积与第一晶圆的侧壁接触的保护层,其中,沉积工艺包括沉积与第一侧壁接触的不含氧材料。该方法还包括去除与第一晶圆重叠的保护层的水平部分,以及在第一晶圆上方形成互连结构,其中,互连结构电连接至第一晶圆中的集成电路器件。
Description
技术领域
本发明的实施例涉及制造形成半导体结构的方法。
背景技术
通常将载体晶圆用作集成电路的封装中的支撑机构。例如,当形成具有穿透器件晶圆的衬底的贯通孔的器件晶圆时,将器件晶圆接合至载体晶圆,从而可以使器件晶圆变薄,并且可以在衬底的背侧上形成电连接件。
发明内容
本发明的一些实施例提供了一种形成半导体结构的方法,包括:将第一晶圆接合至第二晶圆;对所述第一晶圆执行修整工艺,其中,去除所述第一晶圆的边缘部分,并且在所述修整工艺之后,所述第一晶圆具有从所述第二晶圆的第二侧壁横向凹进的第一侧壁;沉积与所述第一晶圆的侧壁接触的保护层,其中,所述沉积所述保护层包括沉积与所述第一侧壁接触的不含氧材料;去除与所述第一晶圆重叠的所述保护层的水平部分;以及在所述第一晶圆上方形成互连结构,其中,所述互连结构电连接至所述第一晶圆中的集成电路器件。
本发明的另一些实施例提供了一种形成半导体结构的方法,包括:在载体晶圆上方接合器件晶圆;减薄所述器件晶圆的半导体衬底;修整所述器件晶圆,其中,修整所述器件晶圆的边缘部分;在所述器件晶圆和所述载体晶圆上沉积保护层,其中,所述沉积所述保护层包括:沉积包括第一材料的第一子层;以及沉积包括与所述第一材料不同的第二材料的第二子层;露出所述器件晶圆的顶表面;以及在所述器件晶圆上方形成互连结构,其中,所述互连结构电连接至所述器件晶圆中的集成电路器件。
本发明的又一些实施例提供了一种形成半导体结构的方法,包括:在载体晶圆上方接合器件晶圆,其中,所述器件晶圆中的第一介电层接合至所述载体晶圆中的第二介电层;修整所述器件晶圆,其中,修整所述器件晶圆中的第一半导体衬底的部分,并且暴露所述载体晶圆中的第二衬底的顶表面;在所述器件晶圆和所述载体晶圆上沉积保护层,其中,使用其中没有氧的工艺气体执行所述沉积所述保护层;从所述器件晶圆和所述载体晶圆去除所述保护层的水平部分;以及去除所述第二衬底。
本发明的一些实施例提供了晶圆接合工艺中无氧保护层的形成。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图11示出了根据一些实施例的晶圆接合工艺和形成封装件中的中间阶段。
图12至图14示出了根据一些实施例的晶圆接合工艺和形成封装件中的中间阶段。
图15示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
提供了封装件及其形成方法。根据本发明的一些实施例,将器件晶圆接合至载体晶圆。减薄器件晶圆,接着进行边缘修整工艺。在器件晶圆的侧壁上形成保护层。根据一些实施例,保护层包括诸如氮化硅层的不含氧层。保护层还可以是包括不含氧层和具有良好隔离湿气能力的层的双层。通过使用不含氧层,降低了对低k介电层和低k介电层中的金属部件的氧化,并且避免了由氧化引起的器件劣化。本文讨论的实施例是为了提供实例以确保制作或使用本发明的主题,并且本领域普通技术人员将容易理解在保持在不同实施例的预期范围内的同时可以进行的修改。在各个视图和示出的实施例中,相似的附图标号用于表示相似的元件。尽管可以将方法实施例讨论为以特定顺序执行,但是可以以任意逻辑顺序执行其他方法实施例。
图1至图11示出了根据本发明的一些实施例的器件晶圆至载体晶圆的接合以及位于器件晶圆的背侧上的背侧互连结构的形成中的中间阶段的截面图。还将相应的工艺示意性地反映在图15所示的流程中。
参考图1,形成晶圆20。根据一些实施例,晶圆20是载体晶圆,并且由此可以被称为载体晶圆20。载体晶圆20可以具有圆形俯视图形状。根据一些实施例,载体晶圆20包括衬底22。衬底22可以由与器件晶圆30中的衬底32相同的材料形成(随后讨论),从而使得在随后的封装工艺中,减小了由于载体晶圆20和器件晶圆30之间的热膨胀系数(CTE)值不匹配带来的翘曲。衬底22可以由硅形成或包括硅,然而也可以使用诸如陶瓷、玻璃、硅酸盐玻璃等的其他材料。根据一些实施例,整个衬底22由均质材料形成,其中没有与均质材料不同的其他材料。例如,整个载体晶圆20可以由硅(掺杂或未掺杂的)形成,并且其中不存在金属区域、介电区域等。
根据可选的实施例,晶圆20是其中包括有源器件(诸如晶体管)和/或无源器件(诸如电容器、电阻器、电感器和/或类似器件)的器件晶圆。当晶圆20是器件晶圆时,也可以是包括连续延伸到晶圆中所有器件管芯中的半导体衬底的未锯切的晶圆,或者可以是包括封装在密封剂(例如模塑料)中的分立器件管芯的重建晶圆。
在衬底22上沉积接合层24。将相应的工艺示出为如图15所示的工艺流程200中的工艺202。根据一些实施例,接合层24由介电材料形成或包括介电材料,该介电材料可以是硅基介电材料,诸如氧化硅(SiO2)、SiN、SiON、SiOCN、SiC、SiCN等,或它们的组合。根据一些实施例,接合层24具有在约至约之间的范围内的厚度。
根据本发明的一些实施例,使用高密度等离子体化学气相沉积(HDPCVD)、等离子体增强化学气相沉积(PECVD)、化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、原子层沉积(ALD)等形成接合层24。
根据一些实施例,接合层24与衬底22物理接触。根据可选的实施例,载体晶圆20包括位于接合层24和衬底22之间的多个层(未示出)。例如,可以存在由诸如氧化硅、磷-硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)等的氧化物基材料(其也可以是氧化硅基的)形成的氧化物基层。还可以存在由氮化硅形成的或包括氮化硅的氮化物基层,同时它还可以是由诸如氮氧化硅(SiON)的其他材料形成或者它可以包括诸如氮氧化硅(SiON)的其他材料。根据本发明的一些实施例,可以使用PECVD、CVD、LPCVD、ALD等形成衬底22和接合层24之间的层。在接合层24和衬底22之间也可以形成对准标记。可以将对准标记形成为可以通过镶嵌工艺形成的金属插塞。
进一步参考图1,形成器件晶圆30。器件晶圆30可以是未锯切的晶圆,并且如图8所示的接合工艺是晶圆-至-晶圆接合工艺。根据一些实施例,器件晶圆30包括衬底32。可以存在从前侧(示出的顶侧)延伸至衬底32中的衬底贯通孔(未示出)。根据可选的实施例,在这个阶段不形成贯通孔,并且在如图8所示的工艺中形成贯通孔。衬底32可以是半导体衬底,诸如硅衬底。根据其他实施例,衬底32可以包括其他半导体材料,诸如硅锗、碳掺杂的硅等。衬底32可以是块状衬底,或者可以具有例如包括硅衬底和位于硅衬底上方的硅锗层的分层结构。
根据一些实施例,器件晶圆30包括器件管芯,其可以包括逻辑管芯、存储器管芯、输入-输出管芯、集成无源器件(IPD)等,或它们的组合。例如,器件晶圆30中的逻辑器件管芯可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、基带(BB)管芯、应用处理器(AP)管芯等。器件晶圆30中的存储器管芯可以包括静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等。器件晶圆30可以是包括在整个器件晶圆30中连续延伸的半导体衬底的简单的器件晶圆,或者可以是包括封装在其中的器件管芯的重建晶圆、包括集成为系统的多个集成电路(或器件管芯)的片上系统(SoC)管芯等。
根据本发明的一些实施例,在半导体衬底32的顶表面上形成集成电路器件34。示例性集成电路器件34可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。在此没有示出集成电路器件34的细节。根据可选的实施例,将器件晶圆30用于形成中介层,其中衬底32可以是半导体衬底或介电衬底。
在半导体衬底32上方形成层间电介质(ILD)36,并且层间电介质(ILD)36填充集成电路器件34中晶体管(未示出)的栅极堆叠件之间的间隔。根据一些示例性实施例,ILD 36由氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)等形成或者ILD 36包括氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)等。可以使用旋涂、可流动化学气相沉积(FCVD)、化学气相沉积(CVD)等来形成ILD 36。根据本发明的一些实施例,使用诸如PECVD、LPCVD等的沉积方法来形成ILD 36。
在ILD 36中形成接触插塞38,并且将接触插塞38用于将集成电路器件34电连接至上面的金属线和通孔。根据本发明的一些实施例,接触插塞38由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金、和/或它们的多层的导电材料形成。接触插塞38的形成可以包括在ILD 36中形成接触开口,将一种(多种)导电材料填充至接触开口中,以及执行平坦化工艺(例如化学机械抛光(CMP)工艺)以使ILD 36的顶表面与接触插塞38的顶表面齐平。
在ILD 36和接触插塞38上方存在有互连结构40。互连结构40包括形成在介电层46中的金属线42和通孔44。在下文中,介电层46可以包括金属间介电(IMD)层46。根据本发明的一些实施例,一些介电层46由具有低于约3.0的介电常数值(k值)的低k介电材料形成。介电层46可以由Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的一些实施例,介电层46的形成包括沉积含致孔剂的介电材料,以及然后执行固化工艺以驱除致孔剂,并且由此剩余的介电层46是多孔的。根据本发明的可选的实施例,一些或全部介电层46由诸如氧化硅、碳化硅(SiC)、碳-氮化硅(SiCN)、氧-碳-氮化硅(SiOCN)等的非低k介电材料形成。在介电层46之间形成可以由碳化硅、氮化硅、氮氧化硅、铝、氧化物、氮化铝等或它们的多层形成的蚀刻停止层(未示出),并且为简单起见未示出蚀刻停止层。
在介电层46中形成金属线42和通孔44。在下文中,将相同水平处的金属线42统称为金属层。根据本发明的一些实施例,互连结构40包括通过通孔44互连的多个金属层。根据路由要求来确定IMD层的数量。例如,可以有5至15个IMD层。
金属线42和通孔44可以由铜或铜合金形成,并且它们也可以由其他金属形成。形成工艺可以包括单镶嵌工艺和双镶嵌工艺。在示例性单镶嵌工艺中,首先在介电层46的一个介电层中形成沟槽,随后用导电材料填充沟槽。然后执行诸如CMP工艺的平坦化工艺以去除高于IMD层的顶表面的一种(多种)导电材料的多余部分,在沟槽中留下金属线。在双镶嵌工艺中,在IMD层中形成沟槽和通孔开口两者,通孔开口位于沟槽下面并连接至沟槽。然后将一种(多种)导电材料填充到沟槽和通孔开口中以分别形成金属线和通孔。一种(多种)导电材料可以包括扩散阻挡层和位于扩散阻挡层上方的含铜金属材料。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽等。
介电层46还可以包括位于低k介电层上方的钝化层。例如,在镶嵌金属线42和通孔44上方可以有未掺杂的硅酸盐玻璃(USG)层、氧化硅层、氮化硅层等。钝化层比低k介电层更致密,并且具有将低k介电层与有害化学物质和气体,诸如湿气,隔离的功能。
根据一些实施例,可以在互连结构40上方形成有顶部金属焊盘50,以及将顶部金属焊盘50通过金属线42和通孔44电连接至集成电路器件34。顶部金属焊盘50可以由铜、镍、钛、钯等或它们的合金形成或者顶部金属焊盘50可以包括铜、镍、钛、钯等或它们的合金。根据一些实施例,顶部金属焊盘50位于钝化层52中。根据可选的实施例,可以形成聚合物层52(其可以是聚酰亚胺、聚苯并恶唑(PBO)等),使顶部金属焊盘50位于该聚合物层中。
在器件晶圆30的顶部上沉积接合层54,并且由此接合层54是器件晶圆30的顶部表面层。将相应的工艺示出为如图15所示的工艺流程200中的工艺204。接合层54可以由选自用于形成接合层24的候选材料的相同组的材料形成。例如,接合层54可以选自氧化硅(SiO2)、SiN、SiON、SiOCN、SiC、SiCN等,或它们的组合。接合层24和54的材料可以彼此相同或彼此不同。根据一些实施例,接合层54具有在约至约之间的范围内的厚度。
参考图2,将器件晶圆30翻转倒置,并且用接合层54接合至接合层24将器件晶圆30接合至载体晶圆20。可以通过熔融接合来执行该接合。将相应的工艺示出为如图15所示的工艺流程200中的工艺206。根据一些实施例,器件晶圆30与载体晶圆20的接合包括在包含氧(O2)和/或氮(N2)的工艺气体中预处理接合层24和54,执行预接合工艺以将接合层24和54结合在一起,以及在预粘合工艺之后执行退火工艺。根据一些实施例,在预接合工艺期间,随着施加压力以将器件晶圆30压靠载体晶圆20,使器件晶圆30与载体晶圆20接触。
在预接合工艺之后,执行退火工艺。可以形成Si-O-Si键以将接合层24和54结合在一起,从而使得接合层24和54以高接合强度彼此接合。根据一些实施例,在约250℃至约400℃之间的温度下执行退火工艺。退火持续时间可以在约30分钟至约60分钟之间的范围内。根据一些实施例,如图2所示,器件晶圆30位于载体晶圆20上方并且接合至下面的载体晶圆20。根据可选的实施例,将器件晶圆30位于载体晶圆20下面并且接合至上面的载体晶圆20,并且在接合之后,将接合结构翻转,以及生成的结构如图2所示。
参考图3,将聚合物层58分配到衬底22和衬底32之间的间隙中,以及互连结构40的侧壁上。将相应的工艺示出为如图15所示的工艺流程200中的工艺208。根据一些实施例,聚合物层58由聚酰亚胺、PBO等形成或者聚合物层58包括聚酰亚胺、PBO等。将聚合物层58以可流动的形式分配,以及然后固化(cured)和凝固(solidified)。此外,将聚合物层58分配为完全环绕衬底22和衬底32之间的区域的环。
参考图4,从器件晶圆30的背侧执行背侧研磨工艺,并且减薄衬底32。将相应的工艺示出为如图15所示的工艺流程200中的工艺210。可以通过CMP工艺或机械抛光工艺来执行背侧研磨工艺。在背侧研磨工艺中,聚合物层58具有防止器件晶圆30从载体晶圆20剥离的功能。另外,研磨工艺和随后的清洁工艺可能涉及水的使用,并且聚合物层58可以阻止湿气从介电层46的侧壁穿透至互连结构40中,并且可以防止器件晶圆30中的介电层和金属部件的劣化。
然后执行边缘修整工艺以去除聚合物层58和器件晶圆30的边缘部分。还可以去除载体晶圆20的一些边缘部分。将相应的工艺示出为如图15所示的工艺流程200中的工艺212。生成的结构在图5中示出,其中,晶圆30的侧壁从晶圆20的对应边缘横向凹进。根据一些实施例,修整宽度W1可以在约2mm至约4mm之间的范围内。此外,在修整工艺中,可以修整衬底22的顶部部分以形成延伸至衬底22中的凹槽60。凹槽60的深度D1可以在约50μm至约200μm之间的范围内。凹槽60形成环绕衬底22顶部部分的凹槽环。
在随后的工艺中,可以进一步减薄衬底32。根据可选的实施例,跳过衬底32的进一步减薄。根据一些实施例,在干蚀刻工艺中减薄衬底32,该干蚀刻工艺可以是各向异性蚀刻工艺或各向同性蚀刻工艺。根据可选的实施例,可以通过干蚀刻工艺以及随后的湿蚀刻工艺来执行蚀刻。例如,可以使用包括氟(F2)、氯(Cl2)、氯化氢(HCl)、溴化氢(HBr)、溴(Br2)、C2F6、CF4、SO2、HBr和Cl2、O2的混合物、HBr和Cl2、O2、CH2F2的混合物等的蚀刻气体来执行干蚀刻工艺。如果有的话,可以使用KOH、四甲基氢氧化铵(TMAH)、CH3COOH、NH4OH、H2O2、异丙醇(IPA)、HF和HNO3、H2O的溶液等来执行湿蚀刻工艺。
根据可选的实施例,可以通过CMP工艺或机械研磨工艺来执行衬底32的减薄。在先前已经形成贯通孔65(图8)以延伸到半导体衬底32中的实施例中,将通过减薄工艺暴露贯通孔65。
图6示出了也是隔离层的保护层62的形成。将相应的工艺示出为如图15所示的工艺流程200中的工艺214。根据一些实施例,保护层62包括下部子层62A,并且可以或可以不包括上部子层62B。与器件晶圆30和载体晶圆20物理接触的下部子层62A形成为无氧层,其可以是无氧介电层。用于形成下部子层62A的前体也没有氧和水。根据一些实施例,下部子层62A由SiN、SiC、SiCN等形成或者下部子层62A包括SiN、SiC、SiCN等。
下部子层62A的形成可以包括共形沉积工艺,例如CVD、ALD等。因此,下部子层62A形成为共形层,例如,下部子层62A的不同部分具有小于约20%的变化。下部子层62A的厚度T1可以足够大,从而使得它可以充当阻挡层以在上部子层62B的形成期间防止氧和湿气穿透它。根据一些实施例,下部子层62A的厚度T1可以大于约并且可以在约至约之间的范围内。下部子层62A具有对晶圆20和30的良好粘附性。
根据一些实施例,在下部子层62A上沉积上部子层62B。上部子层62B形成为含氧层,其可以是含氧介电层。根据一些实施例,上部子层62B由SiO2、SiOC、SiON、SiOCN等形成或者上部子层62B包括SiO2、SiOC、SiON、SiOCN。用于形成上部子层62B的前体可以包括诸如硅烷、二硅烷等的含硅前体,以及诸如O2、臭氧等的含氧前体。形成工艺可以包括诸如CVD、ALD等的共形沉积工艺。因此,上部子层62B形成为共形层,例如,上部子层62B的不同部分具有小于约20%的变化。上部子层62B的厚度T2可以足够大,从而使得它可以充当阻挡层以防止外部环境中的氧和湿气穿透它。根据一些实施例,上部子层62B可以具有大于约的厚度T2,并且厚度T2可以在约至约之间的范围内。
在上部子层62B为诸如氧化硅层的含氧层时,上部子层62B具有良好的用于阻止空气中的氧和湿气到达互连结构40的阻氧能力。另一方面,用于形成上部子层62B的前体可以包括氧,并且由此上部子层62B的形成可能导致介电层46的劣化并且可能氧化器件晶圆30中的金属部件。由此形成下部子层62A以防止在上部子层62B的形成中的含氧前体到达器件晶圆30。因此,由于双层保护层62的形成,器件晶圆30在隔离层62的形成期间和之后都与氧和湿气隔离。
根据一些实施例,下部子层62A和上部子层62B中的每个都具有均匀的组成,这意味着当沉积时,下部子层62A和上部子层62B中的每个中的元素的原子百分比是均匀的。因此,下部子层62A和上部子层62B中的每个中的对应前体的流速是均匀的。根据可选的实施例,在上部子层62B和下部子层62A之间,形成第三(中间)子层。第三子层具有从下部子层62A的组成逐渐过渡到上部子层62B的组成的逐渐改变的组成。例如,当下部子层62A是氮化硅层并且上部子层62B是氧化硅层时,在进行第三子层的沉积期间,在第三子层的沉积中,逐渐降低用于沉积下部子层62A的含氮前驱体的流速,并且逐渐增加用于沉积上部子层62B的含氧前体的流速,直到在某个时刻处,关闭含氮前体。从这个时刻开始,开始沉积上部子层62B。
根据一些实施例,下部子层62A具有比上部子层62B更低的氧原子百分比和更高的氮或碳原子百分比。上部子层62B具有比下部子层62A更好的隔离能力。根据一些实施例,下部子层62A和上部子层62B中的每个可以包括SiOC或SiON,只是下部子层62A中的氧原子百分比低于上部子层62B中的氧原子百分比。
图7示出了保护层62的水平部分的去除,从而使器件晶圆30的顶表面暴露。将相应的工艺示出为如图15所示的工艺流程200中的工艺216。根据一些实施例,执行CMP工艺以去除与器件晶圆30重叠的保护层62的第一部分。可以执行蚀刻工艺以去除与载体晶圆20中的衬底22重叠并接触的保护层62的第二部分。根据可选的实施例,不去除保护层62的第二部分,并且将保护层62的第二部分留在器件晶圆20上。示出虚线区域63以显示保护层62的第二部分可以存在或者可以不存在于这个区域中。根据可选的实施例,通过一个或多个各向异性蚀刻工艺来执行保护层62的水平部分的去除。根据这些实施例,去除与器件晶圆30重叠的保护层62的水平部分和与载体晶圆20重叠的保护层62的水平部分两者。
剩余的保护层62形成环绕并接触器件晶圆30的完整环。保护层62具有防止器件晶圆30中的层剥离的功能。同样,保护层62防止湿气和氧从它们的侧壁穿透到器件晶圆30中。
参考图8,例如在共形沉积工艺中形成介电层64,该共形沉积工艺可以是ALD工艺、CVD工艺等。将相应的工艺示出为如图15所示的工艺流程200中的工艺218。根据一些实施例,介电层64由氧化硅、氮化硅、氧化硅、氮氧化硅等形成或者介电层64包括氧化硅、氮化硅、氧化硅、氮氧化硅等。可以形成贯通孔65以穿透衬底32,并且将贯通孔65电连接至集成电路器件34。形成工艺可以包括蚀刻介电层64和衬底32以形成贯通开口。该蚀刻可以停止在互连结构40中的金属焊盘上。接下来,形成隔离层以环绕每个贯通开口。形成工艺可以包括沉积延伸到贯通开口中的共形介电层,以及然后执行各向异性蚀刻工艺以再暴露金属焊盘。然后沉积一种(多种)导电材料以填充贯通开口,随后进行平坦化工艺以去除贯通开口外部的多余导电材料。该一种(多种)导电材料的剩余部分是贯通孔65。将相应的工艺示出为如图15所示的工艺流程200中的工艺220。
根据可选的实施例,先前已经形成贯通孔65(例如,在图1中所示的工艺中)。因此,在图8所示的工艺中,可以对衬底32执行背侧研磨工艺和回蚀刻工艺,从而使得贯通孔65的顶部部分突出高于衬底32的凹进的顶表面。然后沉积介电层64,随后进行光CMP工艺以再暴露贯通孔65。
如图8所示,介电层64在保护层62的外侧壁上延伸。介电层64还可以在衬底22的顶表面上延伸并接触衬底22的顶表面。相反,当没有去除保护层62的这些部分时,介电层64在虚线区域63(图7)中的保护层62的水平部分的顶表面上延伸并接触虚线区域63(图7)中的保护层62的水平部分的顶表面。
参考图9,形成包括一层或多层介电层72和一层或多层再分布线(RDL)70的背侧互连结构68。将相应的工艺示出为如图15所示的工艺流程200中的工艺222。根据一些实施例,通过镶嵌工艺形成RDL 70,该镶嵌工艺包括沉积对应的介电层72,在介电层72中形成沟槽和通孔开口,以及用一种(多种)金属材料填充沟槽和通孔开口以形成RDL 70。介电层72可以由诸如氧化硅、氮化硅、氮氧化硅等的无机介电材料形成或者介电层72包括诸如氧化硅、氮化硅、氮氧化硅等的无机介电材料。
根据可选的实施例,介电层72可以由可以是光敏的聚合物形成,并且RDL层的形成工艺可以包括沉积金属晶种层、在金属晶种层上方形成镀掩模并图案化该镀掩模,执行镀工艺以形成RDL,去除镀掩模以暴露金属晶种层的下面部分,以及蚀刻金属晶种层的暴露部分。
根据一些实施例,在器件晶圆30的背面上形成电连接件76。电连接件76可以包括金属凸块、金属焊盘、焊料区域等。根据一些实施例,电连接件76突出高于表面介电层72的顶表面。根据可选的实施例,电连接件76的顶表面与表面介电层72共面。
根据一些实施例,去除载体晶圆20。将相应的工艺示出为如图15所示的工艺流程200中的工艺224。根据一些实施例,将图9所示结构的顶侧粘附至带,并且将该结构翻转倒置。然后去除衬底22,这可以通过CMP工艺、机械研磨工艺、蚀刻工艺或它们的组合。可以去除接合层24,或者可以不去除接合层24。当去除接合层24时,将暴露接合层54。图10示出了生成的结构。
同样如图10所示,在器件晶圆30的前侧上形成电连接件78。将相应的工艺示出为如图15所示的工艺流程200中的工艺226。形成工艺可以包括蚀刻接合层54以形成开口,从而使金属焊盘50暴露,以及形成延伸到开口中以电连接至金属焊盘50的电连接件78。
根据一些实施例,器件晶圆30可以在管芯锯切工艺中被分割(singulated)以形成分立器件管芯30’。通过管芯锯切工艺去除保护层62,并且保护层62不存在于生成的器件管芯30’中。根据可选的实施例,将另一器件晶圆接合至晶圆30以形成重建晶圆,该重建晶圆被切割以将器件管芯30’彼此分隔开,将每个器件管芯30’与另一个器件晶圆中的一个或多个其它器件管芯接合。
图11示出了包括与器件管芯82接合的器件管芯30’的封装件80。将相应的工艺示出为如图15所示的工艺流程200中的工艺228。可以分配密封剂84以密封器件管芯82。密封剂84可以是模塑料、模塑底部填充物等。将封装组件88接合至器件管芯30’。封装组件88可以是印刷电路板、封装衬底等。底部填充物86可以设置在器件管芯30’和封装组件88之间。
根据可选的实施例,器件管芯82不是在去除衬底22(图9)之后接合至器件管芯30’,而是在去除衬底22之前接合至未锯切的器件晶圆30中的器件管芯30’。因此,如图11所示的器件管芯82可以接合至图9所示的结构,随后进行封装工艺以形成包括载体晶圆20、器件晶圆30、器件管芯82和密封剂84(图11)的重建晶圆。然后可以执行后续工艺以形成图11所示的结构。
图12至图14示出了根据本发明的可选实施例的封装件的形成中的中间阶段的截面图。除了保护层62是单层之外,这些实施例类似于图1至图11中所示的实施例。除非另有说明,这些实施例中的组件的材料和形成工艺与图1至图11所示的前述实施例中由相似的参考标号表示的相似的组件基本相同。由此,可以在前述实施例的讨论中找到关于图12至图14中所示组件的形成工艺和材料的细节。
这些实施例的初始工艺与图1至图5所示的基本相同。接着,如图12所示,沉积保护层62。根据一些实施例,保护层62是均质层,整个保护层62由均质材料形成。保护层62由无氧材料形成,前体也没有氧。例如,可以使用与形成下部子层62A(图6)基本相同的方法来形成保护层62。由于保护层62的形成没有氧,在保护层62的形成中,不会有含氧工艺气体穿透并劣化器件晶圆30。
图13示出了保护层62的水平部分的去除,这可以通过平坦化工艺、各向异性蚀刻工艺或两者进行。图14示出位于器件晶圆30的背侧上的背侧互连结构的形成。对应的工艺与参考图9讨论的基本相同。后续工艺与参考图10和图11所讨论的基本相同,并且在此不再重复。
本发明的实施例具有一些有利特征。通过形成包括两个或多个子层的双层保护层或多层保护层,保护层的下部层没有氧,并且它的形成不会劣化器件晶圆中的低k介电层和金属部件。上部层具有良好的氧和湿气隔离能力,并且在后续工艺中可以阻止氧和湿气穿透至器件晶圆中。因此,改善了保护层的氧和湿气隔离能力。
根据本发明的一些实施例,一种方法包括将第一晶圆接合至第二晶圆;对第一晶圆执行修整工艺,其中,去除第一晶圆的边缘部分,并且在修整工艺之后,第一晶圆具有从第二晶圆的第二侧壁横向凹进的第一侧壁;沉积与第一晶圆的侧壁接触的保护层,其中,沉积保护层包括沉积与第一侧壁接触的不含氧材料;去除与第一晶圆重叠的保护层的水平部分;以及在第一晶圆上方形成互连结构,其中,将互连结构电连接至第一晶圆中的集成电路器件。
在实施例中,沉积保护层包括沉积由不含氧材料形成的第一子层;以及在第一子层上沉积第二子层,其中,第二子层由与不含氧材料不同的材料形成。在实施例中,沉积第二子层包括沉积含氧材料。在实施例中,沉积第一子层包括沉积氮化硅,以及沉积第二子层包括沉积氧化硅。在实施例中,该方法还包括在沉积第一子层和沉积第二子层之间,沉积第三子层,其中,在沉积第三子层期间,工艺气体从用于沉积第一子层的第一工艺气体逐渐过渡至用于沉积第二子层的第二工艺气体。
在实施例中,整个保护层包括不含氧材料。在实施例中,该方法还包括在形成互连结构之后,从第一晶圆去除第二晶圆。在实施例中,该方法还包括对第一晶圆执行切割工艺(singulation process)以将第一晶圆分隔成多个器件管芯。在实施例中,多个器件管芯没有保护层的剩余部分。在实施例中,保护层形成为共形层。在实施例中,去除保护层的水平部分包括执行各向异性蚀刻工艺。在实施例中,去除保护层的水平部分包括执行抛光工艺。
根据本发明的一些实施例,一种方法包括在载体晶圆上方接合器件晶圆;减薄器件晶圆的半导体衬底;修整器件晶圆,其中,修整器件晶圆的边缘部分;在器件晶圆和载体晶圆上沉积保护层,其中,沉积保护层包括沉积包含第一材料的第一子层;以及沉积包含与第一材料不同的第二材料的第二子层;露出器件晶圆的顶表面;以及在器件晶圆上方形成互连结构,其中,将互连结构电连接至器件晶圆中的集成电路器件。
在实施例中,第一子层具有比第二子层低的氧原子百分比。在实施例中,第二子层具有比第一子层更好的阻氧能力。在实施例中,该方法还包括,在沉积保护层之后,形成穿透半导体衬底以电连至半导体衬底下面的导电部件的的贯通孔。在实施例中,形成互连结构包括在器件晶圆上沉积介电层,其中,介电层在保护层的侧壁上延伸。
根据本发明的一些实施例,一种方法包括在载体晶圆上方接合器件晶圆,其中,器件晶圆中的第一介电层接合至载体晶圆中的第二介电层;修整器件晶圆,其中,修整器件晶圆中的第一半导体衬底的部分,并且暴露载体晶圆中的第二衬底的顶表面;在器件晶圆和载体晶圆上沉积保护层,其中,使用其中没有氧的工艺气体执行沉积保护层;从器件晶圆和载体晶圆去除保护层的水平部分;以及去除第二衬底。在实施例中,沉积保护层包括沉积氮化硅层。在实施例中,沉积保护层还包括在氮化硅层上方沉积氧化硅层。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成半导体结构的方法,包括:
将第一晶圆接合至第二晶圆;
对所述第一晶圆执行修整工艺,其中,去除所述第一晶圆的边缘部分,并且在所述修整工艺之后,所述第一晶圆具有从所述第二晶圆的第二侧壁横向凹进的第一侧壁;
沉积与所述第一晶圆的侧壁接触的保护层,其中,所述沉积所述保护层包括沉积与所述第一侧壁接触的不含氧材料;
去除与所述第一晶圆重叠的所述保护层的水平部分;以及
在所述第一晶圆上方形成互连结构,其中,所述互连结构电连接至所述第一晶圆中的集成电路器件。
2.根据权利要求1所述的方法,其中,所述沉积所述保护层包括:
沉积由所述不含氧材料形成的第一子层;以及
在所述第一子层上沉积第二子层,其中,所述第二子层由与所述不含氧材料不同的材料形成。
3.根据权利要求2所述的方法,其中,所述沉积所述第二子层包括沉积含氧材料。
4.根据权利要求3所述的方法,其中,所述沉积所述第一子层包括沉积氮化硅,并且所述沉积所述第二子层包括沉积氧化硅。
5.根据权利要求2所述的方法,还包括在所述沉积所述第一子层和所述沉积所述第二子层之间,沉积第三子层,其中,在所述沉积所述第三子层期间,工艺气体从用于沉积所述第一子层的第一工艺气体逐渐过渡至用于沉积所述第二子层的第二工艺气体。
6.根据权利要求1所述的方法,其中,整个所述保护层包括所述不含氧材料。
7.根据权利要求1所述的方法,还包括在形成所述互连结构之后,从所述第一晶圆去除所述第二晶圆。
8.根据权利要求1所述的方法,还包括对所述第一晶圆执行切割工艺以将所述第一晶圆分隔成多个器件管芯。
9.一种形成半导体结构的方法,包括:
在载体晶圆上方接合器件晶圆;
减薄所述器件晶圆的半导体衬底;
修整所述器件晶圆,其中,修整所述器件晶圆的边缘部分;
在所述器件晶圆和所述载体晶圆上沉积保护层,其中,所述沉积所述保护层包括:
沉积包括第一材料的第一子层;以及
沉积包括与所述第一材料不同的第二材料的第二子层;
露出所述器件晶圆的顶表面;以及
在所述器件晶圆上方形成互连结构,其中,所述互连结构电连接至所述器件晶圆中的集成电路器件。
10.一种形成半导体结构的方法,包括:
在载体晶圆上方接合器件晶圆,其中,所述器件晶圆中的第一介电层接合至所述载体晶圆中的第二介电层;
修整所述器件晶圆,其中,修整所述器件晶圆中的第一半导体衬底的部分,并且暴露所述载体晶圆中的第二衬底的顶表面;
在所述器件晶圆和所述载体晶圆上沉积保护层,其中,使用其中没有氧的工艺气体执行所述沉积所述保护层;
从所述器件晶圆和所述载体晶圆去除所述保护层的水平部分;以及
去除所述第二衬底。
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