TWI653691B - 接合結構及其形成方法 - Google Patents

接合結構及其形成方法 Download PDF

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Publication number
TWI653691B
TWI653691B TW105121359A TW105121359A TWI653691B TW I653691 B TWI653691 B TW I653691B TW 105121359 A TW105121359 A TW 105121359A TW 105121359 A TW105121359 A TW 105121359A TW I653691 B TWI653691 B TW I653691B
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Taiwan
Prior art keywords
dielectric layer
layer
opening
conductive
forming
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TW105121359A
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TW201730986A (zh
Inventor
李明機
劉重希
古進譽
郭宏瑞
艾力克斯安德 卡林斯基
劉國洲
何明哲
吳逸文
陳清暉
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括在一導電墊上方形成一第一介電層，在第一介電層上方形成一第二介電層，並且蝕刻第二介電層形成第一開口，第一介電層的一頂表面暴露至第一開口。形成一模板層填入第一開口。第二開口然後在模板層和第一介電層內形成，導電墊的一頂表面暴露至第二開口。一導電柱在第二開口裡形成。

Description

接合結構及其形成方法
本揭露是有關於一種半導體裝置，特別是有關於一種具有接合結構之半導體裝置。
金屬對金屬的接合(也有時稱為直接接合)以及焊接接合通常是在積體電路的封裝裡的被使用的接合方法。在直接的接合裡，兩晶圓或者晶片的接合墊被接合在一起且沒有焊料設置於兩者間。例如，直接的接合可能是銅對銅的接合或者金對金的接合。在典型地直接接合過程中，裝置晶粒的金屬凸塊被對準至，或被放置於一封裝基板的金屬凸塊。應用一壓力將裝置晶粒和封裝基板彼此互壓。在接合過程期間，裝置晶粒及封裝基板也被加熱。伴隨著壓力和高溫，裝置晶粒以及封裝基板的金屬凸塊的表面部分混合，以使封裝形成。
在本揭露的一些實施例中，一種方法包括在一導電墊上方形成一第一介電層；在該第一介電層上方形成一第二介電層；蝕刻第二介電層以形成一第一開口，該第一介電層的一頂表面暴露至該第一開口；形成一模板層填入該第一開口；在模板層和第一介電層內一形成第二開口，該導電墊的一頂部表面暴露至該第二開口；以及在該第二開口裡電鍍一 導電柱。
在本揭露的一些實施例中，一種方法包括在一導電墊上方形成一第一介電層，該第一介電層為一平坦層；在該第一介電層上方形成一第二介電層；蝕刻該第二介電層以形成一第一開口，其中當暴露出該第一介電層的一頂表面，停止該第二介電層的該蝕刻；形成一共形介電層延伸進該第一開口；形成一模板層填入該第一開口，並在該共形介電層上方；形成一圖案化光阻在模板層上；蝕刻該模板層、該共形介電層和該第一介電層以形成該第二開口；在該第二開口裡電鍍一導電柱，該導電柱連接該導電墊；以及移除模板層。
在本揭露的一些實施例中，一種結構包括一導電墊；在該導電墊上方的一第一介電層；在該第一介電層上方的一第二介電層；一第三介電層延伸至在該第二介電層裡的一開口，其中該第三介電層包括在該開口的側壁上的側壁部分，以及接觸該第一介電層的一頂表面的一底部部分；並且一導電柱穿過該第三介電層和該第一介電層的該底部部分，其中該導電柱和該導電墊接觸。
100‧‧‧封裝元件
20‧‧‧半導體基板
22‧‧‧積體電路裝置
24‧‧‧層間介電層
27‧‧‧蝕刻停止層
28‧‧‧接觸拴塞
30‧‧‧介電層
32‧‧‧導電線
34‧‧‧擴散阻絕層
36‧‧‧含銅材料
40‧‧‧IMD層
42‧‧‧溝槽
44‧‧‧通孔開口
50‧‧‧導電通孔
52‧‧‧導電線
53‧‧‧IMD層
54‧‧‧蝕刻停止層
56‧‧‧介電層
58‧‧‧溝槽
60‧‧‧通孔開口
62‧‧‧導電襯墊
64‧‧‧導電材料
66‧‧‧通孔
68‧‧‧導電部件
68A‧‧‧導電襯墊
68B‧‧‧導電線
70‧‧‧介電層
72‧‧‧介電層
74‧‧‧介電層
76‧‧‧介電層
78‧‧‧介電層
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
T4‧‧‧厚度
80‧‧‧光阻
α‧‧‧標號角
82‧‧‧開口
82A‧‧‧側壁
84‧‧‧介電層
T5‧‧‧厚度
T6‧‧‧厚度
86‧‧‧模板層
88‧‧‧光阻
90‧‧‧開口
L1‧‧‧橫向尺寸
92A‧‧‧鎳層
92B‧‧‧金層
93‧‧‧頂表面
84A‧‧‧頂表面
92‧‧‧導電柱
△H‧‧‧高度差
102‧‧‧晶粒
200‧‧‧封裝元件
204‧‧‧金屬部件
206‧‧‧介電層
300‧‧‧封裝元件
304‧‧‧導電部件
306‧‧‧介電層
308‧‧‧焊接區
402-416‧‧‧步驟
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。強調根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1至圖16A圖式說明根據一些實施例之在一封裝結構的形成的中間階段的剖視圖。
圖16B圖式說明根據一些實施例之一導電柱和環繞的開口的俯 視圖。
圖17圖式說明根據一些實施例之與另一個封裝結構的一導電部件接觸的導電柱。
圖18圖式說明根據一些實施例之透過焊料接合接合至另一封裝結構的一導電部件的導電柱。
圖19圖式說明根據一些實施例之形成一封裝結構的處理流程。
以下揭示內容提供許多不同的實施例或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例，亦可包含在該第一與第二特徵之間形成其他特徵的實施例，因而該第一與第二特徵並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施例與/或所討論架構之間的關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。可理解當一特徵係形成於另一特徵或基板上方時，可有其他特徵存在於其間。
封裝結構及其之形成方法係按照各種示範性的實施例來提供。圖式說明根據一些實施例之形成封裝結構的中間階 段。一些實施例的一些變化被討論。在整個各種觀點和圖式說明的實施例中，相同的參考號用於指定相同的元件。
圖1至圖16A圖式說明根據一些實施例之在一封裝結構的形成的中間階段的剖視圖。如圖1至圖16A顯示的步驟也在如圖19中所示之處理流程400裡圖式說明。在隨後討論中，將參照圖19中的製程討論圖1至圖16A的製程步驟。
圖1圖式說明一封裝元件100的剖面圖。根據本揭露的一些實施例，封裝元件100是一裝置晶圓，包括主動裝置，例如電晶體和/或二極體，以及可能的被動裝置(例如電容器、電感器、電阻器，或諸如此類)。根據本揭露的其他的實施例，封裝元件100是一矽中介層晶圓，這可或可不包括主動裝置和/或被動裝置。根據本揭露的又其他實施例，封裝元件100為一封裝基板片，其可能於其中具有核心或沒有核心之封裝基板。在隨後的討論過程中，一裝置晶圓被用作一示範性的封裝元件100。本揭露的教導可能也被應用於矽中介層晶圓、封裝基板，等等。
根據本揭露的一些實施例，示範性的晶圓100包括半導體基板20，以及形成在半導體基板20的頂表面的部件。半導體基板20可以包括多晶矽、結晶鍺(crystalline germanium)、矽化鍺和/或一III-V化合物半導體(例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP)，等等。半導體基板20也可能是一個大塊矽基板或者絕緣體上矽基板。淺凹槽隔離(Shallow Trench Isolation，STI)區域(未示出)可能形成於半導體基板20內以絕緣在半導體基板20裡的主動區。雖然不顯示，貫穿通路可能形成延伸至半導體基板20，其中貫穿通路用於相互電性耦合在晶圓100相對側上的部件。
根據本揭露的一些實施例，晶圓100包括積體電路裝 置22，其在半導體基板20的頂表面上形成。示例性的積體電路裝置22包括互補性金屬氧化半導體(complementary metal-oxide semiconductor，CMOS)電晶體、電阻器、電容器、二極體，等等。積體電路裝置22的細節在此沒被說明。根據其他的實施例，晶圓100用於形成矽中介層，其中基板20可能是一個半導體基板或者一個介電基板。
層間介電層(inter-layer dielectric，ILD)24形成在半導體基板20上並且填入在積體電路裝置22中之電晶體之閘極堆疊間的空間。根據一些示範性實施例，ILD 24包括磷矽酸鹽玻璃(phosphosilicate glass，PSG)、矽硼玻璃(borosilicate glass，BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、摻雜氟的矽玻璃(phosphosilicate glass，FSG)、二氧化矽(tetraethyl orthosilicate，TEOS)，或諸如此類。可能使用旋塗法、可流動式化學氣相沉積(flowable chemical vapor deposition，FCVD)及諸如此類的方法形成ILD 24。根據本揭露的其他的實施例，使用電漿化學氣相沈積(plasma enhanced chemical vapor deposition，PECVD)、低壓化學氣相沈積(low pressure chemical vapor deposition，LPCVD)及諸如此類的方法形成ILD 24。
接觸拴塞28在ILD 24內形成，並且用來電性連接積體電路裝置22至上覆的金屬線、通孔和導電柱92(圖16A)。根據本揭露的一些實施例，因此，接觸拴塞28由從鎢、鋁、銅、鈦、鉭、鈦氮化物、鉭氮化物、及其合金和/或其之多層中選出來的一種導電的材料形成。接觸拴塞28的形成可以包括在ILD 24中形成開口，填入一導電物質至該接觸開口，並且進行平面化(例如化學機械研磨(chemical mechanical polish，CMP))以使接觸拴塞28的頂表面與ILD 24的頂表面對準成一水平面。
如圖1所示，蝕刻停止層27形成在ILD 24和積體電路裝置22上，如果有的話。蝕刻停止層27可包括碳化矽、氮化矽、氮氧化矽、碳氮化矽(silicon carbo-nitride)，或諸如此類。蝕刻停止層27由相對於上覆的介電層30具有高蝕刻選擇性的材料形成，因此蝕刻停止27層可用來停止介電層30的蝕刻。
進一步圖式說明圖1之介電層30，其或者在下文中稱為金屬間介電(inter-metal dielectric，IMD)層30。根據本揭露的一些實施例，IMD層30由具有介電常數(k值)低於大約3.0、大約2.5或甚至更低的一種低k介電材料形成。IMD層30可以包括黑金剛石(Black Diamond)(廠商(Applied Materials)的註冊商標)、一含碳的低k介電材料、氫矽鹽酸類(hydrogen silsesquioxane，HSQ)、甲基倍半矽氧烷(methylsilsesquioxane，MSQ)，諸如此類。IMD層30可能也有低k值，其可能小於約3.0、2.5、或者2.0。根據本揭露的一些實施例，IMD層30的形成包括沉積一種包含成孔劑(porogen)的介電材料，然後進行一硬化製程以驅逐成孔劑，並且因此剩下的IMD層30是多孔的。
根據其他的實施例，IMD層30由一種非低k的介電材料(例如矽氧化物、矽氮化物、碳化矽、氮氧化矽，諸如此類)形成。
導電線32在IMD層30裡形成。根據一些實施例，金屬線32包括擴散阻絕層34以及在擴散阻絕層34上的含銅材料36。擴散阻絕層34可以包括鈦、鈦氮化物、鉭、鉭氮化物，諸如此類，並且有防止在含銅材料36內的銅擴散進IMD層30的功能。導電線32在下文也被稱為金屬線32。導電線32的形成可以包括一個單個的鑲嵌製程(damascene process)。
參照圖2，蝕刻停止層38和IMD層40形成在IMD 30 和導電線32上。根據目前應用的一些實施例，蝕刻停止層38係由從碳化矽、矽氮化物及碳氮化矽(silicon carbo-nitride)，諸如此類中選出的介電材料所形成。IMD層40可能由一種低k材料或者一種非低k材料形成，並且IMD層40的材料可能係從形成IMD 30之候選材料的相同的組中選出。
參照圖3，溝槽42和通孔開口44在IMD層40裡形成。根據本揭露的一些實施例，為了形成一初始通孔開口，形成的製程包括使用光學微影製程蝕刻IMD層40，其中初始通孔開口從IMD層40的頂表面延伸到在IMD層40的頂表面和底部表面之間的中間水平位置。下一步，一種金屬硬遮罩(未示出)形成並且被圖案化以界定溝槽42的圖案。為了形成溝槽42，接著執行非等向性蝕刻以蝕刻IMD層40。在溝槽42形成的同時，初始通孔開口延伸向下至蝕刻停止層38，因此形成通孔開口44。用於形成溝槽42的這種蝕刻法可能被使用一種時間模式執行。根據其他的實施例，通孔開口44和溝槽42在分別的光學微影製程內形成。例如，在第一光學微影製程中，通孔開口44形成並往下至蝕刻停止層38。在第二光學微影製程中，溝槽42形成。蝕刻停止層38然後暴露出這下伏導電線32。
IMD層40的蝕刻可能使用包括氟和碳的一種製程氣體執行，其中氟用於蝕刻，碳具有保護結果通孔開口44和溝槽42的側壁的效應。例如，用於蝕刻的製程氣體包括含氟和碳的氣體，例如C4F8，CH2F2和/或CF4和一種例如N2那樣的載運氣體。由於有合適的氟與碳之比，通孔開口44和溝槽42可能有合乎需要的輪廓。
圖4和圖5圖式說明形在通孔開口44(圖3)中之導電通孔50，以及在溝槽42中的導電線52的形成。圖4圖式說明在導電通孔50和導電線52的形成過程中的一個中間階段。根據本揭露的 一些實施例，導電通孔50和導電線52的形成包括進行覆蓋式沉積(blanket deposition)以形成導電襯墊46、沉積一個銅或者銅合金的薄種晶層(未示出)、並且藉由，例如，電鍍、無店電鍍、少電電鍍、沉積或諸如此類之方法將導電材料48填入其餘的通孔開口44及溝槽42。導電襯墊46可能是一個擴散阻障層、一個黏附層，或諸如此類。導電襯墊46可以包括鈦、鈦氮化物、鉭、鉭氮化物或者其他的選擇。導電材料48可以包括銅、銅合金、銀、黃金、鎢、鋁，或諸如此類。下一步，如圖5中所示，執行像是CMP那樣的平坦化製程，使襯墊46和導電材料48的表面對準成一水平面，並從IMD層40的頂表面移除超出的材料。
圖6結構性地圖式說明更多介電(IMD)層以及在介電層53中的各自的導電線和通孔(未示出)的形成。IMD層53的數量之決定係基於封裝元件100的繞線需求，並且根據一些示範性實施例範圍可從從0到7，或更多。IMD層53的數量等於0表示後來形成的蝕刻停止層54和介電層56係直接形成在IMD層40上而於兩者間沒有另外的介電層和導電線。在IMD層53中的導電線和通孔(未示出)電性耦合至積體電路裝置22。
如圖6所示，蝕刻停止層54和IMD層56形成在介電層53上。根據目前的應用的一些實施例，且蝕刻停止層54的材料可能係從形成蝕刻停止層27之候選材料的相同的組中選出，其中候選材料可以包括碳化矽、矽氮化物、氮氧化矽、碳氮化矽，或諸如此類。IMD層56也可能由一種低k材料或者一種非低k材料形成，並且IMD層56的材料可能係從形成IMD 30和40之候選材料的相同的組中選出。
圖7至圖9圖式說明導電墊和連結通孔的形成。個別步驟顯示為在圖19顯示之處理流程之步驟402。參照圖7，溝槽58 和通孔開口60在IMD層56裡形成。形成過程可能與圖3所示之溝槽42及通孔開口44的形成相同。在隨後過程中，如圖8中所示，導電襯墊62形成，隨後以導電材料64填入溝槽58及通孔開口60。襯墊62和導電材料64的材料可分別選自下伏襯墊46以及導電材料48(圖4)的候選材料。下一步，一個平坦化製程被進行以移除比IMD層56的頂表面高的導電襯墊62和導電的材料64的部分，導致如圖9中所示之通孔66和導電部件68。通孔66和導電部件68可電性耦合至積體電路裝置22。
導電部件68包括導電襯墊68A，並且可能包括連接至導電墊68A的導電線68B。導電墊68A可能透過導電線68B連接至通孔66，如根據一些示範性實施例之圖9所示。根據一些實施例，導電墊68A可能也有接觸通孔66之頂表面之自己的底部表面。
參照圖10，介電層70和72形成。個別步驟顯示為在圖19顯示之處理流程之步驟404。根據一些示範性實施例，每個介電層70和72皆由一種非低k介電材料形成，包括矽氮化物、矽氧化物、碳化矽、氮氧化矽、碳氮化矽，其之結合，或者在其上之多層。根據一些示範性實施例，介電層70由氮矽化物形成。介電層70的厚度T1可能在大約1,000埃和大約3,000埃之間的範圍內。能夠理解的是在敘述中引述之數值僅是一種例子，其他數值可被被使用。
介電層72可能是單層，或者可能是包括多個(次)介電層之一個複合層。當介電層72是一個複合層時，在介電層72裡的相鄰的介電層由不同的介電材料形成。在介電層72裡的介電層的數量可能是1，2，3或更多。根據一些示範性實施例，如圖10之圖式說明，介電層72包括在介電層70上的介電層74，以及在介電層74上的介電層76，以及在介電層76上的介電層78。根據一些示範 性實施例，介電層74可能由氧化矽(SiO2)形成。根據一些示範性實施例，介電層76可能由氮化矽形成。根據一些示範性實施例，介電層78可能由氧化矽(SiO2)形成。介電層74的厚度T2之範圍可能在在大約1,000埃和大約3,000埃之間。介電層74的厚度T3之範圍可能在大約200埃和大約1,000埃之間。介電層78的厚度T4之範圍可能在大約2,000埃和大約4,000埃之間。介電層70、74、76及78可能形成為一平坦層，其平坦的遍布在整個封裝元件100。層70、74、76及78的形成方法可能係像是電漿化學氣相沈積法(PECVD)或低壓化學氣相沈積法(low pressure chemical vapor deposition，LPCVD)的化學氣相沉積法(CVD)。
參照圖11，光阻80在介電層72上形成，並且被圖案化形成開口82。下一步，光阻80被使用作為一個蝕刻罩蝕刻，以蝕刻下伏介電層72。個別步驟顯示為在圖19顯示之處理流程之步驟406。這種蝕刻法是非等向性蝕刻，並且可能使用乾式蝕刻來執行。用於蝕刻氧化矽層(例如層74和78)的製程氣體可包括阿摩尼亞(NH3)以及三氟化氮(NF3)的混合氣體、其為所知的SiCoNiTM。用於蝕刻氮化矽的製程氣體可能包括CF4和H2的混合物、CF4、O2和N2的混合物、SF6、O2和N2的混合物、SF6、CH4和N2的混合物，或是SF6，CH4，N2和O2的混合物。製程的組成可能也被調整，以至於有一種適當的蝕刻選擇性，例如，大於大約30，以便介電層70沒被蝕刻穿透過。由於這種蝕刻法，開口82穿透過介電層72，並且稍微地延伸至介電層70，如圖11中所示。開口82可能以一深度D1延伸至介電層70，在一些實施例，該深度D1大於大約50埃。
側壁82A的開口82基本上垂直，舉例來說，根據一些實施例，一側壁82A的一標號角α在大約85度和大約90度之間。在開口82的形成之後，光阻80被移除。
下一步，如圖12所示，介電層84形成。個別步驟顯示為在圖19顯示之處理流程之步驟408。介電層84具有在介電層72上的第一部份以及在延伸至開口82的第二部分。介電層84可能是具有相同厚度，或本質上具有相同厚度之水平部分和垂直部分之共形層。例如，水平部分的厚度T5和垂直部分的厚度T6可能有差(T5-T6)，以及，根據一些實施例，比率(T5-T6)/T5可能小於大約0.2，或者小於大約0.1。介電層84可能使用一種，例如原子層沈積(atomic layer deposition，ALD)的共形沉積法形成。介電層84的厚度T5和T6可能例如在，舉例來說，大約100埃和大約300埃之間的範圍內。根據一些示範性實施例，介電層84包括三氧化二鋁(Al2O3)。
參照圖13，形成模板層86以填入開口82(圖12)。個別步驟顯示為在圖19顯示之處理流程之步驟410。模板層86的頂表面比介電層84的頂表面高。模板層86可能由氧化矽形成，其可能使用像TEOS和臭氧那樣的先驅物形成。這種形成方法可以包括PECVD，次大氣壓化學氣相沈積法(sub-atmospheric chemical vapor deposition，SACVD)，或諸如此類。像是CMP的平坦化操作可能被執行以使模板層86的頂表面成水平面。
參照圖14，光阻88在模板層86上形成，並且被圖案化。下一步，光阻88被使用作為一個蝕刻罩以蝕刻下伏的模板層86、介電層84以及介電層70以形成開口90。個別步驟顯示為在圖19顯示之處理流程之步驟412。因此，導電墊68A被暴露。這種蝕刻法是非等向性蝕刻，並且可能使用乾式蝕刻來執行。根據一些實施例，用於蝕刻模板層86的製程氣體可能也包括SiCoNiTM。用於蝕刻氧化鋁的製程氣體(層84)可包括O2、BCl3和Ar的混合物。由於這種蝕刻法，開口90穿過層86、84和70，並且可能稍微地延 伸至導電墊68A。開口90的橫向尺寸L1是小的，例如，小於大約3μm。在在介電層70中有下切(係對應於相同蝕刻物之不同材料的不同蝕刻率所引起)的例子中，下切被控制以小於大約0.5μm。
光阻88然後被移除，並且最終的結構如圖15所示。下一步，使用模板層86作為一個模板，導電柱92係藉由，舉例來說，電化學電鍍或無電電鍍，形成在開口90中。個別步驟顯示為在圖19顯示之處理流程之步驟414。根據一些實施例，由於導電墊68A作為電鍍的一個種晶層，沒有覆蓋的種晶層形成。導電柱92可能是一個金屬柱，並且可能有單層結構或者多層結構。導電柱92的材料可能選自Cu、Ni、Pd、Au、Sn、SnAg、Co、其組合或其之多層。根據一些示範性實施例，導電柱92包括鎳層92A和在鎳層92A上的金層92B。
模板層86然後被移除，留下導電柱92，如圖16A中所示。個別步驟顯示為在圖19顯示之處理流程之步驟416。導電柱92有部分，這可能是多數，在開口82中，以及比介電層84的頂表面84A高的一部分。導電柱92的頂表面93和層84的頂表面84A有高度差△H，其可能小於大約5,000埃。高度差△H也可能在介於大約2,000埃和大約5,000埃之間的範圍內。
圖16B圖式說明在圖16A中的一封裝結構的俯視圖。圖16B顯示導電柱92被開口82環繞。而且，導電柱92落在導電墊68A上，導電墊68A擴張超過導電柱92的邊緣。在隨後製程中，如圖16A中所示之晶圓100可切斷為晶粒102，或在後續的步驟中仍保留為未切斷之晶圓。
圖17圖式說明晶粒102或者晶圓100(在下文稱為晶粒/晶圓102/100)放入與封裝元件200接觸。封裝元件200可能是一個裝置晶粒或者晶圓、矽中介層或者晶圓、封裝基板，或者一個 封裝。導電柱92可能在封裝元件200的表面實體接觸金屬部件204。因為導電柱突出得比介電層84的表面84A高，介電層84在封裝元件200中與介電層206分開。
根據一示範性實施例，晶粒102或者晶圓100與封裝元件200的接觸可被執行來共同地測試在晶粒/晶圓102/100及封裝元件200中的電路。在後續步驟內，晶粒/晶圓102/100與封裝元件200分離。因為介電層84沒和介電層206實體接觸，沒有黏著力來避免晶粒/晶圓102/100與封裝元件200分離。
圖18圖式說明一步驟，其中晶粒/晶圓102/100被接合至封裝元件300，其可能是裝置晶粒/晶圓、矽中介層/晶圓、封裝基板或者封裝。根據一些實施例，焊接區308接合導電柱92至在封裝元件300中的導電部件304。根據一些實施例，介電層84可能也與在封裝元件300中的介電層306的表面分開。在晶粒/晶圓102/100和封裝元件300之間的空間或許填入底部封膠(underfill)(未示出)，或者保持為未填滿在最終產品(當其被使用)中。根據一些實施例，焊接區308可全部或部分填入開口82(圖16A和圖16B)。焊接區308可與導電柱92的側壁接觸。
本揭露的實施例有一些有利的特徵。透過使用一模板層作為一個電鍍的模板形成導電柱，不必使用光阻作為電鍍的模板抵抗。因此，導電柱的橫向尺寸可被顯著降低，例如，小於約3μm，其係無法被達成的，如果使用光阻做為電鍍模板來形成導電柱。此外，不需要種晶層來電鍍導電柱，並且因此不再需要移除種晶層之不想要的部分。另外，透過在一個開口裡形成導電柱，能防止導電柱被粒子污染，例如，在如圖17顯示之步驟中，防止可能地機械損害。
根據本揭露的一些實施例，一種方法包括在一導電 墊上方形成一第一介電層；在該第一介電層上方形成一第二介電層；蝕刻第二介電層以形成一第一開口，該第一介電層的一頂表面暴露至該第一開口；形成一模板層填入該第一開口；在模板層和第一介電層內一形成第二開口，該導電墊的一頂部表面暴露至該第二開口；以及在該第二開口裡電鍍一導電柱。
根據本揭露的一些實施例，一種方法包括在一導電墊上方形成一第一介電層，該第一介電層為一平坦層；在該第一介電層上方形成一第二介電層；蝕刻該第二介電層以形成一第一開口，其中當暴露出該第一介電層的一頂表面，停止該第二介電層的該蝕刻；形成一共形介電層延伸進該第一開口；形成一模板層填入該第一開口，並在該共形介電層上方；形成一圖案化光阻在模板層上；蝕刻該模板層、該共形介電層和該第一介電層以形成該第二開口；在該第二開口裡電鍍一導電柱，該導電柱連接該導電墊；以及移除模板層。
根據本揭露的一些實施例，一種結構包括一導電墊；在該導電墊上方的一第一介電層；在該第一介電層上方的一第二介電層；一第三介電層延伸至在該第二介電層裡的一開口，其中該第三介電層包括在該開口的側壁上的側壁部分，以及接觸該第一介電層的一頂表面的一底部部分；並且一導電柱穿過該第三介電層和該第一介電層的該底部部分，其中該導電柱和該導電墊接觸。
以上所述一些實施例的特徵，以使本領域內之技藝人士能更好的理解本揭露的各個概念。本領域內之技藝人士他們可以很容易的將本申請公開的內容作為基礎來設計或更改其他的工藝及結構，以實現與本申請介紹的實施例相同的目的和實現同 樣的優點。本領域內之技藝人士還應該注意意識到這種等效構造並不背離本揭露精神的範疇，以及不在背離本揭露精神和範疇的情況下，可作各種改變、替代或更改。

Claims (9)

  1. 一種方法，包括：在一導電墊上方形成一第一介電層；在該第一介電層上方形成一第二介電層；蝕刻該第二介電層以形成一第一開口，該第一介電層的一頂表面暴露至該第一開口；形成一模板層填入該第一開口；施加一圖案化光阻在該模板層上方；蝕刻該模板層和該第一介電層以形成一第二開口，其中係使用該圖案化光阻為蝕刻光罩來進行該蝕刻，該導電墊的一頂部表面暴露至該第二開口；以及在該第二開口裡電鍍一導電柱。
  2. 如申請專利範圍第1項所述之方法，還包括形成一共形介電層延伸至該第一開口，該共形介電層接觸該第一介電層的該頂表面，其中該第二開口貫穿該共形介電層。
  3. 如申請專利範圍第2項所述之方法，更包括：將該導電柱接觸一封裝元件，該共形介電層與該封裝元件分開；以及將該導電柱分開該封裝元件。
  4. 一種方法，包括：在一導電墊上方形成一第一介電層，該第一介電層為一平坦層；在該第一介電層上方形成一第二介電層；蝕刻該第二介電層以形成一第一開口，其中當暴露出該第一介電層的一頂表面時，停止該第二介電層的該蝕刻； 形成一共形介電層延伸至該第一開口；形成一模板層填入該第一開口，並在該共形介電層上方；形成一圖案化光阻在該模板層上；蝕刻該模板層、該共形介電層和該第一介電層以形成一第二開口；在該第二開口裡電鍍一導電柱，該導電柱連接該導電墊，其中該導電柱的邊緣接觸該模板層的邊緣；以及移除該模板層。
  5. 如申請專利範圍第4項所述之方法，更包括：以在一封裝元件裡的一導電部件的一表面接觸該導電柱的一頂表面，其中該共形介電層與該封裝元件分開；以及在該接觸後，把該導電柱與該封裝元件分開。
  6. 如申請專利範圍第4項所述之方法，其中在該模板層被移除之後，該第一開口的部分再次被顯露，並且該導電柱的側壁暴露至該第一開口。
  7. 一種結構包括：一導電墊；一第一介電層，在該導電墊上方；一第二介電層，在該第一介電層上方；一第三介電層延伸至在該第二介電層裡的一開口，其中該第三介電層包括在該開口的側壁上的側壁部分，以及接觸該第一介電層的一頂表面的一底部部分；一導電柱穿過該第三介電層和該第一介電層的該底部部分，其中該導電柱和該導電墊接觸；以及 一焊料區在該開口中並且接觸該導電柱的一側壁和該第三介電層的該等側壁部分。
  8. 如申請專利範圍第7項所述之結構，其中該導電柱的一底部表面和該導電墊的一頂表面實體接觸。
  9. 如申請專利範圍第7項所述之結構，更包括一低k介電層，該導電墊位於該低k介電層內，其中該第一介電層具有一底部表面接觸該低k介電層的一頂表面。
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US20200328153A1 (en) 2020-10-15
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CN106601622A (zh) 2017-04-26
US20170110401A1 (en) 2017-04-20
KR20170045087A (ko) 2017-04-26
TW201730986A (zh) 2017-09-01
CN106601622B (zh) 2020-06-19
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