TWI567925B - 3d堆疊的晶片封裝 - Google Patents

3d堆疊的晶片封裝 Download PDF

Info

Publication number
TWI567925B
TWI567925B TW103138145A TW103138145A TWI567925B TW I567925 B TWI567925 B TW I567925B TW 103138145 A TW103138145 A TW 103138145A TW 103138145 A TW103138145 A TW 103138145A TW I567925 B TWI567925 B TW I567925B
Authority
TW
Taiwan
Prior art keywords
die
rdl
substrate
molding compound
vias
Prior art date
Application number
TW103138145A
Other languages
English (en)
Other versions
TW201541606A (zh
Inventor
余振華
陳明發
呂文森
邱文智
蔡文景
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201541606A publication Critical patent/TW201541606A/zh
Application granted granted Critical
Publication of TWI567925B publication Critical patent/TWI567925B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02372Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0239Material of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091Disposition
    • H01L2224/0918Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73217Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82031Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821Forming a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544Design considerations for via connections, e.g. geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053Oxides composed of metals from groups of the periodic table
    • H01L2924/054414th Group
    • H01L2924/05442SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/37Effects of the manufacturing process

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

3D堆疊的晶片封裝
本發明係關於半導體封裝結構,特別係關於3D堆疊的晶片封裝。
由於各種電子元件(例如,電晶體、二極體、電阻器、電容器等)之整合密度持續改良,半導體產業已經快速成長。整體而言,此整合密度改良係來自於重複縮小最小特徵尺寸(例如,將半導體製程節點縮小至次20奈米節點),其使得在給定面積上整合更多元件。為因應最近微小化、更高速度、更大頻寬、以及較低功率消耗與遲延的需求增加,因此需要用於半導體晶粒之較小且更具創造力的封裝技術。
由於半導體技術日益進步,堆疊半導體裝置,例如3D積體電路(3DIC),已經成為有效益的選擇,用以進一步縮小半導體裝置之實體尺寸。在堆疊半導體裝置中,例如邏輯、記憶體、處理器電路以及類似物之主動電路係製造於不同的半導體晶圓上。可設置二或多個半導體晶圓於彼此頂部上,用以進一步縮小該半導體裝置的尺寸架構(form factor)。
可經由合適的接合技術,將兩個半導體晶圓接合在一起。可在堆疊半導體晶圓之間提供電連接。該堆疊半導體裝置可提供較高密度與較小的尺寸架構(form factor),達到增加效能與降低功率消耗。 一般使用的接合技術包含直接接合、化學活化接合、電漿活化接合、陽極接合、共晶接合(eutectic bonding)、玻璃介質接合(glass frit bonding)、黏著接合、熱壓縮接合、反應性接合與/或類似者。可在該堆疊的半導體晶圓之間,提供電連接。該堆疊半導體裝置可提供較高密度與較小的尺寸架構(form factor),達到增加效能與降低功率消耗。
本揭露某些實施例提供一種封裝,其包括:第一晶粒,其具有位於第一基板的第一側上之第一重佈層(RDL);第二晶粒,其具有位於第二基板的第一側上之第二RDL,該第一RDL接合至該第二RDL;第三晶粒,其具有位於第三基板的第一側上之第三RDL,該第三晶粒係安置於該第二晶粒上方,該第二晶粒係位於該第一晶粒與該第三晶粒之間;第一通路,其延伸穿過該第二基板並且與該第二基板電隔離,該第一通路各自接觸該第一RDL或該第二RDL中的傳導元件;以及第二通路,其延伸穿過該第三基板並且與該第三基板電隔離,該第二通路各自接觸該第三RDL中的傳導元件或是該第一通路其中之一。
本揭露某些實施例提供一種封裝,其包括:第一晶粒,其具有位於第一基板上的第一重佈層(RDL);第二晶粒,其具有位於第二基板上的第二RDL,該第二晶粒係位於該第一晶粒上方,該第二RDL係接合至該第一RDL;第一模塑料,其係位於該第一晶粒上方並且位於該第二晶粒附近;第三晶粒,其具有位於第三基板上的第三RDL,該第三晶粒係位於該第一模塑料上方;第二模塑料,其係位於該第一模塑料上方並且位於該第三晶粒附近;第一通路,其延伸穿透該第二基板,並且各自接觸該第一RDL或該第二RDL中的至少一傳導元件,其中第一間隔物係將該第一通路與該第二基板電絕緣;以及第二通物, 其延伸穿過該第三基板,並且各自接觸該第三RDL中的傳導元件或是該第一通路其中之一,其中第二間隔物係將第二通路與該第三基板電絕緣。
本揭露某些實施例提供一種方法,其包括:提供第一晶粒,其具有位於第一基板上的第一重佈層(RDL),該第一RDL包括第一氧化物層;提供第二晶粒,其具有位於第二基板上的第二RDL,該第二RDL包括第二氧化物層;用氧化物對氧化物接合,藉由接合該第一氧化物層至該第二氧化物層,將該第一晶粒接合至該第二晶粒;將該第一晶粒接合至該第二晶粒之後,在第二晶粒中,形成第一開口,該第一開口延伸穿過該第二基板,並且暴露該第一RDL或該第二RDL中的第一傳導元件;在第一開口中,形成第一通路,該第一通路延伸穿過該第二基板,並且各自接觸個別的該第一傳導元件,其中該第一通路係與該第二基板電絕緣;將第三晶粒安置於該第二晶粒上方,該第三晶粒具有位於第三基板上的第三RDL;將該第三晶粒安置於該第二晶粒上方之後,在第三晶粒中,形成第二開口,該第二開口各自延伸穿過該第三基板,並且暴露該第一通路之一或是該第三RDL中的第二傳導元件;以及在該第二開口中,形成第二通路,該第二通路延伸穿過該第三基板,並且各自接觸個別的該第二傳導元件或是個別的該第一通路,其中該第二通路係與該第三基板電絕緣。
102‧‧‧晶粒
104‧‧‧晶圓
106‧‧‧晶粒基板
108‧‧‧重佈層(RDL)
110‧‧‧傳導元件
112‧‧‧晶圓基板
108、114‧‧‧RDL
202‧‧‧接合界面
302‧‧‧模塑料
402‧‧‧載體
502‧‧‧蝕刻停止層
504‧‧‧遮罩
506‧‧‧開口
702‧‧‧通路開口
902‧‧‧隔離層
1002‧‧‧自對準間隔物
1102‧‧‧通路
1202‧‧‧絕緣層
1204‧‧‧RDL開口
1302‧‧‧頂部RDL傳導元件
1402‧‧‧保護層
1406‧‧‧頂部RDL
1502‧‧‧連接裝置
1602‧‧‧晶粒
1604‧‧‧晶圓
1606‧‧‧蝕刻停止層
1608‧‧‧遮罩
1610‧‧‧傳導元件
1612‧‧‧晶粒基板
1614‧‧‧晶粒RDL
1616‧‧‧晶圓RDL
1618‧‧‧通路開口
1620‧‧‧晶圓基板
1622‧‧‧模塑料
1628‧‧‧接合界面
1702‧‧‧隔離層
1802‧‧‧間隔物
2002‧‧‧通路
2102‧‧‧晶粒
2104‧‧‧晶圓
2106‧‧‧晶粒基板
2108‧‧‧晶粒RDL
2110‧‧‧傳導元件
2112‧‧‧晶圓基板
2114‧‧‧晶圓RDL
2116‧‧‧模塑料
2118‧‧‧接合界面
2202‧‧‧第一遮罩
2204‧‧‧開口
2302‧‧‧通路開口
2402‧‧‧第二遮罩
2502‧‧‧第二遮罩開口
2702‧‧‧隔離層
2802‧‧‧間隔物
2902‧‧‧通路
3000‧‧‧封裝
3002‧‧‧第一晶粒
3004‧‧‧第一基板
3006‧‧‧第一RDL
3008‧‧‧第二晶粒
3010‧‧‧第二基板
3012‧‧‧第二RDL
3014‧‧‧傳導元件
3016‧‧‧第一模塑料
3102‧‧‧第一通路
3104‧‧‧傳導元件
3202‧‧‧第三晶粒
3204‧‧‧第三基板
3206‧‧‧第三RDL
3208‧‧‧第二模塑料
3302‧‧‧第二通路
3402‧‧‧頂部RDL
3404‧‧‧頂部RDL介電層
3406‧‧‧保護層
3408‧‧‧連接裝置
3410‧‧‧頂部RDL傳導元件
3502‧‧‧第二封裝
3504‧‧‧第二連接裝置
3506‧‧‧散熱片
3508‧‧‧黏著層
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之各方面。注意,根據產業之標準實施方式,各種特徵並非依比例繪示。實際上,為了清楚討論,可任意增大或縮小各種特徵的尺寸。
圖1至15係根據實施例說明使用後鑽孔製程(via last process)形成晶圓上晶片(chip-on-wafer)結構之中間製程步驟的橫切面圖式。
圖16至20係根據另一實施例說明使用後鑽孔製程(via last process)形成晶圓上晶片(chip-on-wafer)結構之中間製程步驟的橫切面圖式。
圖21至29係根據實施例說明使用雙鑲嵌後鑽孔製程(dual damascene via last process)形成晶片堆疊晶圓結構之中間製程步驟的橫切面圖式。
圖30至35係根據一些實施例說明形成3D晶圓上晶片且基板上晶圓(chip-on-wafer-on-substrate)結構之中間製程步驟的橫切面圖式。
以下揭示內容提供許多不同的實施例或範例,用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下,以簡化本申請案之揭示內容。當然,這些僅為範例,並非用於限制本申請案。例如,以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例,亦可包含在該第一與第二特徵之間形成其他特徵的實施例,因而該第一與第二特徵並非直接接觸。此外,本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的,而非支配不同實施例與/或所討論架構之間的關係。再者,本申請案所述之一些方法實施例係以特定順序進行;然而,其他方法實施例可考量以任何邏輯順序進行。
再者,本申請案可使用空間對應語詞,例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明,以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外,裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向),並且可相應解釋本申請案使用的空間對應描述。
半導體裝置接合在一起,形成具有各種性能的封裝。在一些製 程中,使用例如氧化物對氧化物接合、混合接合(through hybrid bonding)或類似方式之直接表面接合而將晶粒、晶圓或晶粒與晶圓的組合物接合在一起。已經發現可使用後鑽孔製程(via last process)而提供接合晶圓之間的互連。在後鑽孔製程中,接合晶粒之後,形成通路(via)穿過該晶粒其中之一,用以在該晶粒與外部連接裝置之間提供電連接,在通路開口的側壁上使用自對準(self-aligning)絕緣間隔物(spacer)。該側壁上的自對準間隔物容許較窄、較高的通路,並且將該通路的深寬比(aspect ratio)改良至約3至約10之間。改良的深寬比造成更緊密配置的通路陣列。
進一步發現由於本申請案揭示的後鑽孔製程實施例可提供封裝中晶粒之間或是晶粒與外部連接裝置之間的連接性,因此該後鑽孔製程容許堆疊許多晶粒。在接合每一個晶粒或晶粒層之後,形成通路。形成通路連接至先前接合的晶粒,或是連接至較低晶粒中之先前形成的通路。在頂部或是層晶粒上方,提供外部連接裝置,該外部連接裝置將通路連接至電源或是提供與另一晶粒、基板、封裝或類似物之通訊。
圖1係根據實施例說明在接合之前的晶圓104與晶粒102之橫切面圖式。晶粒102包括晶粒基板106,例如具有一或多個主動裝置(active device)形成於其中的半導體。晶粒重佈層(RDL)108係位於該晶粒基板106上。該晶粒RDL 108包括一或多個介電層,具有傳導元件110位於該介電層中。在具有主動裝置的該側基板上方,形成該晶粒RDL 108,該傳導元件110係連接至該晶粒基板106上的主動裝置。
該晶圓104具有位於晶圓基板112上方的晶圓RDL 114。在一些實施例中,該晶圓基板112係具有一或多個主動裝置形成於其中的半導體。該晶圓RDL 114係形成在該晶圓基板112中的主動裝置上方,並且具有位於介電層中的一或多個傳導元件110。
圖2係根據實施例說明接合晶圓的製程步驟之橫切面圖式。在該RDL 108的頂部表面上,接合晶粒102與晶圓104,形成接合界面202。該晶粒102與晶圓104係作為用於具有將封裝安置至外部裝置、基板或類似物之連接的封裝基礎。在一些實施例中,例如,藉由直接表面接合、金屬對金屬接合、混合接合或是其他接合製程,將晶粒102接合至晶圓104。直接表面接合製程透過清理與/或表面活化製程,而後施加壓力、熱與/或其他接合製程步驟至接合表面,而產生氧化物對氧化物接合或是基板對基板接合。在一些實施例中,藉由熔化暴露在RDL 108與114表面上的傳導元件110,例如金屬接合墊,達到金屬對金屬接合而接合晶粒102與晶圓104。在其他實施例中,藉由直接表面接合與金屬對金屬接合的組合,混合接合係用以接合晶粒102與晶圓104,其中RDL 108與114的表面與暴露在RDL 108與114表面的金屬接合墊之表面接合。在一些實施例中,接合的晶粒係烘乾的(baked)、退火的(annealed)、壓合的(pressed)或是被處理而強化或完成該接合。
圖3係根據實施例說明在封裝上方形成模塑料302的橫切面圖式。該模塑料302係形成於該晶粒102附近與該晶圓RDL 114上。例如,在一些實施例中,使用模型(未繪示)而將該模塑料302成形或塑形,該模型可具有邊界或是其他特徵用於保留所施加的模塑料302。此模型可用以加壓成形該晶粒102附近的模塑料302,以迫使該模塑料302進入開口與凹槽中,消除模塑料302中的氣泡(air pocket)或是類似物。在實施例中,該成形材料302係非傳導性或介電材料,例如環氧化合物、樹脂、例如PBO之可成形的聚合物,或是其他可成形材料。例如,模塑料302係可透過化學反應或乾燥而硬化的環氧化合物或樹脂。在另一實施例中,模塑料302係經紫外線(UV)硬化的聚合物。
在晶粒102與晶圓104上方形成模塑料302之後,例如藉由研磨、 化學機械拋光(CMP)、蝕刻或是其他製程,將成形材料302縮減或是平面化。在一些實施例中,在平面化作用之後,模塑料302延伸至晶粒102上方,以及在其他實施例中,縮減模塑料而暴露晶粒102。在一些實施例中,在與該模塑料相同的製程中,將晶粒基板106減薄或是縮減,造成晶粒102背側表面實質上與成形材料表面齊平。
圖4係根據實施例說明將封裝安置至載體402的橫切面圖式。將該封裝倒置,以容許於晶圓基板112上之處理。例如,晶粒102與模塑料302表面接合至玻璃載體或其他處理表面。使用晶粒附接膜(die attachment film,DAF)、黏著劑或是類似物,將封裝附接至載體402。在其他實施例中,該封裝係附接至載體402,該晶圓基板112係位於該載體402上,容許透過該封裝的晶粒側而處理該封裝。在一些實施例中,亦藉由研磨、CMP、蝕刻或其他製程而減薄化縮減該晶圓基板112。
圖5係根據實施例說明遮罩晶圓基板112的橫切面圖式。載該晶圓基板112上形成蝕刻停止層502,相較於晶圓基板112的材料,該蝕刻停止層502的材料具有高蝕刻選擇比。此外,相較於晶圓RDL 114與晶粒RDL 108,蝕刻停止層502具有高蝕刻選擇比。在一些實施例中,晶圓基板112係矽且RDL 114與108係氧化矽,蝕刻停止層502係例如氮化矽(SiN)之氮化物、例如碳化矽(SiC)之碳化物、或是例如氮氧化矽(SiON)之氮氧化物,或是其他蝕刻停止材料。在此實施例中,藉由使用化學氣相沉積(CVD)、電漿輔助化學氣相沉積(PECVD)、物理氣相沉積(PVD)、磊晶、旋塗製程或是其他沉積製程,而沉積該蝕刻停止層。
在該蝕刻停止層502上方,形成遮罩504,並且將該遮罩504圖案化以形成暴露部分蝕刻停止層502的開口506。在一些實施例中,遮罩504係沉積、曝光且顯影的光阻。該遮罩504中的開口506係對準於 RDL 108與114中的傳導元件110上方。
圖6係根據實施例說明蝕刻停止層502的蝕刻之橫切面圖式。將該蝕刻停止層502蝕刻,暴露該晶圓基板112。在一些實施例中,使用乾式電漿蝕刻而將蝕刻停止層502蝕刻,該乾式電漿蝕刻係例如使用以氟為基礎的蝕刻劑之氧氣或氮氣電漿,該蝕刻劑例如四氟化碳(CF4)或是六氟化硫(SF6)。在其他實施例中,藉由使用濕式蝕刻而將蝕刻停止層502蝕刻,該濕式蝕刻係使用例如硫酸(H2SO4)、加熱的磷酸(H3PO4)、或類似物。
圖7係根據實施例說明晶圓基板112的蝕刻之橫切面圖式。將晶圓基板112非等向性蝕刻,以形成具有實質垂直壁的通路開口702。在一些實施例中,在不同的製程步驟蝕刻晶圓基板112與蝕刻停止層502,使得蝕刻停止層502作為蝕刻晶圓基板112的硬遮罩。例如,當晶圓基板112為矽,用例如氯氣(Cl2)之氯基底蝕刻劑對於晶圓基板112進行乾式電漿蝕刻,或是用氫氧化鉀(KOH)或硝酸/氫氟酸(HNO3/HF)混合物對於晶圓基板112進行濕式蝕刻。此外,選擇性蝕刻晶圓基板112,蝕刻停止於晶圓RDL 114。
圖8係說明蝕刻RDL 108與114的氧化物層之橫切面圖式。在實施例中,使用包括氟化銨(NH4F)與氫氟酸的緩衝氧化物蝕刻液(BOE),蝕刻該氧化物層。RDL 108與114的氧化物層中的傳導元件110係作為蝕刻停止層,使得將RDL 108與114蝕刻至不同深度。蝕刻該氧化物層係從通路開口702延伸至RDL 108與114中的傳導元件110。在一些實施例中,通路開口702延伸穿過上傳導元件110中的開口,並且暴露下傳導元件110的表面。因而,單一通路開口702可暴露多個傳導元件110的表面。此外,在一些實施例中,該通路開口702暴露RDL 108與晶圓RDL 114中的傳導元件110。
圖9係根據實施例說明形成隔離層902的橫切面圖式。移除遮罩 504(參閱圖7),在蝕刻停止層502上方,形成保形介電隔離層(conformal dielectric isolation layer)902。該隔離層902延伸至每一個通路開口702中,並且覆蓋該通路開口702的側壁,包含暴露在該通路開口702中的部分晶圓基板112。
例如,在實施例中,使用CVD或PECVD製程,由氮化矽形成該隔離層902。在其他實施例中,由氧化物、其他氮化物、碳化物、氮氧化物、旋塗式玻璃(SOG)或是其他介電質或電絕緣材料而形成該隔離層902。隔離層902的厚度有一部分係藉由在將形成於通路開口702中的通路上所要施加的電壓而判定。已經判定在約500埃至約5000埃之間的厚度造成崩潰電壓大於約3.8伏特。
圖10係根據實施方式說明形成自對準間隔物1002的橫切面圖式。例如,使用氯氣、六氟化硫、四氟化碳、在氬氣(Ar)、氦氣(He)或其他蝕刻劑或其他環境,進行乾式電漿蝕刻,蝕刻隔離層902(參閱圖9)。例如,在一些實施例中,以氧氣(O2)、氮氣(N2)或其他製程氣體提供蝕刻劑,以增進蝕刻的選擇比。在此蝕刻中,將環境維持在約25℃至約150℃之間,且壓力在約10mtorr至約200mtorr之間。在一些實施例中,該蝕刻為非等向性,以垂直方向移除材料。因此,該蝕刻自封裝的水平表面移除隔離層902的材料,在封裝的側壁表面上留下間隔物1002。例如,移除位在蝕刻停止層502上的部分隔離層902,同時在通路開口702的側壁上保留部分該隔離層902。這是由於在側壁垂直方向之隔離層902的厚度係大於在水平表面的厚度。此外,在蝕刻過程中,暴露傳導元件110之部分頂部表面。這是由於實質上自頂部方向移除隔離材料,該隔離層902的方向性蝕刻縮減隔離層902的頂部表面,消除隔離層902的側向部分並且留下垂直部分。
已經發現可在通路開口702中形成自對準間隔物1002,以及該間隔物1002的自對準特徵造成該間隔物1002形成於通路開口702的側壁 上。該間隔物1002係將形成通路開口702側壁之材料與通路開口702中所形成的通路絕緣。特別地,間隔物1002形成在通路開口702的側壁上,該通路開口702穿過晶圓基板112,該間隔物1002的外表面係位於通路開口702的側壁上,該間隔物1002的內表面係面對通路開口702的內部。間隔物1002使得在通路開口702中形成傳導通路,同時防止與晶圓基板112以及RDL 108與114的垂直表面電接觸。在一些實施例中,間隔物1002延伸至下方傳導特徵110,屏蔽通路開口702,使其避開通路開口702的所有側壁。此外,間隔物1002留下傳導元件110的部分側表面暴露於通路開口702中,使得後續形成的通路可與傳導元件110電接觸。因此,一些間隔物係延伸於晶圓基板112的最底部表面下方至RDL 108與114中,間隔物1002的內表面係自傳導元件1002持續延伸至晶圓基板112的頂部表面或是於晶圓基板的頂部表面上方。
在一些實施例中,通路開口702係形成於上方傳導元件(upper conductive element)110上方或是穿過上方傳導元件110至下方傳導元件(lower conductive element)110,該通路開口702的上部之寬度係大於通路開口702的下部之寬度。在此實施例中,在通路開口702的上部與下部之側壁上,形成個別的間隔物1002,上方與下方間隔物1002側向間隔以暴露上方傳導元件110的側表面。
圖11係根據實施例說明在通路開口702中形成通路1102的橫切面圖式。在接合晶粒102至晶圓104之後,形成通路1102,因而此製程戲稱為後鑽孔(via last)製程。在一些實施例中,延伸穿過例如晶圓基板112之基板的通路1102係稱為貫穿基板之通路(through substrate via,TSV),或者稱為貫穿矽之通路,通路延伸穿過矽基板。延伸穿過模塑料302的通路1102係稱為貫穿介電質之通路(through dielectric via,TDV)。
在一些實施例中,阻障層(未繪示以求圖式清晰呈現)係形成於通 路開口702中,例如,使用CVD、PECVD或其他沉積製程,由鈷(Co)、鈦、鎢、氮化鉭(TaN)、氮化鈦(TiN)或類似物形成該阻障層。使用例如銅(Cu)、鋁(Al)、鋁銅合金(AlCu)、金、鈦、鈷、合金或其他傳導材料之傳導材料,填充通路開口702而產生通路1102。例如,在一些實施例中,透過電化學電鍍(electrochemical plating,ECP)、電鍍(electroplating)、無電式電鍍(electroless plating)或其他製程而形成通路。例如,在此實施例中,使用原子層沉積,在間隔物與傳導元件110上方或是在阻障層上方,形成晶種層(未繪示)。該晶種層提供電鍍製程的成核位置(nucleation site),並且增加形成通路1102之電鍍材料的均勻性。在一些實施例中,通路1102的傳導材料在通路開口702的上方延伸。例如,使用過量填充(overfilling),以確保完全填充開口702。使用研磨、CMP、拋光、蝕刻或其他減縮製程而移除過多的材料。在形成通路1102之後,通路1102的頂部表面實質上與蝕刻停止層502的頂部表面齊平。在一些實施例中,研磨製程移除蝕刻停止層502,或是減縮晶圓基板112的頂部表面。
通路1102延伸穿過晶圓基板112,以接觸一或多個傳導元件110。間隔物1102將通路1102與晶圓基板112電絕緣,使得通過通路1102所傳送的電子信號不會干擾晶圓基板112中的主動裝置。在一些實施例中,通路1102延伸穿過晶圓基板112、晶圓RDL 114與接合界面202,以接觸晶粒RDL 108中的傳導元件110。在此實施例中,晶粒RDL 108上的傳導元件110係透過晶粒RDL 108而電連接至晶粒基板106。因此,可自封裝的晶圓側,形成晶粒基板106與外部裝置或連接之間的連接。同樣地,在一些實施例中,通路1102延伸穿過晶圓基板112並且接觸晶圓RDL 114中的傳導元件110,其係電連接至晶圓基板112。因此,可自晶粒102或晶圓104,將電力或資料連接透過晶圓基板112而提供至外部裝置。
此外,在一些實施例中,使用後鑽孔製程,可將晶圓104電連接至晶粒102。例如,可藉由通路1102而連接晶圓RDL 114中的第一傳導元件110與晶粒RDL 108中的第二傳導元件110,該通路1102接觸第一與第二傳導元件110。因此,即使RDL 108與114係位於晶粒102與晶圓104之間,仍可提供外部電連接性以及晶粒至晶圓連接性而不需要個別的連接裝置,例如在接合晶粒102至晶圓104之前所形成的微凸塊或是錫球。此外,該後鑽孔製程使得在晶粒與晶圓接合製程中不需要將晶圓對準晶粒。
已經發現間隔物1002對於晶片堆疊晶圓結構提供較低成本與較簡單的結構。此外,間隔物1002使得通路的高度與寬度之深寬比在3與約10之間,增加晶片間連接的密度。進一步發現通路1102延伸穿過晶圓基板112,可更規則性地配置通路1102穿過封裝,並且提供更異質(heterogeneous)的晶片堆疊。在後續處理或封裝固定的過程中,通路1102的規則配置亦提供改良的翹曲(warpage)控制。
圖12係說明頂部RDL絕緣層1202的橫切面圖式。在一些實施例中,在蝕刻停止層502上方,形成絕緣材料,例如PBO、氧化矽、聚亞醯胺或是其他絕緣材料。在絕緣層1202中形成一或多個RDL開口1204,暴露通路1102。在一些實施例中,絕緣層1202係噴塗或旋塗的PBO,並且使用光微影蝕刻製程,曝光與顯影PBO而形成RDL開口1204。在其他實施例中,使用CVD或類似製程沉積絕緣層1202,並且將其蝕刻、雷射鑽孔、銑削(milled)或圖案化。
圖13係根據實施例說明在頂部RDL絕緣層1202中形成頂部RDL傳導元件1302的橫切面圖式。例如,使用濺鍍、PVD、CVD、電鍍或是其他沉積製程,在RDL開口1204中的絕緣層1202上方沉積例如銅之傳導材料。藉由遮罩與蝕刻或是在沉積之前的遮罩,將所沉積的傳導材料圖案化。雖然為求清楚而將所述的頂部RDL傳導元件1302繪示為實 質上垂直延伸,但應理解在一些實施例中,頂部RDL傳導元件1302具有側向延伸的部分,以提供所欲之後續形成層或連接裝置的佈局。
圖14係說明形成附加絕緣層與傳導元件以形成頂部RDL 1406的橫切面圖式。將一或多個頂部RDL絕緣層1202與傳導元件1302形成堆疊,以於外部裝置與通路1102之間提供電連接性。此外,保護層1402形成於最上頂部RDL絕緣層1202的上方,並且具有開口以暴露頂部RDL傳導元件1302。在一些實施例中,保護層1402係PBO、環氧化合物、氧化物、氮化物、碳化物、氮氧化物、聚亞醯胺或其他絕緣或保護材料,並且係如上所述被沉積與圖案化。
圖15係根據實施例說明形成連接裝置1502的橫切面圖式。在頂部RDL傳導元件1302的暴露部分上,安置一或多個連接裝置1502。在一些實施例中,連接裝置1502為錫球、錫柱、傳導凸塊或是其他傳導連接裝置。連接裝置1502使得將封裝安置於標的基板,例如晶粒、封裝、晶圓、PCB或類似物。因此,晶圓104與晶粒102透過連接裝置1502與通路1102而與標的基板具有信號連接性。而後,自封裝移除載體402。
雖然所示之晶片堆疊晶圓封裝係使用後鑽孔製程以形成通路1102,其係自封裝的晶圓側延伸通過晶圓基板112而至RDL 108與114,應理解所揭示的實施例並非受限於此配置。在其他實施例中,自封裝的晶粒側形成穿過晶粒基板106與模塑料302而至RDL 108及114的通路1102。此外,在一些實施例中,從封裝的晶圓側與晶粒側形成通路1102。
此外,以上揭示的實施例並不受限於所描述的步驟順序與結構。圖16至20係根據實施例說明形成具有部分高度自對準間隔物之晶片堆疊晶圓的中間製程步驟之橫切面圖式。
圖16係根據實施例說明將封裝的模塑料1622中的通路開口1618 遮罩與蝕刻之橫切面圖式。例如,如上所述,接合晶粒1602與晶圓1604。晶粒1602與晶圓1604分別具有晶粒基板1612與晶圓基板1620,並且該基板1612與1620具有一或多個主動裝置。晶粒RDL 1614與晶圓RDL 1616係位於個別的基板1612與1620上,並且包括具有傳導元件1610位於其中的介電層,該傳導元件1610中的一部分係與個別基板1612及1620中的主動裝置接觸。晶粒1602與晶圓1604接合在一起,使得晶粒RD 1614與晶圓RDL 1616接觸並且形成接合界面1628。在一些實施例中,晶粒1602與晶圓1604係以上述之直接表面、金屬對金屬、或是混合接合的方式接合。模塑料1622係形成於晶粒1602上方,並且在一些實施例中係於晶粒1602上方延伸。在模塑料1622的上方,形成蝕刻停止層1606。
在蝕刻停止層1606的上方,沉積遮罩1608,並且將其圖案化開口,使得該開口位在一或多個該傳導元件1610上方。使用遮罩1608蝕刻通路開口1618穿過模塑料1622,以控制通路開口1618的位置。在實施例中,通路開口1618延伸穿過模塑料1622,位於晶粒基板1612上方的通路開口1618延伸穿過晶粒基板1612至晶粒RDL 1614。與晶粒基板1612相鄰且非位於晶粒基板1612上方的通路開口1618係部分延伸穿過模塑料1622。
圖17係根據實施例說明形成隔離層1702的橫切面圖式。移除遮罩1608(參閱圖16),並且在蝕刻停止層1606上方,形成保形介電隔離層(conformal dielectric isolation layer)1702。在實施例中,隔離層1702的形成係如上所述。隔離層1702延伸至各個通路開口1618中,並且覆蓋通路開口1618的側壁,包含暴露在通路開口1618中的部分晶粒基板1612。此外,例如,隔離層1702係覆蓋暴露在開口1618之底部的晶粒RDL 1614與模塑料1622的側表面。
圖18係根據實施例說明形成部分高度自對準間隔物(partial height self-aligning spacers)1802的橫切面圖式。在一些實施例中,蝕刻隔離層(參閱圖17),如上所述。該蝕刻暴露間隔物1802之間的通路開口1618中的晶粒RDL 1614之部分側表面。此外,對於與晶粒RDL 1614相鄰但不位在晶粒RDL 1614上方的通路開口1618,該蝕刻暴露模塑料1622表面,其形成通路開口1618的底部。
圖19係根據實施例說明在形成間隔物1802之後的第二蝕刻之橫切面圖式。在一些實施例中,參閱圖8,如上所述,選擇性蝕刻隔離層1702。通路開口1618延伸至RDL 1614與1616中的下方傳導元件1610,暴露傳導元件1610的上表面。在此實施例中,間隔物1802僅部分延伸穿過通路開口1618,間隔物1802的底部表面係位於晶粒RDL 1614上或是位於模塑料1622內。然而,間隔物1802係位於晶粒基板1612側壁上的通路開口1618中,將晶粒基板1612與通路開口1618及後續形成的通路電絕緣。已經發現該部分高度自對準間隔物1802容許以單一遮罩蝕刻晶粒RDL以及RDL 1614與1616。在第二蝕刻的過程中,間隔物1802位於晶粒RDL 1614的側壁。所得到的通路開口1618具有下部,其側壁係與間隔物1802之內表面實質上齊平、同水平(level)、均平(even)或對準。在一些實施例中,模塑料1622係延伸於晶粒基板1012的頂部表面上方,間隔物1802係約從晶粒基板1612的底部表面延伸至模塑料1622的頂部表面或是延伸超過模塑料1622的頂部表面。
圖20係根據實施例說明形成通路2002的橫切面圖式。在一些實施例中,參閱圖11,如上所述,在通路開口1618中形成通路2002(參閱圖17)。藉由間隔物1802而將通路2002與晶粒基板1612絕緣,通路2002自封裝的頂部表面延伸穿過晶粒基板1612至RDL 1614與1616中的傳導元件1610。
雖然所述的實施例係具有部分高度間隔物1802將通路2002與晶 粒基板1612絕緣,但是該等實施例並不受限於所述內容。例如,在一些實施例中,部分高度間隔物1802係位於晶圓基板1620中,通路2002係從封裝的晶圓側延伸至RDL 1614與1616。
圖21至29係根據實施例說明使用雙鑲嵌後鑽孔製程形成晶片堆疊晶圓結構中的中間製程步驟之橫切面圖式。圖21係根據實施例說明在晶粒2102接合至晶圓2104的上方形成模塑料2116之橫切面圖式。晶粒2102與晶圓2104分別具有晶粒基板2106與晶圓基板2112,其具有一或多個主動裝置。晶粒RDL 2108與晶圓RDL 2114係位於個別基板2106與2112上,並且包括具有傳導元件2110位於其上的介電層,該傳導元件2110中的一些係與個別基板2106及2112中的主動裝置接觸。晶粒2102與晶圓2104的接合如上所述,使得晶粒RDL 2108與晶圓RDL 2114接觸,並且形成接合界面2118。如上所述,模塑料2116形成於晶粒2102與晶圓2104上方,並且在一些實施例中,模塑料2116係延伸於晶粒2102上方。
圖22係根據實施例說明在封裝上形成第一遮罩2202的橫切面圖式。在此實施例中,第一遮罩2202係形成於模塑料2116上方,並且被圖案化以形成開口2204。在一些實施例中,第一遮罩2202係被沉積、曝光與顯影的光阻。在RDL 2108及2114中的傳導元件2110上方,第一遮罩2202中的開口2204對準。已經發現形成通路開口的雙鑲嵌技術容許免用蝕刻停止層以及蝕刻停止層的相關蝕刻。在此實施例中,第一遮罩2202係位於模塑料2116上。
圖23係根據實施例說明蝕刻晶粒基板2106的橫切面圖式。形成通路開口2302穿過模塑料2116,以及穿過晶粒基板2106,以暴露晶粒RDL 2108。在實施例中,如上所述,蝕刻通路開口2302。與晶粒基板2106相鄰但不位在晶粒基板2106上方的通路開口2302係部分延伸穿過模塑料2116。
圖24係根據實施例說明使用第二遮罩2402的橫切面圖式。在一些實施例中,通路開口2302的第一蝕刻穿過晶粒基板2106之後,移除第一遮罩2202。第二遮罩2402形成於基板上方,延伸至通路開口2302中。例如,在一些實施例中,第二遮罩2402係使用旋塗、噴塗或類似方式而沉積的光阻。
圖25係根據實施例說明將第二遮罩2402圖案化的橫切面圖式。在一些實施例中,將第二遮罩2402曝光與顯影,以將第二遮罩2402圖案化形成第二遮罩開口2502。在一些實施例中,在第一蝕刻之後,第二遮罩開口2502比通路開口2302寬,該第二遮罩開口2502係位於通路開口2302上方。此外,在一些實施例中,第二遮罩開口2502定義用於金屬跡線的開口,該金屬跡線自通路開口側向延伸以提供電連接至後續形成於通路開口2302之下部中的通路。
圖26係根據實施例說明蝕刻RDL 2108與2114的橫切面圖式。蝕刻RDL 2108與2114,以及移除第二遮罩2402。在一些實施例中,使用時間模式蝕刻製程,使得蝕刻製程蝕刻預定深度。使用第二遮罩的蝕刻造成通路開口2302的上部之寬度大於通路開口2302的下部之寬度。該時間模式蝕刻控制通路開口2302的上部之深度,並且造成通路開口2302的下部向下延伸以暴露下方的傳導元件2110.
圖27係根據實施例說明形成隔離層2702的橫切面圖式。保形介電隔離層2702係形成於模塑料2116上方,並且延伸至通路開口2302中。在實施例中,隔離層2702的形成如上所述。該隔離層2702延伸至各個通路開口2302中,並且覆蓋通路開口2302的側壁,包含在通路開口2302中暴露的部分晶粒基板2106。
圖28係根據實施例說明形成自對準間隔物2802的橫切面圖式。在一些實施例中,如上所述蝕刻該隔離層2702(參閱圖27),移除隔離層2702的側部,並且在通路開口2302的側壁上留下間隔物2802。間隔 物2802將晶粒基板2106與通路開口2302絕緣,並且暴露傳導元件2110的部分頂部表面。在一些雙鑲嵌實施例中,在通路開口2302的上部與下部中,形成分離的間隔物2802,上方與下方間隔物2802彼此側向分離,並且暴露成形材料2116的側表面。此外,下方間隔物2802從晶粒基板2106上的RDL 2108與2114中的傳導元件2110延伸至模塑料2116中。
圖29係根據實施例說明在通路開口702中形成通路2902的橫切面圖式。在一些實施例中,通路2902的形成如上所述。藉由間隔物2802而將通路2902與晶粒基板2106絕緣,該通路2902從模塑料2116的頂部表面延伸至傳導元件2110。在一些實施例中,通路2902的頂部部分側向延伸穿過模塑料2116的頂部部分,形成模塑料2116中的頂部RDL之第一層。在第二蝕刻之後形成間隔物2802,使得在通路開口2302內,形成全高度的間隔物。在一些實施例中,在通路開口2302中,形成阻障層、晶種層與金屬層,而後使用CMP或類似方法進行減縮。因此,形成頂部RDL的第一層之傳導元件之不同步驟可被合併在通路形成製程中,以降低成本與增加生產量。
圖30係說明形成具有透過後鑽孔製程所形成的多組通路之晶片堆疊晶圓結構中的中間製程步驟之橫切面圖式,其中該製程使得三或更多個晶粒堆疊為3D晶片堆疊晶圓堆疊基板封裝。已經發現後鑽孔製程可對於具有間距(pitch)為10微米或更小之堆疊晶粒提供晶片間連接性(inter-chip connectivity),並且不需要錫球或微凸塊於堆疊晶片之間而提供改良的間距。此外,後鑽孔製程容許晶片直接接合,而不需要接合的RDL中之金屬接墊於接合製程中接觸。該後鑽孔製程進一步容許堆疊不同寬度的晶粒而不需要額外的製程步驟,這是由於後鑽孔製程可在與形成通路穿過堆疊晶粒的相同製程步驟中形成通路穿過模塑料,並且容許使用扇出通路布局(fan-out via layouts)。
圖30係根據實施例說明形成具有多層通路之封裝3000中的初始步驟之橫切面圖式。一開始,提供第一晶粒3002。在該第一晶粒3002上,安置一或多個第二晶粒3008。第一晶粒3002包含具有第一RDL 3006之第一基板3004,以及第二晶粒3008各自具有第二基板3010與第二RDL 3012。傳導元件3014係位於RDL 3006與3012中,並且電連接至個別的基板3004與3010。在一些實施例中,使用直接接合技術,將第二晶粒3008接合至第一晶粒3002。例如,在一些實施例中,第二晶粒3008具有使用氧化物對氧化物接合而接合至第一RDL 3006的第二RDL 3012。在其他實施例中,使用混合接合技術或其他接合技術,而將第二晶粒3008以黏著劑接合至第一晶粒3002。
雖然本申請案所述之實施例說明兩個第二晶粒3008接合至單一第一晶粒3002,但是該實施例係作為說明而非限制本申請案。例如,在其他實施例中,單一第二晶粒3008係接合至單一第一晶粒3002或接合至多個第一晶粒3002。此外,第二晶粒3008比第一晶粒3002窄,在第一RDL 3006上,留下不被任何第二晶粒3008覆蓋的間隔(space)。然而,繪示第二晶粒3008相對於第一晶粒3002的寬度與配置,以說明扇出配置(fan-out arrangement),而非用以限制本申請案。
在第一晶粒3002與第二晶粒3008上方,形成第一模塑料3016。在實施例中,參閱圖3、16或21,形成如上所述之第一模塑料3016。在一些實施例中,模塑料3016延伸於第二晶粒3008的上方,並且填充第二晶粒3008之間的區域以及在第一晶粒3002上方相鄰於第二晶粒的區域。在其他實施例中,將第一模塑料3016平面化而與第二基板3010的頂部表面約同水平或齊平。
圖31係根據一些實施例說明形成第一通路3102穿過第二晶粒3008至第一RDL 3006與第二RDL 3012的橫切面圖式。為求方便,多個個別的第一通路3102A...3102F係統稱為第一通路3102。本申請案 所揭示的第一通路3102係由雙鑲嵌後鑽孔技術所形成,如圖21-29所示,然而,亦可使用其他後鑽孔技術以形成通路3102。例如,在一些實施例中,根據圖1至15所示的實施例,形成具有完整間隔(full space)的第一通路3102,或是根據圖16至20所示之實施例,形成具有部分高度的第一通路3102。
形成第一通路3102,穿過第二晶粒3008至RDL 3006與3012中的傳導元件3014,其將第一通路3102電連接至第一基板3004或第二基板3010。在一些實施例中,第一通路3102將第一基板3004連接至第二基板3010其中之一。例如,第一通路3102D連接至第二RDL 3012其中之一中的傳導元件3104以及連接至第一RDL 3006中的傳導元件3014,在第一晶粒3002與第二晶粒3008之間提供晶片間連接性。此外,在一些實施例中,第一通路3102F延伸穿過相鄰於第二晶粒3008的第一模塑料3016而至第一RDL 3006中的傳導元件3014。在一些實施例中,第一通路3102E具有部分側向延伸穿過扇出架構中的第一模塑料3016。
圖32係根據一些實施例說明將第三晶粒3202安置在封裝3000上的橫切面圖式。第三晶粒3202具有第三基板3204與第三RDL 3206,並且安置於第二晶粒3008上方。第三RDL 3206具有連接至第三基板3204的一或多個傳導特徵3104。在第一模塑料3016延伸於第二晶粒3008上方的實施例中,第三晶粒3202係安置於第一模塑料3016的頂部表面上,以及在第二晶粒3008透過第一模塑料3016而暴露的實施例中,第三晶粒3202係安置於第二晶粒3008與第一模塑料3016的頂部表面上。第三晶粒3202係以晶粒附接膜(DAF)、黏著劑、直接表面接合或其他製程而固定於封裝。第二模塑料3208係形成於第三晶粒3202附近,並且在一些實施例中,係形成如上所述用於第一模塑料3016。在其他實施例中,在將第三晶粒3202安置於封裝3000之前,於第三晶粒 3202附近形成第二模塑料3208。
本申請案揭示第三晶粒3202係直接安置於第一模塑料3016的頂部表面上;然而,該實施例並不受限於此結構。在其他實施例中,在安置第三晶粒3202之前,在封裝3000上方,形成一或多個中間層(未繪示)。例如,在第一模塑料3016或第二晶粒3008上方,形成介電層、保護層、鈍化層或是其他層,第三晶粒3202係安置至該中間層。
圖33係根據一些實施例說明形成第二通路3302穿過第三晶粒3202與第二模塑料3208之橫切面圖式。為求方便,多個個別第二通路3302A...3302G係統稱為第二通路3302。類似於第一通路3102,本申請案所述之第二通路3302係由雙鑲嵌後鑽孔技術形成,但是在其他實施例中,係以完全高度間隔物或是部分高度間隔物技術而形成。此外,雖然第一通路3102與第二通路3302係以相同技術形成,但是在一些實施例中,使用不同的通路形成技術,形成不同的通路層。
在一些實施例中,一或多個第二通路3302係延伸穿過第三基板3204以接觸第三RDL 3206中的傳導元件3104。例如,第二通路3302D與3302E延伸至第三RDL 3206中的傳導元件3104,以於第三基板3204與後續形成的外部連接裝置之間提供電力或是通訊連接性。在此範例中,第二通路3302D與3302在第三RDL 3206內結束,並且與第一模塑料3016絕緣。這使得第一通路3102位於第二通路3302下方,而不接觸第二通路3302。例如,第一通路3102D在第一晶粒3002與第二晶粒3008之間提供晶片間連接性,但不需要至外部連接裝置的連接性,並且可在第二通路3302D的下方對準,該第二通路3302D係在第三RDL 3306中結束。因此,第一通路3102D係與第二通路3302電絕緣。在另一範例中,第一通路3102E係從下方的第二通路3302E側向延伸,該第二通路3302E係於第三RDL 3206中結束。不同的第二通路3302,例如第二通路3302F,係於第一通路3102E與後續形成的外部連接裝置 之間提供連接性。
此外,在一些實施例中,一或多個第二通路3302延伸穿過第三RDL 3206,以接觸第一通路3102的頂部表面。例如,第二通路3302B延伸穿過第三RDL 3206,並且接觸第一通路3102B的頂部表面,以於第一基板3304與後續形成的外部連接裝置之間提供電力或通訊連接性。
在一些實施例中,一或多個第二通路3302接觸第三RDL 3206中的傳導元件3104以及第一通路3102。因此,可在第三基板3204與第一基板3004或第二基板3010之間提供通訊連接性。例如,第二通路3302A係接觸第三RDL 3206中的傳導元件3104,並且延伸穿過該傳導元件3104以接觸第一通路3102A。第一通路3102A係接觸第二RDL 3012中的傳導元件3104,其依序連接至第二基板3010。同樣地,第二通路3302C係接觸第三RDL 3206中的傳導元件3104,並且延伸穿過該傳導元件3104,以接觸第一通路3102C。第一通路3102C接觸第一RDL 3006中的傳導元件3104,其依序連接至第一基板3004。因此,藉由第一通路3102與第二通路3302,在第三基板3204與第一基板3004或第二基板3010之間,提供晶片間連接。
在一些實施例中,第一晶粒3002係比第三晶粒3202寬。在此實施例中,一部分的第二模塑料3208係位於與第三晶粒3202相鄰的第一模塑料3016上方。形成第二通路3302穿過部分的第二模塑料3208,其係與第三晶粒3202相鄰。例如,在一些實施例中,第二通路3302G延伸穿過第二模塑料3208,以接觸標準或垂直的第一通路3102F之頂部表面,其延伸至第一RDL 3006中並且接觸傳導元件3104。在另一範例中,第二通路3302F係延伸穿過第二模塑料3208,以接觸部分第一通路3102E的頂部表面,其側向延伸穿過扇出架構中的第一模塑料3016。因此,可提供電力或資料通訊至第一晶粒或第二晶粒3008,而 不需要第二通路3102穿過第三通路3202。例如,使用此配置,第三晶粒3202比第一晶粒3002窄。
此外,雖然本申請案所述之第三晶粒3202之寬度與第二晶粒3008的寬度相同,但是在一些實施例中,第二晶粒3008延伸超過第三晶粒3202的邊緣。在此實施例中,在第二晶粒3008上方,直接沉積第二通路3302。第二通路3302延伸穿過第二模塑料3208,以接觸第一通路3102,其係垂直延伸穿過第二晶粒3008。或者,在其他實施例中,第三晶粒3202係比第二晶粒3008寬,並且延伸穿過第二晶粒3008。在此實施例中,側向沉積一或多個第二通路3302以與第二晶粒3008相鄰或是在第二晶粒3008的邊緣外部,並且該一或多個第二通路3302係延伸穿過第三晶粒3202,以接觸第一通路3102,其係延伸穿過與第二晶粒3008相鄰之部分的第一模塑料3016。此外,在一些實施例中,使用扇入配置(fan-in arrangement),第一通路3102與第二通路3302各自延伸穿過基板。在此實施例中,第一晶粒3002、第二晶粒3008以及第三晶粒3202具有邊緣,該邊緣實質上係與被排除的通路3102F/3302G或3302F對準。
雖然本申請案所揭示的封裝3000具有三層晶粒,但是封裝3000並不受限於此實施例。在其他實施例中,在第三晶粒3202上方,形成一或多層附加層,附加通路延伸穿過各層以接觸下方層中的通路。再者,在一些實施例中,形成通路穿過封裝3000的頂部與底部側。在此實施例中,在封裝的兩側上,形成附加層與附加晶粒。
圖34係根據一些實施例說明在第二模塑料3208上方形成頂部RDL 3402之橫切面圖式。在一些實施例中,使用類似於圖12至15所述之製程,形成頂部RDL 3402、保護層3406以及連接裝置3408。頂部RDL 3402具有頂部RDL介電層3404,其具有一或多個頂部RDL傳導元件3410,其將一或多個第二通路3302連接至連接裝置3408。保護層3406 係位於頂部RDL 3402上方,連接裝置3408延伸穿過保護層3406中的開口,以接觸頂部RDL傳導元件3410。連接裝置3408係電連接至第二通路3302,以通路對3302B/3102B或是3102F/3302G提供電力或資料連接性至第一晶粒3002、以通路對3102E/3302F提供電力或資料連接性至第二晶粒3008,或是以通路3302D或3302E提供電力或資料連接性至第三晶粒3202。
在一些實施例中,在第三晶粒3202與第一晶粒3002或第二晶粒3008之間提供晶片間連接性的第二通路3302係與連接裝置3408電絕緣,而提供電力或資料連接性至晶粒3002、3008或3202的第二通路3302係電連接至連接裝置3408。例如,第二通路3302A接觸第三RDL 3206中的傳導元件3104以及第一通路3102A。第一通路3102依序接觸第二RDL 3012中的傳導元件3104。因此,藉由第二通路3302A與第一通路3102A,在第三晶粒3202與第二晶粒3008之間,提供晶片間連接性。在此範例中,第二通路3302未連接至連接裝置3408,並且藉由頂部RDL介電層3404而在頂部表面電絕緣。
一些第二通路3302與連接裝置3408絕緣,不需要頂部RDL傳導元件3410於一些第二通路3302上方或是連接至一些第二通路3302。因此,在一些實施例中,連接裝置3408的間距(pitch)或配置係不同於第二通路3302的間距或配置。此外,一些頂部RDL傳導元件3410係側向延伸於第二通路3302的上方,該第二通路3302係與連接裝置3408絕緣。
圖35係根據一些實施例說明將封裝3000安置於第二封裝3502上的橫切面圖式。藉由連接裝置3408而將封裝3000安置至第二封裝3502,其可為基板、晶粒、PCB、晶片或是其他表面。在一些實施例中,第二封裝3502具有與連接裝置3408相對立的一或多個第二連接裝置3504。此外,在一些實施例中,藉由黏著層3508或是藉由其他接合 材料或熱黏著劑,將例如散熱片(heat sink)3506之散熱結構附接至封裝3000。此外,雖未繪示,在一些實施例中,附加的晶粒安置在第二封裝3502上,並且透過第二封裝而與封裝3000電通訊。
因此,根據實施例,封裝包括第一晶粒與第二晶粒,該第一晶粒具有位在第一基板的第一側上之第一重佈層(RDL),該第二晶粒具有位在第二基板的第一側上之第二RDL。該第一RDL係接合至該第二RDL。第三晶粒具有位在第三基板的第一側上之第三RDL。該第三晶粒係安置於該第二晶粒上方,該第二晶粒係位於該第一晶粒與該第三晶粒之間。第一通路延伸穿過該第二基板,並且與該第二基板電隔離,該第一通路各自接觸該第一RDL或該第二RDL中的傳導元件。第二通路延伸穿過該第三基板,並且與該第三基板電隔離,該第二通路各自接觸該第三RDL中的傳導元件或該第一通路其中之一。
根據另一實施例,封裝包括第一晶粒與第二晶粒,該第一晶粒具有位在第一基板上的第一重佈層(RDL),該第二晶粒具有位在第二基板上的第二RDL。該第二晶粒係位於該第一晶粒上方,該第二RDL接合至該第一RDL。第一模塑料係位於該第一晶粒上方並且位於該第二晶粒附近。第三晶粒具有位於第三基板上的第三RDL,該第三晶粒係位於該第一模塑料上方。第二模塑料係位於該第一模塑料上方並且位於該第三晶粒附近。第一通路延伸穿過該第二基板,並且各自接觸該第一RDL或該第二RDL中的至少一傳導元件。第一間隔物係將該第一通路與該第二基板電絕緣。第二通路延伸穿過該第三基板,並且各自接觸該第三RDL中的傳導元件或是該第一通路其中之一。第二間隔物係將該第二通路與該第三基板電絕緣。
根據實施例,方法包括提供第一晶粒,該第一晶粒具有位於第一基板上的第一重佈層(RDL),該第一RDL包括第一氧化物層,以及提供第二晶粒,該第二晶粒具有位於第二基板上的第二RDL,該第二 RDL包括第二氧化物層。以氧化物對氧化物接合,藉由將該第一氧化物層接合至該第二氧化物層,使得該第一晶粒接合至第二晶粒。在接合該第一晶粒至該第二晶粒之後,在該第二晶粒中,形成第一開口。該第一開口延伸穿過該第二基板,並且暴露該第一RDL或該第二RDL中的第一傳導元件。在該第一開口中,形成第一通路,該第一通路延伸穿過該第二基板,並且各自接觸個別的該第一傳導元件。該第一通路係與該第二基板電絕緣。第三晶粒係安置於該第二晶粒上方,該第三晶粒具有位於第三基板上的第三RDL。在安置該第三晶粒於該第二晶粒上方之後,在該第三晶粒中,形成第二開口。第二開口各自延伸穿過該第三基板,並且暴露該第一通路其中之一或是該第三RDL中的第二傳導元件。在該第二開口中,形成第二通路,該第二通路延伸穿過該第三基板並且接觸個別的該第二傳導元件或是該第一通路其中之一。該第二通路係與該第三基板電絕緣。
前述內容概述一些實施方式的特徵,因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎,用於設計或修飾其他製程與結構而實現與本申請案所述之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍,以及熟知此技藝之人士可進行各種變化、取代與替換,而不脫離本申請案揭示內容之精神與範圍。
3000‧‧‧封裝
3002‧‧‧第一晶粒
3408‧‧‧連接裝置
3502‧‧‧第二封裝
3504‧‧‧第二連接裝置
3506‧‧‧散熱片
3508‧‧‧黏著層

Claims (10)

  1. 一種3D堆疊晶片封裝,其包括:第一晶粒,其具有位於第一基板的第一側上之第一重佈層(RDL);第二晶粒,其具有位於第二基板的第一側上之第二RDL,該第一RDL接合至該第二RDL;第三晶粒,其具有位於第三基板的第一側上之第三RDL,該第三晶粒係安置於該第二晶粒上方,該第二晶粒係位於該第一晶粒與該第三晶粒之間;第一通路,其延伸穿過該第二基板並且與該第二基板電隔離,該第一通路各自接觸該第一RDL或該第二RDL中的傳導元件;以及第二通路,其延伸穿過該第三基板並且與該第三基板電隔離,該第二通路各自接觸該第三RDL中的傳導元件或是該第一通路其中之一。
  2. 如請求項1所述之封裝,其中該第一RDL係直接接合至該第二RDL。
  3. 如請求項1所述之封裝,進一步包括:第一間隔物,其係插入該第二基板與一或多個該第一通路之間,並且各自延伸穿過該第二基板;以及第二間隔物,其係插入該第三基板與一或多個該第二通路之間,並且各自延伸穿過該第三基板。
  4. 一種3D堆疊晶片封裝,其包括:第一晶粒,其具有位於第一基板上的第一重佈層(RDL);第二晶粒,其具有位於第二基板上的第二RDL,該第二晶粒 係位於該第一晶粒上方,該第二RDL係接合至該第一RDL;第一模塑料,其係位於該第一晶粒上方並且位於該第二晶粒周圍;第三晶粒,其具有位於第三基板上的第三RDL,該第三晶粒係位於該第一模塑料上方;第二模塑料,其係位於該第一模塑料上方並且位於該第三晶粒周圍;第一通路,其延伸穿透該第二基板,並且各自接觸該第一RDL或該第二RDL中的至少一傳導元件,其中第一間隔物係將該第一通路與該第二基板電絕緣;以及第二通物,其延伸穿過該第三基板,並且各自接觸該第三RDL中的傳導元件或是該第一通路其中之一,其中第二間隔物係將第二通路與該第三基板電絕緣。
  5. 如請求項4所述之封裝,其中該第一模塑料係於該第二晶粒上方延伸;其中該第一通路各自具有上部,該上部比下部寬;以及其中該各個該第一通路的該上部係位於該第二晶粒上。
  6. 如請求項4所述之封裝,其中至少一該第二通路係從該第二模塑料的頂部表面延伸穿過該第二模塑料的底部表面至該第一RDL。
  7. 如請求項4所述之封裝,其中第一個該第一通路係接觸該第一RDL中的傳導元件以及該第二RDL中的傳導元件;其中該第一個該第一通路係與該第二通路電絕緣;以及其中該第二通路之一的至少一部分係於該第一個該第一通路上方直接對準。
  8. 如請求項4所述之封裝,其中至少第二個該第一通路具有頂部部分側向延伸超過該第二晶粒的邊緣;以及 其中該第二通路之一係延伸穿過與該第三晶粒相鄰之該第二模塑料,並且接觸該第二個該第一通路的該頂部部分。
  9. 一種3D堆疊晶片封裝的製造方法,其包括:提供第一晶粒,其具有位於第一基板上的第一重佈層(RDL),該第一RDL包括第一氧化物層;提供第二晶粒,其具有位於第二基板上的第二RDL,該第二RDL包括第二氧化物層;用氧化物對氧化物接合,藉由接合該第一氧化物層至該第二氧化物層,將該第一晶粒接合至該第二晶粒;將該第一晶粒接合至該第二晶粒之後,在第二晶粒中,形成第一開口,該第一開口延伸穿過該第二基板,並且暴露該第一RDL或該第二RDL中的第一傳導元件;在第一開口中,形成第一通路,該第一通路延伸穿過該第二基板,並且各自接觸個別的該第一傳導元件,其中該第一通路係與該第二基板電絕緣;將第三晶粒安置於該第二晶粒上方,該第三晶粒具有位於第三基板上的第三RDL;將該第三晶粒安置於該第二晶粒上方之後,在第三晶粒中,形成第二開口,該第二開口各自延伸穿過該第三基板,並且暴露該第一通路之一或是該第三RDL中的第二傳導元件;以及在該第二開口中,形成第二通路,該第二通路延伸穿過該第三基板,並且各自接觸個別的該第二傳導元件或是個別的該第一通路,其中該第二通路係與該第三基板電絕緣。
  10. 如請求項9所述之方法,進一步包括:在形成該第一通路之前,形成第一模塑料於該第一晶粒上方以及該第二晶粒周圍;以及 在形成該第二通路之前,形成第二模塑料於該第三晶粒周圍。
TW103138145A 2014-04-30 2014-11-04 3d堆疊的晶片封裝 TWI567925B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201461986653P 2014-04-30 2014-04-30
US14/462,791 US9666520B2 (en) 2014-04-30 2014-08-19 3D stacked-chip package

Publications (2)

Publication Number Publication Date
TW201541606A TW201541606A (zh) 2015-11-01
TWI567925B true TWI567925B (zh) 2017-01-21

Family

ID=54355783

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103138145A TWI567925B (zh) 2014-04-30 2014-11-04 3d堆疊的晶片封裝

Country Status (4)

Country Link
US (3) US9666520B2 (zh)
KR (1) KR101752543B1 (zh)
CN (1) CN105047651B (zh)
TW (1) TWI567925B (zh)

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9258952B2 (en) * 2009-10-07 2016-02-16 Rain Bird Corporation Volumetric budget based irrigation control
US9379078B2 (en) * 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9754918B2 (en) * 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US9449837B2 (en) * 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
KR20150139255A (ko) 2014-06-03 2015-12-11 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US10354958B2 (en) * 2014-10-01 2019-07-16 Nxp Usa, Inc. Through package circuit in fan-out wafer level package
US9559081B1 (en) * 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US10163859B2 (en) * 2015-10-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
US9859156B2 (en) 2015-12-30 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure with sidewall dielectric protection layer
US9786619B2 (en) * 2015-12-31 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9620465B1 (en) * 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
CN107622992B (zh) * 2016-07-14 2021-04-27 联华电子股份有限公司 半导体元件及其制作方法
US10332841B2 (en) * 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US9786586B1 (en) * 2016-08-21 2017-10-10 Micron Technology, Inc. Semiconductor package and fabrication method thereof
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TWI824467B (zh) 2016-12-14 2023-12-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US10784198B2 (en) * 2017-03-20 2020-09-22 Samsung Electronics Co., Ltd. Power rail for standard cell block
US10672729B2 (en) * 2017-03-30 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming package structure
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10522449B2 (en) * 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
US10276439B2 (en) * 2017-06-02 2019-04-30 International Business Machines Corporation Rapid oxide etch for manufacturing through dielectric via structures
DE102017120875B4 (de) * 2017-06-15 2022-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Vorrichtung und Verfahren mit RDL-Last-Prozess-Geformtem Gehäuse
US10541228B2 (en) 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10361158B2 (en) * 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch
US10714421B2 (en) 2017-08-29 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with self-aligned conductive features
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10290571B2 (en) * 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
DE102018116750A1 (de) * 2017-09-29 2019-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und Herstellungsverfahren
US10727217B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
KR101942742B1 (ko) * 2017-10-26 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
US10163758B1 (en) * 2017-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method for the same
US11031342B2 (en) * 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US11557536B2 (en) 2017-12-27 2023-01-17 Intel Corporation Integrated circuits (IC's) with electro-migration (EM)—resistant segments in an interconnect level
EP3732704A4 (en) 2017-12-27 2021-07-28 INTEL Corporation INTEGRATED LINE BREAKAGE AND LINE BRIDGE CIRCUITS IN A SINGLE INTERCONNECTION LEVEL
WO2019132885A1 (en) 2017-12-27 2019-07-04 Intel Corporation Metal-insulator-metal (mim) structure supporting high voltage applications and low voltage applications
US11502031B2 (en) 2017-12-27 2022-11-15 Intel Corporation Multiple layer metal-insulator-metal (MIM) structure
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10727205B2 (en) * 2018-08-15 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding technology for stacking integrated circuits
CN109148415B (zh) 2018-08-28 2020-08-25 武汉新芯集成电路制造有限公司 多晶圆堆叠结构及其形成方法
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10700041B2 (en) * 2018-09-21 2020-06-30 Facebook Technologies, Llc Stacking of three-dimensional circuits including through-silicon-vias
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
TWI680557B (zh) * 2018-11-23 2019-12-21 南亞科技股份有限公司 半導體封裝結構及其製備方法
US10607924B1 (en) 2018-11-23 2020-03-31 Nayna Technology Corporation Semiconductor package structure and method for preparing the same
US11081467B2 (en) * 2018-12-28 2021-08-03 Micron Technology, Inc. Apparatuses and methods for arranging through-silicon vias and pads in a semiconductor device
US11024586B2 (en) * 2019-01-22 2021-06-01 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11600519B2 (en) * 2019-09-16 2023-03-07 International Business Machines Corporation Skip-via proximity interconnect
US11856800B2 (en) * 2019-09-20 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with system on chip devices
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11211371B2 (en) * 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11362036B2 (en) * 2020-01-06 2022-06-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11488901B2 (en) * 2020-04-29 2022-11-01 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
KR20220058682A (ko) 2020-10-29 2022-05-10 삼성전자주식회사 반도체 장치
KR20220075030A (ko) 2020-11-26 2022-06-07 삼성전자주식회사 반도체 패키지
EP4203002A4 (en) * 2021-03-24 2024-05-22 Changxin Memory Technologies, Inc. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHODS THEREFOR
KR20240058890A (ko) * 2021-09-16 2024-05-03 소니 세미컨덕터 솔루션즈 가부시키가이샤 반도체 장치, 및 반도체 장치의 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050104219A1 (en) * 2003-09-26 2005-05-19 Kuniyasu Matsui Intermediate chip module, semiconductor device, circuit board, and electronic device
TW201208004A (en) * 2010-08-13 2012-02-16 King Dragon Internat Inc Semiconductor device package structure and forming method of the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
US20080116584A1 (en) * 2006-11-21 2008-05-22 Arkalgud Sitaram Self-aligned through vias for chip stacking
KR100895813B1 (ko) * 2007-06-20 2009-05-06 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
US8946873B2 (en) 2007-08-28 2015-02-03 Micron Technology, Inc. Redistribution structures for microfeature workpieces
US8350377B2 (en) 2008-09-25 2013-01-08 Wen-Kun Yang Semiconductor device package structure and method for the same
TWI402941B (zh) * 2009-12-03 2013-07-21 Advanced Semiconductor Eng 半導體結構及其製造方法
US8822281B2 (en) 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
CN102914832A (zh) * 2011-08-05 2013-02-06 快捷半导体(苏州)有限公司 晶片级成型的光耦合器
US20130040423A1 (en) 2011-08-10 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Multi-Chip Wafer Level Packaging
WO2013062590A1 (en) 2011-10-28 2013-05-02 Intel Corporation 3d interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
US9059109B2 (en) 2012-01-24 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package assembly and method of forming the same
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US10269619B2 (en) 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US9754918B2 (en) * 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US9711379B2 (en) 2014-04-30 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9449837B2 (en) 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US9905436B2 (en) * 2015-09-24 2018-02-27 Sts Semiconductor & Telecommunications Co., Ltd. Wafer level fan-out package and method for manufacturing the same
US10163859B2 (en) * 2015-10-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
KR102600694B1 (ko) 2016-10-28 2023-11-09 엘지디스플레이 주식회사 백색 발광 영역을 포함하는 디스플레이 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050104219A1 (en) * 2003-09-26 2005-05-19 Kuniyasu Matsui Intermediate chip module, semiconductor device, circuit board, and electronic device
TW201208004A (en) * 2010-08-13 2012-02-16 King Dragon Internat Inc Semiconductor device package structure and forming method of the same

Also Published As

Publication number Publication date
KR20150125582A (ko) 2015-11-09
TW201541606A (zh) 2015-11-01
US20150318263A1 (en) 2015-11-05
US20190355640A1 (en) 2019-11-21
CN105047651A (zh) 2015-11-11
KR101752543B1 (ko) 2017-07-11
US10971417B2 (en) 2021-04-06
US9666520B2 (en) 2017-05-30
US20170263519A1 (en) 2017-09-14
CN105047651B (zh) 2018-05-25
US10373885B2 (en) 2019-08-06

Similar Documents

Publication Publication Date Title
TWI567925B (zh) 3d堆疊的晶片封裝
US10096571B2 (en) Chip-on-wafer package and method of forming same
US9698081B2 (en) 3D chip-on-wafer-on-substrate structure with via last process
US10535631B2 (en) 3D Chip-on-wager-on-substrate structure with via last process
US9711379B2 (en) 3D stacked-chip package
US11430670B2 (en) Stacked semiconductor devices and methods of forming same
US10879183B2 (en) Semiconductor device and method of manufacture
US9564420B2 (en) Functional block stacked 3DIC and method of making same
CN107039249B (zh) 分割和接合方法及其形成的结构
CN113990855A (zh) 封装件及制造方法
CN112582389A (zh) 半导体封装件、封装件及其形成方法
US11594420B1 (en) Semiconductor structure and manufacturing method thereof