CN106409702A - 一种多芯片堆叠封装结构及其制作方法 - Google Patents
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Abstract
本发明提供一种多芯片堆叠封装结构及其制作方法,所述封装结构包括:封装基板、多个芯片及多个可弯折基板,所述多个芯片中的一个芯片通过焊球或凸点贴装在所述封装基板上,剩余芯片分别通过焊球或凸点贴装在一个可弯折基板上,所述贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,从而实现芯片的堆叠结构,所述可弯折基板上设置有上下位置对齐的焊盘,所述可弯折基板弯折后使得其上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘与所述封装基板上的焊盘焊接在一起,从而使得可弯折基板与封装基板固定在一起,并实现所有芯片之间及芯片与封装基板之间的互连。本发明能够实现多芯片的堆叠及封装,其工艺简单、可靠性高、成本较低。
Description
技术领域
本发明涉及半导体封装技术领域,尤其涉及一种多芯片堆叠封装结构及其制作方法。
背景技术
随着集成电路技术的发展,集成电路的封装技术也在不断的提高,其发展方向主要向轻、薄、短、小的多元化发展,并且对集成度的要求也越来越高;要求在给定的空间上集成更多的芯片装置。这种需求推动了三维封装技术的不断发展,出现了以芯片堆叠、TSV(Through silicon via,穿透硅通孔)技术、CSP(Chip scale package,芯片级封装)及WLP(Wafer level packaging,晶圆级封装)为代表的先进封装形式。芯片堆叠作为三维封装的一种,具有集成度高、性比价高、工艺成熟等优点,在实际工业生产过程中获得了很多应用。专利1(申请号201210306562.X)采用倒装和压焊的方式实现了WLCSP多芯片堆叠封装;专利2(申请号201110214210.7)采用较大的顶部封装焊球实现了两个封装结构的堆叠;专利3(申请号201080045165.0)和专利4(申请号201110384864.4)采用穿透硅通孔(TSV)技术实现多芯片之间的堆叠和互连。
在实现本发明的过程中,发明人发现现有技术中至少存在如下技术问题:
随着集成度的不断提高,当堆叠芯片数量较多时,采用专利1的方案实现三维封装会带来很大的工艺难度和可靠性问题。同时受到焊球回流次数的限制,专利2同样不能实现过多封装体的堆叠,一般不大于2个。专利3和专利4虽然可以很方便地实现多芯片的三维堆叠和高效互连,但其工艺复杂、可靠性不高、成本较高。
发明内容
本发明提供的一种多芯片堆叠封装结构及其制作方法,能够实现多芯片的堆叠、互连及封装,其工艺简单、可靠性高、成本较低。
第一方面,本发明提供一种多芯片堆叠封装结构,所述封装结构包括:封装基板、多个芯片及多个可弯折基板,所述多个芯片中的一个芯片通过焊球或凸点贴装在所述封装基板上,剩余芯片分别通过焊球或凸点贴装在一个可弯折基板上,所述贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,从而实现芯片的堆叠结构,所述可弯折基板上设置有上下位置对齐的焊盘,所述可弯折基板弯折后使得其上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘与所述封装基板上的焊盘焊接在一起,从而使得可弯折基板与封装基板固定在一起,并实现所有芯片之间及芯片与封装基板之间的互连。
可选地,还包括塑封料,所述塑封料对所述可弯折基板与封装基板固定在一起后的堆叠结构进行塑封及固化。
可选地,所述可弯折基板及封装基板上设置有线路结构,所述可弯折基板及封装基板上的线路结构通过所述焊盘的焊接实现电气连接。
可选地,所述可弯折基板的焊盘位于所述可弯折基板的外围,并且上下位置对齐。
第二方面,本发明提供一种多芯片堆叠封装结构制作方法,所述方法包括:
将一个芯片通过焊球或凸点贴装在封装基板上;
将多个芯片分别通过焊球或凸点贴装在可弯折基板上,所述可弯折基板上设置有焊盘;
将一个贴装有芯片的可弯折基板通过胶固定在所述贴装在封装基板上的芯片上,贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,形成堆叠结构;
将所述可弯折基板弯折,使得所述可弯折基板上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘及所述封装基板的焊盘焊接在一起;
利用塑封料将上述堆叠结构塑封并固化。
可选地,所述可弯折基板及封装基板上设置有线路结构,所述可弯折基板及封装基板上的线路结构通过所述焊盘的焊接实现电气连接。
可选地,所述可弯折基板的焊盘位于所述可弯折基板的外围,并且上下位置对齐。
本发明实施例提供的一种多芯片堆叠封装结构及其制作方法,将待堆叠芯片组装在可弯折基板上,可弯折基板的外围设置连接焊盘,贴装在封装基板上,实现多芯片的堆叠、互连及封装。本发明实施例提供的一种多芯片堆叠封装结构及其制作方法,利用焊料将可弯折基板与封装基板相连,直接完成了芯片之间、芯片与封装基板之间的导通、互连,其工艺简单,具有良好的电学性能;其无需打线,减少了金线用量,从而节约封装成本;并且可以避免多次回流引起的可靠性问题。
附图说明
图1为本发明一实施例一种多芯片堆叠封装结构的结构示意图;
图2为本发明一实施例一种多芯片堆叠封装结构制作方法中制作可弯折基板的结构示意图;
图3为本发明一实施例一种多芯片堆叠封装结构制作方法中在可弯折基板上制作焊球或凸点的结构示意图;
图4为本发明一实施例一种多芯片堆叠封装结构制作方法中在可弯折基板上贴装第一芯片的结构示意图;
图5为本发明一实施例一种多芯片堆叠封装结构制作方法中在可弯折基板外围上下焊盘处刷焊锡膏的结构示意图;
图6为本发明一实施例一种多芯片堆叠封装结构制作方法中在可弯折基板上设置第二芯片的结构示意图,实施过程与第一芯片类似;
图7为本发明一实施例一种多芯片堆叠封装结构制作方法中制作封装基板的结构示意图;
图8为本发明一实施例一种多芯片堆叠封装结构制作方法中在封装基板上植球的结构示意图;
图9为本发明一实施例一种多芯片堆叠封装结构制作方法中在封装基板上贴装第三芯片的结构示意图;
图10为本发明一实施例一种多芯片堆叠封装结构制作方法中将第一芯片与第三芯片固定在一起的结构示意图;
图11为本发明一实施例一种多芯片堆叠封装结构制作方法中将第一芯片、第二芯片及第三芯片固定在一起的结构示意图;
图12为本发明一实施例一种多芯片堆叠封装结构制作方法中将堆叠结构采用塑封料进行塑封固化的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明提供一种多芯片堆叠封装结构,所述堆叠封装结构包括:封装基板、多个芯片及多个可弯折基板,所述多个芯片中的一个芯片通过焊球或凸点贴装在所述封装基板上,剩余芯片分别通过焊球或凸点贴装在一个可弯折基板上,所述贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,从而实现芯片的堆叠结构,所述可弯折基板上设置有上下位置对齐的焊盘,所述可弯折基板弯折后使得其上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘与所述封装基板上的焊盘焊接在一起,从而使得可弯折基板与封装基板固定在一起,并实现所有芯片之间及芯片与封装基板之间的互连。
本发明实施例提供的一种多芯片堆叠封装结构,将待堆叠芯片组装在可弯折基板上,可弯折基板的外围设置上下对应的连接焊盘,贴装在封装基板上,实现多芯片的堆叠、互连及封装。本发明实施例提供的一种多芯片堆叠封装结构及其制作方法,利用焊料将可弯折基板与封装基板相连,直接完成了芯片之间、芯片与封装基板之间的导通、互连,其工艺简单,具有良好的电学性能;其无需打线,减少了金线用量,从而节约封装成本;并且可以避免多次回流引起的可靠性问题。
可选地,还包括塑封料,所述塑封料对所述可弯折基板与封装基板固定在一起后的堆叠结构进行塑封及固化。
可选地,所述可弯折基板及封装基板上设置有线路结构,所述可弯折基板及封装基板上的线路结构通过所述焊盘的焊接实现电气连接。
可选地,所述可弯折基板的焊盘位于所述可弯折基板的外围,并且上下位置对齐。
本发明实施例还提供一种多芯片堆叠封装结构制作方法,所述方法包括:
将一个芯片通过焊球或凸点贴装在封装基板上;
将多个芯片分别通过焊球或凸点贴装在可弯折基板上,所述可弯折基板上设置有焊盘;
将一个贴装有芯片的可弯折基板通过胶固定在所述贴装在封装基板上的芯片上,贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,形成堆叠结构;
将所述可弯折基板弯折,使得所述可弯折基板上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘及所述封装基板的焊盘焊接在一起;
利用塑封料将上述堆叠结构塑封并固化。
本发明实施例提供的一种多芯片堆叠封装结构制作方法,将待堆叠芯片组装在可弯折基板上,可弯折基板的外围设置连接焊盘,贴装在封装基板上,实现多芯片的堆叠、互连及封装。本发明实施例提供的一种多芯片堆叠封装结构及其制作方法,利用焊料将可弯折基板与封装基板相连,直接完成了芯片之间、芯片与封装基板之间的导通、互连,其工艺简单,具有良好的电学性能;其无需打线,减少了金线用量,从而节约封装成本;并且可以避免多次回流引起的可靠性问题。
可选地,所述可弯折基板及封装基板上设置有线路结构,所述可弯折基板及封装基板上的线路结构通过所述焊盘的焊接实现电气连接。
可选地,所述可弯折基板的焊盘位于所述可弯折基板的外围,并且上下位置对齐。
下面以3个芯片的封装结构为例,进行详细说明。如图1所示,本发明实施例提供的一种多芯片堆叠封装结构,包括第一芯片4、第二芯片9、第三芯片13。同时还包括包含线路的可弯折基板1、6和封装基板11,所述第一芯片4和第二芯片9分别通过焊球或凸点贴装在可弯折基板1上及可弯折基板6上,第三芯片13通过焊球或凸点贴装在封装基板11上。可弯折基板1及可弯折基板6的两侧分别设置有焊盘2及焊盘7,焊盘处刷焊锡膏。利用可弯折基板的柔韧性,将可弯折基板1、6弯折后贴装在封装基板11上,此时,可弯折基板上1、6的焊盘对准封装基板11上的焊盘,将可弯折基板1、6上的焊盘2、7与封装基板11上的焊盘(图中未示出)焊接在一起,从而使得第一芯片4和第二芯片9通过焊盘和焊料实现与封装基板11的互连,第三芯片13通过焊球12与封装基板11实现互连,第一芯片4、第二芯片9和第三芯片13通过封装基板11实现电气连接。结合实际需求,进行组装时,多个可弯折基板在连接处可以重叠。如果还有更多芯片,可以贴装在不同的可弯折基板上,再贴装到封装基板上。
下面将本发明实施例提供的一种多芯片堆叠封装结构的制作流程进行详细介绍,以三个芯片的封装为例进行解释说明。
(1)如图2所示,制作可弯折基板1,可弯折基板的外围设有上下对齐的焊盘2。
(2)如图3所示,在可弯折基板1上制作焊球或凸点3。
(3)如图4所示,在可弯折基板1上贴装第一芯片4。
(4)在可弯折基板1的外围焊盘2上刷焊锡膏5,如图5所示。
(5)重复步骤1-4,将第二芯片9贴装在可弯折基板6上,并在可弯折基板6的外围焊盘7上刷焊锡膏10,如图6所示。
(6)制作封装基板11,如图7所示。
(7)在封装基板11上植球12,如图8所示。
(8)在封装基板11上贴装第三芯片13,如图9所示。
(9)将贴装有第一芯片4的可弯折基板1,通过胶14固定在第三芯片13上,并进行弯折,焊盘2与封装基板11对应位置的焊盘对准,如图10所示。
(10)将贴装有第二芯片9的可弯折基板6,通过胶15固定在第一芯片4上,并进行弯折,焊盘7与焊盘2对准,并与封装基板11实现互连,然后进行回流焊,将可弯折基板1和6固定在封装基板上,如图11所示。
(11)利用塑封料16对前述结构进行塑封并固化,得到完整的封装体,如图12所示。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应该以权利要求的保护范围为准。
Claims (7)
1.一种多芯片堆叠封装结构,其特征在于,包括:封装基板、多个芯片及多个可弯折基板,所述多个芯片中的一个芯片通过焊球或凸点贴装在所述封装基板上,剩余芯片分别通过焊球或凸点贴装在一个可弯折基板上,所述贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,从而实现芯片的堆叠结构,所述可弯折基板上设置有上下位置对齐的焊盘,所述可弯折基板弯折后使得其上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘与所述封装基板上的焊盘焊接在一起,从而使得可弯折基板与封装基板固定在一起,并实现所有芯片之间及芯片与封装基板之间的互连。
2.根据权利要求1所述的一种多芯片堆叠封装结构,其特征在于,还包括塑封料,所述塑封料对所述可弯折基板与封装基板固定在一起后的堆叠结构进行塑封及固化。
3.根据权利要求2所述的一种多芯片堆叠封装结构,其特征在于,所述可弯折基板及封装基板上设置有线路结构,所述可弯折基板及封装基板上的线路结构通过所述焊盘的焊接实现电气连接。
4.根据权利要求3所述的一种多芯片堆叠封装结构,其特征在于,所述可弯折基板的焊盘位于所述可弯折基板的外围,并且上下位置对齐。
5.一种多芯片堆叠封装结构制作方法,其特征在于,包括:
将一个芯片通过焊球或凸点贴装在封装基板上;
将多个芯片分别通过焊球或凸点贴装在可弯折基板上,所述可弯折基板上设置有焊盘;
将一个贴装有芯片的可弯折基板通过胶固定在所述贴装在封装基板上的芯片上,贴装有芯片的可弯折基板依次堆叠通过胶固定在其他芯片上,形成堆叠结构;
将所述可弯折基板弯折,使得所述可弯折基板上的焊盘对准封装基板上的焊盘,所述可弯折基板上的焊盘及所述封装基板的焊盘焊接在一起;
利用塑封料将上述堆叠结构塑封并固化。
6.根据权利要求5所述的一种多芯片堆叠封装结构制作方法,其特征在于,所述可弯折基板及封装基板上设置有线路结构,所述可弯折基板及封装基板上的线路结构通过所述焊盘的焊接实现电气连接。
7.根据权利要求6所述的一种多芯片堆叠封装结构制作方法,其特征在于,所述可弯折基板的焊盘位于所述可弯折基板的外围,并且上下位置对齐。
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