CN104576608A - 一种膜塑封pop封装结构及其制备方法 - Google Patents

一种膜塑封pop封装结构及其制备方法 Download PDF

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CN104576608A
CN104576608A CN201410840967.0A CN201410840967A CN104576608A CN 104576608 A CN104576608 A CN 104576608A CN 201410840967 A CN201410840967 A CN 201410840967A CN 104576608 A CN104576608 A CN 104576608A
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soldered ball
packaging body
package body
substrate
base plate
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梁天胜
李涛涛
谌世广
刘卫东
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明公开了一种膜塑封POP封装结构及其制备方法,所述结构包括下封装体和上封装体;下封装体主要由基板、焊盘、基板上表面焊球、芯片、凸点、底部填充胶、塑封体和基板下表面焊球组成;上封装体主要由上封装体基板、上封装体焊盘、上封装体芯片、上封装体凸点、上封装体的底部填充胶、上封装体基板下表面焊球组成;所述上封装体基板下表面焊球与下封装体基板上表面焊球的上部分相互对位焊接。所述制备方法为:通过在下封装体上表面形成与上封装体下表面焊球相对应的焊球,经过特殊的模具塑封(CUF)工艺,最后焊球部分露出塑封体,与上封装体进行互连,实现导通,过程中不需要进行激光开槽和塑封孔填充等过程,从而简化制作工艺,节约成本,减小封装体厚度,提高I/O密度,同时提高了封装效率。

Description

一种膜塑封POP封装结构及其制备方法
技术领域
本发明涉及半导体封装领域,尤其涉及一种膜塑封POP封装结构及其制备方法。
背景技术
POP封装是一种很典型的半导体堆叠封装(Package on Package,简称POP),在逻辑电路及存储器领域,其已被作为业界的首选,主要应用于制造高端便携式设备和智能手机使用的先进移动通信平台。传统的POP 封装结构,其下封装体与上封装体互联窗口的制备,通常是先对下封装结构进行塑封,然后利用激光烧蚀的方法在下封装体(对应上封装体基板下表面焊球位置)上表面开槽,此凹槽与下封装体上表面焊盘位置相同,露出预先存在的焊球或在凹槽内进行锡膏印刷植球,最后用于和上封装体进行焊接互连。
但是,如上所述方法,在现有的POP 的制程过程中,需要在塑封体上开槽以及通过焊料印刷形成互连焊球的方法,制作工艺复杂,良率比较低,且成本较高。
发明内容
本发明针对POP封装结构下封装体的制备给出一种实用、有效的方法。通过先在下封装体上表面形成焊球,然后再焊球表面用凹型模具进行贴膜工艺,进行塑封过程,从而保证了在完成塑封过程后,焊球的上表面露出在塑封体之外,方便与上层封装体互连。避免了塑封体开槽及对槽内进行焊料填充的工艺步骤,本发明具有制作工艺简单,低成本,低封装厚度,高I/O密度,高良率的优点。
一种膜塑封POP封装结构,所述结构包括下封装体和上封装体;
下封装体主要由基板、焊盘、基板上表面焊球、芯片、凸点、底部填充胶、塑封体和基板下表面焊球组成;所述基板通过焊盘、凸点连接有芯片, 底部填充胶填充四者的连接部分;基板通过其下表面的焊盘连接有基板下表面焊球,基板通过其上表面的焊盘连接有基板上表面焊球,塑封体包围有芯片、底部填充胶以及基板上表面焊球的下部分;
上封装体主要由上封装体基板、上封装体焊盘、上封装体芯片、上封装体凸点、上封装体的底部填充胶、上封装体基板下表面焊球组成;所述上封装体基板通过上封装体焊盘、上封装体凸点连接有上封装体芯片,上封装体的底部填充胶填充四者的连接部分;上封装体基板通过其下表面的上封装体焊盘连接有上封装体基板下表面焊球;
所述上封装体基板下表面焊球与下封装体基板上表面焊球的上部分相互对位焊接。
一种膜塑封POP封装结构的制备方法,具体按照如下步骤进行:
 步骤A: 下封装体基板上表面倒装上芯和回流焊,基板与芯片互连形成电流通路;
步骤B: 下封装体基板和芯片用底部填充胶固化保护凸点,防止再次过回流焊导致凸点出现变异;
步骤C:在下封装体基板上表面的焊盘区域制作焊球,形成基板上表面焊球;
步骤D:对下封装体用凹型模具塑封,塑封时,凹型模具下行,模具放置在基板上表面焊球上并包围基板上表面焊球的上部分,阻挡塑封体对基板上表面焊球上部分的包裹,塑封体仅包裹芯片、底部填充胶以及基板上表面焊球的下部分;
所述模具的凹部略大于基板上表面焊球的上部分。
步骤E:在模具离开基板上表面焊球后,基板上表面焊球的上部分即暴露在塑封体之外;
步骤F:在下封装体基板通过其下表面的焊盘制作焊球,形成下封装体基板下表面焊球;
步骤G:上封装体基板通过上封装体焊盘、上封装体凸点连接有上封装体芯片,上封装体的底部填充胶填充四者的连接部分;上封装体基板通过其下表面的上封装体焊盘连接有上封装体基板下表面焊球;
步骤H:上封装体基板下表面焊球与下封装体基板上表面焊球的上部分相互对位焊接,在下封装体上表面完成上封装体贴装。
所述焊球成份为Sn、SnAg、SnCu、SnPb或者SnAgCu焊料。
所述步骤A中下封装体为倒装工艺,也可为键合工艺,也可为倒装与键合混合工艺。
所述步骤B中,其芯片底部还可填充有塑封料(MUF工艺)或其他可用于用以加固焊接的填充物。
附图说明
 图1为下封装体基板与其上的芯片互连示意图;
图1为下封装体基板和倒装芯片之间做底部填充胶示意图;
图2为下封装体基板上表面制作焊球示意图;
图3 用特殊模具塑封的示意图;
图4为塑封和后固化示意图;
图5为下封装体基板下表面制作焊球示意图;
图6为下封装体与上封装体焊接示意图。
图中:1为基板,2为焊盘,3为基板上表面焊球,4为芯片,5为凸点,6为底部填充胶,7为模具,8为塑封体,9为基板下表面焊球,10为上封装体基板,11为上封装体焊盘,12为上封装体芯片,13为上封装体凸点,14为上封装体的底部填充胶,15为上封装体基板下表面焊球。
具体实施方式
下面根据附图来对该发明做进一步的描述。
一种膜塑封POP封装结构,所述结构包括下封装体和上封装体;
下封装体主要由基板1、焊盘2、基板上表面焊球3、芯片4、凸点5、底部填充胶6、塑封体8和基板下表面焊球9组成;所述基板1通过焊盘2、凸点5连接有芯片4, 底部填充胶6填充四者的连接部分;基板1通过其下表面的焊盘2连接有基板下表面焊球9,基板1通过其上表面的焊盘2连接有基板上表面焊球3,塑封体8包围有芯片4、底部填充胶6以及基板上表面焊球3的下部分;
上封装体主要由上封装体基板10、上封装体焊盘11、上封装体芯片12、上封装体凸点13、上封装体的底部填充胶14、上封装体基板下表面焊球15组成;所述上封装体基板10通过上封装体焊盘11、上封装体凸点13连接有上封装体芯片12,上封装体的底部填充胶14填充四者的连接部分;上封装体基板10通过其下表面的上封装体焊盘11连接有上封装体基板下表面焊球15;
所述上封装体基板下表面焊球15与下封装体基板上表面焊球3的上部分相互对位焊接。
一种膜塑封POP封装结构的制备方法,具体按照如下步骤进行:
步骤A:下封装体基板1上表面倒装上芯和回流焊,基板1与芯片4互连形成电流通路,如图1所示;
步骤B:下封装体基板1和芯片4用底部填充胶6固化保护凸点5,防止再次过回流焊导致凸点5出现变异,如图1所示;
步骤C:在下封装体基板1上表面的焊盘2区域制作焊球,形成基板上表面焊球3,如图2所示;
步骤D:对下封装体用凹型模具7塑封,塑封时,凹型模具7下行,模具7放置在基板上表面焊球3上并包围基板上表面焊球3的上部分,阻挡塑封体8对基板上表面焊球3上部分的包裹,塑封体8仅包裹芯片4、底部填充胶6以及基板上表面焊球3的下部分,如图3所示;
所述模具7的凹部略大于基板上表面焊球3的上部分。
步骤E:在模具7离开基板上表面焊球3后,基板上表面焊球3的上部分即暴露在塑封体8之外,如图4所示;
步骤F:在下封装体基板1通过其下表面的焊盘2制作焊球,形成下封装体基板下表面焊球9,如图5所示;
步骤G:上封装体基板10通过上封装体焊盘11、上封装体凸点13连接有上封装体芯片12,上封装体的底部填充胶14填充四者的连接部分;上封装体基板10通过其下表面的上封装体焊盘11连接有上封装体基板下表面焊球15;
步骤H:上封装体基板下表面焊球15与下封装体基板上表面焊球3的上部分相互对位焊接,在下封装体上表面完成上封装体贴装,如图6所示。
所述焊球成份为Sn、SnAg、SnCu、SnPb或者SnAgCu焊料。
所述步骤A中下封装体为倒装工艺,也可为键合工艺,也可为倒装与键合混合工艺。
所述步骤B中,其芯片底部还可填充有塑封料(MUF工艺)或其他可用于用以加固焊接的填充物。

Claims (6)

1.一种膜塑封POP封装结构,其特征在于,所述结构包括下封装体和上封装体;
下封装体主要由基板(1)、焊盘(2)、基板上表面焊球(3)、芯片(4)、凸点(5)、底部填充胶(6)、塑封体(8)和基板下表面焊球(9)组成;所述基板(1)通过焊盘(2)、凸点(5)连接有芯片(4),底部填充胶(6)填充四者的连接部分;基板(1)通过其下表面的焊盘(2)连接有基板下表面焊球(9),基板(1)通过其上表面的焊盘(2)连接有基板上表面焊球(3),塑封体(8)包围有芯片(4)、底部填充胶(6)以及基板上表面焊球(3)的下部分;
上封装体主要由上封装体基板(10)、上封装体焊盘(11)、上封装体芯片(12)、上封装体凸点(13)、上封装体的底部填充胶(14)、上封装体基板下表面焊球(15)组成;所述上封装体基板(10)通过上封装体焊盘(11)、上封装体凸点(13)连接有上封装体芯片(12),上封装体的底部填充胶(14)填充四者的连接部分;上封装体基板(10)通过其下表面的上封装体焊盘(11)连接有上封装体基板下表面焊球(15);
所述上封装体基板下表面焊球(15)与下封装体基板上表面焊球(3)的上部分相互对位焊接。
2.一种膜塑封POP封装结构的制备方法,其特征在于,具体按照如下步骤进行:
步骤A: 下封装体基板(1)上表面倒装上芯和回流焊,基板(1)与芯片(4)互连形成电流通路;
步骤B: 下封装体基板(1)和芯片(4)用底部填充胶(6)固化保护凸点(5),防止再次过回流焊导致凸点(5)出现变异;
步骤C:在下封装体基板(1)上表面的焊盘(2)区域制作焊球,形成基板上表面焊球(3);
步骤D:对下封装体用凹型模具(7)塑封,塑封时,凹型模具(7)下行,模具(7)放置在基板上表面焊球(3)上并包围基板上表面焊球(3)的上部分,阻挡塑封体(8)对基板上表面焊球(3)上部分的包裹,塑封体(8)仅包裹芯片(4)、底部填充胶(6)以及基板上表面焊球(3)的下部分;
步骤E:在模具(7)离开基板上表面焊球(3)后,基板上表面焊球(3)的上部分即暴露在塑封体(8)之外;
步骤F:在下封装体基板(1)通过其下表面的焊盘(2)制作焊球,形成下封装体基板下表面焊球(9);
步骤G:上封装体基板(10)通过上封装体焊盘(11)、上封装体凸点(13)连接有上封装体芯片(12),上封装体的底部填充胶(14)填充四者的连接部分;上封装体基板(10)通过其下表面的上封装体焊盘(11)连接有上封装体基板下表面焊球(15);
步骤H:上封装体基板下表面焊球(15)与下封装体基板上表面焊球(3)的上部分相互对位焊接,在下封装体上表面完成上封装体贴装。
3.根据权利要求2所述的一种膜塑封POP封装结构的制备方法,其特征在于,所述步骤D和步骤E中模具(7)的凹部略大于基板上表面焊球(3)的上部分。
4.根据权利要求2所述的一种膜塑封POP封装结构的制备方法,其特征在于,所述焊球成份为Sn、SnAg、SnCu、SnPb或者SnAgCu焊料。
5.根据权利要求2所述的一种膜塑封POP封装结构的制备方法,其特征在于,所述步骤A中下封装体为倒装工艺,也可为键合工艺,也可为倒装与键合混合工艺。
6.根据权利要求2所述的一种膜塑封POP封装结构的制备方法,其特征在于,所述步骤B中,其芯片底部还可填充有塑封料(MUF工艺)或其他可用于用以加固焊接的填充物。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275225A (zh) * 2017-06-20 2017-10-20 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN107316818A (zh) * 2017-06-20 2017-11-03 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN109712954A (zh) * 2018-12-10 2019-05-03 通富微电子股份有限公司 叠层封装件以及叠层封装方法
CN112820651A (zh) * 2020-12-30 2021-05-18 苏州通富超威半导体有限公司 封装体上功能凸点的设置方法及封装体的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101286484A (zh) * 2007-04-13 2008-10-15 日本电气株式会社 半导体器件和制造方法
CN102222663A (zh) * 2010-04-14 2011-10-19 海力士半导体有限公司 具有柔性导体的堆叠封装
CN104078435A (zh) * 2014-07-15 2014-10-01 南通富士通微电子股份有限公司 Pop封装结构
CN104103536A (zh) * 2014-07-15 2014-10-15 南通富士通微电子股份有限公司 Pop封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101286484A (zh) * 2007-04-13 2008-10-15 日本电气株式会社 半导体器件和制造方法
CN102222663A (zh) * 2010-04-14 2011-10-19 海力士半导体有限公司 具有柔性导体的堆叠封装
CN104078435A (zh) * 2014-07-15 2014-10-01 南通富士通微电子股份有限公司 Pop封装结构
CN104103536A (zh) * 2014-07-15 2014-10-15 南通富士通微电子股份有限公司 Pop封装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275225A (zh) * 2017-06-20 2017-10-20 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN107316818A (zh) * 2017-06-20 2017-11-03 上海图正信息科技股份有限公司 芯片封装模组的制备方法及封装结构
CN109712954A (zh) * 2018-12-10 2019-05-03 通富微电子股份有限公司 叠层封装件以及叠层封装方法
CN112820651A (zh) * 2020-12-30 2021-05-18 苏州通富超威半导体有限公司 封装体上功能凸点的设置方法及封装体的制备方法

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