CN106997875A - 一种PoP堆叠封装结构及其制造方法 - Google Patents
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Abstract
本发明名称:一种PoP堆叠封装结构及其制造方法。所属的技术领域涉及微电子封装技术领域。本发明公开了一种PoP堆叠封装结构及其制造方法。该PoP堆叠封装通过上、下封装堆叠形成,其中下封装为塑封型BGA、CSP封装等表面贴装型封装,上封装为至少具有一个插针的PGA封装等插装型封装。下封装的塑封材料至少具有一个模塑通孔,导电材料填充于模塑通孔中。上封装的插针完全插入下封装模塑通孔中的导电材料中。制造该封装结构的主要方法:在下封装的塑封材料中制作模塑通孔,裸露出下封装基板上的互联接口,在模塑通孔中填充导电材料,将上封装的插针完全插入下封装模塑通孔中的导电材料中,形成PoP堆叠封装。
Description
技术领域
本发明涉及微电子封装技术以及三维集成技术领域,特别涉及一种三维PoP 封装技术及其制造方法。
背景技术
随着电子封装产品向高密度、多功能、低功耗、小型化方向的不断发展,采用三维集成技术的系统级封装(System in Package,SiP)取得了突飞猛进的发展。现有成熟的三维集成技术主要为堆叠封装(Package on Package,PoP)。在PoP封装中,上封装通过焊球作为互联结构实现与下封装,以及外部环境的三维导通。由于上、下封装结构的差异,导致制造工艺过程中封装翘曲难以得到有效控制,严重影响焊球互联结构的可靠性。另外,由于焊球互联结构的存在,PoP封装的高度无法进一步的降低,难以满足小型化的要求。
因此,仍然需要新的封装结构和制造技术,以解决现有技术所存在的问题。
发明内容
本发明针对三维PoP 封装技术提出一种封装结构和制造方法,以解决现有PoP 封装技术所存在的封装密度和成本问题。
为了实现上述目的,本发明采用下述技术方案。
本发明提出一种PoP堆叠封装结构,包括PoP封装的第一封装体(下封装体)和第二封装体(上封装体)。PoP堆叠封装通过上、下封装堆叠形成,其中下封装为塑封型BGA、CSP封装等表面贴装型封装,上封装为至少具有一个插针的PGA封装等插装型封装。下封装的塑封材料至少具有一个模塑通孔,导电材料填充于模塑通孔中。上封装的插针完全插入下封装模塑通孔中的导电材料中。
利用该结构,上封装的插针完全插入下封装模塑通孔中的导电材料中,与下封装基板上的互联接口形成互联,从而实现上封装与下封装体之间,以及与外部环境的互联。由于上、下封装之间无需焊球互联结构存在,而是直接通过插针实现互联,不仅提高了封装的热-机械可靠性,而且还降低了封装的整体高度。
根据本发明的实施例,导电材料可以是但不局限于焊料、铜等金属材料。
根据本发明的实施例,导电材料的上表面低于塑封材料的上表面。
根据本发明的实施例,上封装的插针的高度不大于塑封材料的高度。
本发明公开了一种PoP堆叠封装结构的制造方法,所述方法包括以下步骤。
步骤1:准备塑封型BGA、CSP封装等表面贴装型封装,作为PoP堆叠封装的下封装。
步骤2:在下封装的塑封材料中制作模塑通孔,裸露出下封装基板上的互联接口。
步骤3:在模塑通孔中填充导电材料。
步骤4:准备至少具有一个插针的PGA封装等插装型封装,作为PoP堆叠封装的上封装。
步骤5:将上封装的插针完全插入下封装模塑通孔中的导电材料中,形成PoP堆叠封装。
根据本发明的实施例,模塑通孔采用激光或者机械开孔,或者采用特制塑封模具直接塑封形成。
根据本发明的实施例,导电材料通过电镀或者液态金属填充,或者钎料膏印刷方法制作。
附图说明
图1是PoP堆叠封装的下封装的示意图。
图2是在下封装的塑封材料中制作模塑通孔的示意图。
图3是在模塑通孔中填充导电材料的示意图。
图4是准备PoP堆叠封装的上封装的示意图。
图5是PoP堆叠封装的一实施例的示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面结合附图对本发明的具体实施方式作进一步详细描述。
图5为根据本发明的一实施例绘制的PoP堆叠封装的示意图。PoP堆叠封装通过上、下封装堆叠形成。在本发明中,上、下封装中芯片的数量不限,芯片的配置方式不限,可以为引线键合方式,也可以为倒装上芯方式,或者为两者的混合模式。本实施例中,上、下封装均采用引线键合方式。PoP堆叠封装的下封装包含基板1、芯片2、粘贴材料3、金属导线4、塑封料5和焊球6。PoP堆叠封装的上封装包含基板21、芯片23、粘贴材料22、金属导线24、塑封料25和插针26。导电材料7填充于下封装的塑封料5的模塑通孔中。
下面将以图5所述实施例的PoP堆叠封装结构为例,以图1至图5来详细说明PoP堆叠封装结构的制造流程。
步骤1:准备塑封型BGA、CSP封装等表面贴装型封装,作为PoP堆叠封装的下封装,如图1所示。
请参照图1,准备塑封型BGA、CSP封装等表面贴装型封装,作为PoP堆叠封装的下封装。在本发明中,下封装中芯片的数量不限,芯片的配置方式不限,可以为引线键合方式,也可以为倒装上芯方式,或者为两者的混合模式。本实施例中,下封装均采用引线键合方式。PoP堆叠封装的下封装包含基板1、芯片2、粘贴材料3、金属导线4、塑封料5和焊球6。
步骤2:在下封装的塑封材料中制作模塑通孔,裸露出下封装基板上的互联接口,如图2所示。
请参照图2,在下封装的塑封材料5中制作模塑通孔,裸露出下封装基板上的互联接口。在本实施例中,模塑通孔可以采用激光或者机械开孔,或者采用特制塑封模具直接塑封形成。
步骤3:在模塑通孔中填充导电材料,如图3所示。
请参照图3,在模塑通孔中填充导电材料7。在本发明中,采用电镀或者液态金属填充,或者钎料膏印刷方法制作导电材料7。导电材料7可以是但不局限于焊料、铜等金属材料。导电材料7的上表面低于塑封材料的上表面。
步骤4:准备至少具有一个插针的PGA封装等插装型封装,作为PoP堆叠封装的上封装,如图4所示。
请参照图4,准备至少具有一个插针的PGA封装等插装型封装,作为PoP堆叠封装的上封装。在本发明中,上封装中芯片的数量不限,芯片的配置方式不限,可以为引线键合方式,也可以为倒装上芯方式,或者为两者的混合模式。本实施例中,下封装均采用引线键合方式。PoP堆叠封装的上封装包含基板21、芯片23、粘贴材料22、金属导线24、塑封料25和插针26。
步骤5:将上封装的插针完全插入下封装模塑通孔中的导电材料中,形成PoP堆叠封装,如图5所示。
请参照图5,将上封装的插针26完全插入下封装模塑通孔中的导电材料7中,形成PoP堆叠封装。在本发明中,上封装的插针26的高度不大于下封装的塑封材料5的高度。在本发明中,如果填充的导电材料7为焊料等材料,那么在完全插入插针26后需进行回流焊工艺以形成完整的焊接互联。
对本发明的实施例的描述是出于有效说明和描述本发明的目的,并非用以限定本发明,任何所属本领域的技术人员应当理解:凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (7)
1.一种PoP堆叠封装结构,其特征在于,所述结构包括:
PoP堆叠封装通过上、下封装堆叠形成,其中下封装为塑封型BGA、CSP封装等表面贴装型封装,上封装为至少具有一个插针的PGA封装等插装型封装;下封装的塑封材料至少具有一个模塑通孔,导电材料填充于模塑通孔中;上封装的插针完全插入下封装模塑通孔中的导电材料中。
2.根据权利要求1所述一种PoP堆叠封装结构,其特征在于,导电材料可以是但不局限于焊料、铜等金属材料。
3.根据权利要求1所述一种PoP堆叠封装结构,其特征在于,导电材料的上表面低于塑封材料的上表面。
4.根据权利要求1所述一种PoP堆叠封装结构,其特征在于,上封装的插针的高度不大于塑封材料的高度。
5.一种PoP堆叠封装结构的制造方法,其特征在于,所述方法包括:
步骤1:准备塑封型BGA、CSP封装等表面贴装型封装,作为PoP堆叠封装的下封装;
步骤2:在下封装的塑封材料中制作模塑通孔,裸露出下封装基板上的互联接口;
步骤3:在模塑通孔中填充导电材料;
步骤4:准备至少具有一个插针的PGA封装等插装型封装,作为PoP堆叠封装的上封装;
步骤5:将上封装的插针完全插入下封装模塑通孔中的导电材料中,形成PoP堆叠封装。
6.根据权利要求5所述PoP堆叠封装结构的制造方法,其特征在于,模塑通孔采用激光或者机械开孔,或者采用特制塑封模具直接塑封形成。
7.根据权利要求5所述PoP堆叠封装结构的制造方法,其特征在于,导电材料通过电镀或者液态金属填充,或者钎料膏印刷方法制作。
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CN111106013A (zh) * | 2019-10-31 | 2020-05-05 | 广东芯华微电子技术有限公司 | Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法 |
CN111106013B (zh) * | 2019-10-31 | 2022-03-15 | 广东芯华微电子技术有限公司 | Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法 |
CN112996370A (zh) * | 2021-04-25 | 2021-06-18 | 中国人民解放军海军工程大学 | 一种适用于高盐雾环境的功率电子设备封装结构 |
WO2022227498A1 (zh) * | 2021-04-25 | 2022-11-03 | 中国人民解放军海军工程大学 | 一种适用于高盐雾环境的功率电子设备封装结构 |
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