CN103094236A - 一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺 - Google Patents

一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺 Download PDF

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CN103094236A
CN103094236A CN2012105823129A CN201210582312A CN103094236A CN 103094236 A CN103094236 A CN 103094236A CN 2012105823129 A CN2012105823129 A CN 2012105823129A CN 201210582312 A CN201210582312 A CN 201210582312A CN 103094236 A CN103094236 A CN 103094236A
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substrate
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nickel gold
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刘卫东
谌世广
徐召明
朱文辉
马利
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本发明涉及一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺,封装件主要由基板、镍金焊盘、芯片、锡银凸点底填料和锡球组成;所述镍金焊盘固定连接于基板上,锡银凸点固定连接于芯片上;所述锡银凸点与镍金焊盘的中心线重合并焊接连接;所述底填料填充基板与芯片之间的空隙,并包围镍金焊盘和锡银凸点;所述锡银凸点与镍金焊盘的焊接采用助焊剂焊接。制作工艺按照以下步骤进行:上芯、回流焊;去离子水清洗;下填;固化;晶圆减薄;植球、检验、包装、入库。本发明使封装件尺寸更薄,性能更高,显著提高封装件的可靠性。

Description

一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺
  
技术领域
本发明属于集成电路封装技术领域,具体是一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺。 
背景技术
Flip Chip倒装芯片既是一种芯片互连技术,又是一种理想的芯片粘接技术.早在30年前IBM公司已研发使用了这项技术。但直到近几年来,Flip-Chip才成为高端器件及高密度封装领域中经常采用的封装形式。今天,Flip-Chip封装技术的应用范围日益广泛,封装形式更趋多样化,对Flip-Chip封装技术的要求也随之提高。同时,Flip-Chip也向制造者提出了一系列新的严峻挑战,为这项复杂的技术提供封装,组装及测试的可靠支持。以往的一级封闭技术都是将芯片的有源区面朝上,背对基板和贴后键合,如引线健合和载带自动健全(TAB)。Flip-Chip则将芯片有源区面对基板,通过芯片上呈阵列排列的焊料凸点实现芯片与衬底的互连.硅片直接以倒扣方式安装到基板从硅片向四周引出I/O,互联的长度大大缩短,减小了RC延迟,有效地提高了电性能。显然,这种芯片互连方式能提供更高的I/O密度,倒装占有面积几乎与芯片大小一致。在所有表面安装技术中,倒装芯片可以达到最小、最薄的封装。 但是由于以往传统封装的局限性, 晶圆只能减薄到200μm,特别是减薄到100μm以下的厚度是容易翘曲,封装可靠性得不到保证。 
发明内容
为了克服上述现有技术存在的问题,本发明的目的是提供一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺,使晶圆翘曲得到控制,提高封装可靠性。 
本发明的技术方案是:一种底填料固化后晶圆减薄的单芯片封装件,主要由基板、镍金焊盘、芯片、锡银凸点、底填料和锡球组成;所述镍金焊盘固定连接于基板上,锡银凸点固定连接于芯片上;所述锡银凸点与镍金焊盘的中心线重合并焊接连接;所述底填料填充基板与芯片之间的空隙,并包围镍金焊盘和锡银凸点;所述锡银凸点与镍金焊盘的焊接采用助焊剂焊接。 
一种底填料固化后晶圆减薄的单芯片封装件的制作工艺,其按照以下步骤进行: 
第一步、上芯、回流焊:首先,在基板的镍金焊盘上刷一层35μm--60μm的助焊剂;其次,使锡银凸点与镍金焊盘的中心线重合并通过助焊剂黏结接触;再次,在255±5℃的回流温度下,镍金焊盘与锡银凸点有效形成焊接结,即形成金属间化合物;最后,芯片被牢固地焊接在基板上;
第二步、去等离子水清洗:用10MΩ·CM左右的去离子水清洗残留在锡银凸点上的助焊剂和其他杂质;
第三步、下填:首先,对基板进行125℃/150min的烘烤,去除基板与芯片上的水汽;其次,将产品用等离子气体清洗;再次,使用底填料填充芯片与基板的空隙;
第四步、固化采用传统工艺:采用清洁的烘箱,在温度150℃,持续时间2小时对下填的产品进行固化;
第五步、晶圆减薄:用金刚石研磨轮先进行粗磨,然后精磨,最终晶圆厚度减薄至100μm以下;
第六步、植球、检验、包装、入库均同传统工艺。
本发明固化后再进行减薄的工序,保证了晶圆减薄至100μm以下,并且极大得降低了晶圆翘曲的可能性,使封装件尺寸更薄,性能更高,显著提高封装件的可靠性。 
说明书附图
图1为基板剖面图;
图2为基板刷助焊剂产品剖面图;
图3为上芯、回流焊后产品剖面图;
图4为下填后产品剖面图;
图5为芯片粗磨后产品剖面图;
图6为精磨后产品剖面图;
图7为植球后产品成品剖面图。
图中,1为基板、2为镍金焊盘、3为助焊剂、4为芯片、5为锡银凸点、6为底填料、7为粗磨部分、8为精磨部分、9为锡球。 
具体实施方式
下面结合附图对本发明做进一步的说明。 
如图所示,一种底填料固化后晶圆减薄的单芯片封装件,主要由基板1、镍金焊盘2、芯片4、锡银凸点5、底填料6和锡球9组成;所述镍金焊盘2固定连接于基板1上,锡银凸点5固定连接于芯片4上;所述锡银凸点5与镍金焊盘2的中心线重合并焊接连接;所述底填料6填充基板1与芯片4之间的空隙,并包围镍金焊盘2和锡银凸点5;所述锡银凸点5与镍金焊盘2的焊接采用助焊剂3焊接。 
芯片4通过锡银凸点5、镍金焊盘2、基板1和锡球9构成了电路电源和信号的通道。 
如图所示,一种底填料固化后晶圆减薄的单芯片封装件的制作工艺,其按照以下步骤进行: 
第一步、上芯、回流焊:首先,在基板1的镍金焊盘2上刷一层35μm--60μm的助焊剂3,如图2所示;其次,使芯片4的锡银凸点5与基板1的镍金焊盘2的中心线重合并接触,因为助焊剂3的黏性,镍金焊盘2和锡银凸点5牢固接触而不易偏移;再次,在255±5℃的回流温度下,镍金焊盘2与锡银凸点5有效形成焊接结,即形成金属间化合物,助焊剂3在焊接时可去除镍金焊盘2与锡银凸点5表面的氧化物,并具有催化焊接作用;最后,芯片4被牢固地焊接在基板1上。如图3所示。
第二步、等离子清洗:用10MΩ·CM左右的去离子水清洗残留在锡银凸点5上的助焊剂3和其他杂质。因为助焊剂3在回流后的残留会降低底填料6的流动性,使底填料6的填充性变差。 
第三步、下填:首先,对基板1进行125℃/150min的烘烤,去除基板1与芯片4上的水汽,避免在下填与后固化过程中底填料6产生气泡;其次,将产品用等离子气体清洗,原理是惰性气体在高压电场中电离成离子并高速冲击基板表面,去除一些灰尘或者颗粒,使得底填料6在基板1与芯片4之间的流动性更好;再次,使用底填料6填充芯片4与基板1的空隙,底填料6通过毛细管作用从芯片4的一边流到芯片4另一边。这里,可根据芯片4的形状、芯片4厚度、芯片4与基板1的空隙大小及锡银凸点5的排布选择合适的底填料6和适当的工艺条件(胶水温度,基板预热温度、点胶模式等),以防止气泡的产生。下填后的剖面图如4所示。 
第四步、固化采用传统工艺:采用清洁的烘箱,温度保持150℃,持续时间2小时对下填的产品进行固化。底填料6在高温时发生交联反应,使胶体的强度、耐热性和耐磨性大大提高,能有效保护封装件。 
第五步、晶圆减薄:用金刚石研磨轮先进行粗磨,然后精磨,最终晶圆厚度减薄至100μm以下。如图5和如图6所示粗磨部分7和精磨部分8。 
第六步、植球、检验、包装、入库均同传统工艺。如图7所示。 
该底填料固化后的单芯片封装件晶圆减薄技术优点是:1)易于晶圆安全传递与运输;2)晶圆划片前不需要背面减薄;3)易于晶圆切割,减少了切割时的崩边与裂片;4)在FLIP CHIP封装过程的芯片裂片可能性大大降低;5)晶圆背面减薄,有利用芯片工作时的散热,从而提高了产品的寿命;6)晶圆在切割和封装过程中有一定厚度,大大降低芯片封装时的Crack风险,进而提升了产品封装优良率。 
  

Claims (2)

1.一种底填料固化后晶圆减薄的单芯片封装件,其特征在于:主要由基板(1)、镍金焊盘(2)、芯片(4)、锡银凸点(5)、底填料(6)和锡球(9)组成;所述镍金焊盘(2)固定连接于基板(1)上,锡银凸点(5)固定连接于芯片(4)上;所述锡银凸点(5)与镍金焊盘(2)的中心线重合并焊接连接;所述底填料(6)填充基板(1)与芯片(4)之间的空隙,并包围镍金焊盘(2)和锡银凸点(5);所述锡银凸点(5)与镍金焊盘(2)的焊接采用助焊剂(3)焊接。
2.一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺,其特征在于:其按照以下步骤进行:
第一步、上芯、回流焊:首先,在基板(1)的镍金焊盘(2)上刷一层35μm--60μm的助焊剂(3);其次,使锡银凸点(5)与镍金焊盘(2)的中心线重合并通过助焊剂(3)黏结接触;再次,在255±5℃的回流温度下,镍金焊盘(2)与锡银凸点(5)有效形成焊接结,即形成金属间化合物;最后,芯片(4)被牢固地焊接在基板(1)上;
第二步、去离子水清洗:用10MΩ·CM左右的去离子水清洗残留在锡银凸点(5)上的助焊剂(3)和其他杂质;
第三步、下填:首先,对基板(1)进行125℃/150min的烘烤,去除基板(1)与芯片(4)上的水汽;其次,将产品用等离子气体清洗;再次,使用底填料(6)填充芯片(4)与基板(1)的空隙;
第四步、固化:采用清洁的烘箱,在温度150℃,持续时间2小时对下填的产品进行固化;
第五步、晶圆减薄:用金刚石研磨轮先进行粗磨,然后精磨,最终晶圆厚度减薄至100μm以下;
第六步、植球、检验、包装、入库。
CN2012105823129A 2012-12-28 2012-12-28 一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺 Pending CN103094236A (zh)

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Cited By (4)

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CN103928441A (zh) * 2014-03-31 2014-07-16 华天科技(西安)有限公司 一种基于胶膜的fcbga单芯片封装件及其制作工艺
CN103928434A (zh) * 2014-03-31 2014-07-16 华天科技(西安)有限公司 一种基于Flux的FCBGA单芯片封装件及其制作工艺
CN107431107A (zh) * 2015-04-01 2017-12-01 歌尔股份有限公司 微发光二极管的转移方法、制造方法、装置和电子设备
CN117650061A (zh) * 2023-10-27 2024-03-05 南京屹立芯创半导体科技有限公司 一种芯片加工方法

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