CN103021988A - 一种以胶膜替代底填料的单芯片封装件及其制作工艺 - Google Patents

一种以胶膜替代底填料的单芯片封装件及其制作工艺 Download PDF

Info

Publication number
CN103021988A
CN103021988A CN2012105342237A CN201210534223A CN103021988A CN 103021988 A CN103021988 A CN 103021988A CN 2012105342237 A CN2012105342237 A CN 2012105342237A CN 201210534223 A CN201210534223 A CN 201210534223A CN 103021988 A CN103021988 A CN 103021988A
Authority
CN
China
Prior art keywords
chip
substrate
glued membrane
salient point
nickel gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012105342237A
Other languages
English (en)
Inventor
郭小伟
刘建军
谌世广
崔梦
刘卫东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Xian Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN2012105342237A priority Critical patent/CN103021988A/zh
Publication of CN103021988A publication Critical patent/CN103021988A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

本发明公开了一种以胶膜替代底填料的单芯片封装件及其制作工艺，该封装件主要由基板、镍金焊盘、芯片、锡银凸点、胶膜和锡球组成；所述镍金焊盘固定连接于基板上，锡银凸点固定连接于芯片上；所述锡银凸点与镍金焊盘的中心线重合并焊接连接；所述胶膜填充基板与芯片之间的空隙，并包围镍金焊盘和锡银凸点。制作工艺按照以下步骤进行：贴胶膜；上芯、回流焊；晶圆背面减薄；植球、检验、包装、入库。该技术降低了封装成本，提高了封装可靠性，减少了工艺环节。

Description

一种以胶膜替代底填料的单芯片封装件及其制作工艺
 
技术领域
    本发明属于集成电路封装技术领域，具体是一种以胶膜替代底填料的单芯片封装件及其制作工艺。
背景技术
Flip Chip倒装技术既是一种芯片互连技术，又是一种理想的芯片粘接技术．早在30年前IBM公司已研发使用了这项技术。但直到近几年来，Flip-Chip已成为高端器件及高密度封装领域中经常采用的封装形式。今天，Flip-Chip封装技术的应用范围日益广泛，封装形式更趋多样化，对Flip-Chip封装技术的要求也随之提高。同时，Flip-Chip也向制造者提出了一系列新的严峻挑战，为这项复杂的技术提供封装，组装及测试的可靠支持。以往的一级封闭技术都是将芯片的有源区面朝上，背对基板和贴片后键合，如引线健合和载带自动健全（ＴＡＢ）。ＦＣ则将芯片有源区面对基板，通过芯片上呈阵列排列的焊料凸点实现芯片与衬底的互连．硅片直接以倒扣方式安装到基板从硅片向四周引出Ｉ／Ｏ，互联的长度大大缩短，减小了ＲＣ延迟，有效地提高了电性能．显然，这种芯片互连方式能提供更高的Ｉ／Ｏ密度．倒装占有面积几乎与芯片大小一致．在所有表面安装技术中，倒装芯片可以达到最小、最薄的封装。 但是由于以往传统封装的局限性， 晶圆只能减薄到200μm，特别是减薄到100μm以下的厚度是容易翘曲，封装可靠性得不到保证。
发明内容
为了克服上述现有技术存在的问题，本发明的目的是提供一种以胶膜替代底填料的单芯片封装件及其制作工艺，该技术使晶圆翘曲得到控制，并使用新型胶膜，替代底填料，降低封装成本，提高封装可靠性。
本发明的技术方案是：一种以胶膜替代底填料的单芯片封装件，主要由基板、镍金焊盘、芯片、锡银凸点、胶膜和锡球组成；所述镍金焊盘固定连接于基板上，锡银凸点固定连接于芯片上；所述锡银凸点与镍金焊盘的中心线重合并焊接连接；所述胶膜填充基板与芯片之间的空隙，并包围镍金焊盘和锡银凸点。
芯片通过锡银凸点、镍金焊盘、基板和锡球构成了电路电源和信号的通道。
一种以胶膜替代底填料的单芯片封装件的制作工艺，其按照如下步骤进行：
第一步、贴胶膜：首先，在整个晶圆表面均匀地旋转涂布一层化学胶膜，厚度150μm，使化学胶膜完全覆盖锡银凸点；其次，将晶圆放在加热平台上加热，温度在80--100摄氏度，使胶膜一次固化；最后，用金刚石刀片或者激光将晶圆切割成单个芯片；
第二步、上芯、回流焊：首先，芯片被精确地定位于基板上，使芯片的锡银凸点与基板的镍金焊盘的中心线重合并接触；其次，设置回流焊炉各温区的温度为255±5℃，锡银凸点与镍金焊盘先有效形成焊接结，即金属间化合物；同时，胶膜受热熔化填充芯片与基板之间的空隙并二次固化，保护封装件。基板镍金焊盘上无需刷助焊剂，芯片上的锡银凸点与基板的镍金焊盘在回流焊接后没有助焊剂残留，胶膜受热溶化填充时可以避免空洞的产生；
第三步、晶圆背面减薄；用金刚石研磨轮先进行粗磨，然后精磨，最终减薄厚度减薄至100μm以下；
第四步、植球、检验、包装、入库均同传统工艺。
本发明采用在封装件貼膜后固化后再进行减薄工序，保证了晶圆减薄至100μm以下，并且极大的降低了晶圆翘曲的可能性；胶膜取代了底填料，降低封装成本，提高了封装的可靠性，更好的保护锡球；因为不采用助焊剂，去除了等离子清洗的工序，减少了工艺环节。
说明书附图
　 图1为基板剖面图；
　 图2为芯片剖面图；
　 图3为芯片贴膜后剖面图；
　 图4为上芯、后固化后产品剖面图；
　 图5为芯片粗磨后产品剖面图；
　 图6为精磨后产品剖面图；
　 图7为植球后产品成品剖面图。
　 图中，1为基板、2为镍金焊盘、3为芯片、4为锡银凸点、5为胶膜、6为粗磨部分、7为精磨部分、8为锡球。
具体实施方式
如图所示，一种以胶膜替代底填料的单芯片封装件，主要由基板1、镍金焊盘2、芯片3、锡银凸点4、胶膜5和锡球8组成；所述镍金焊盘2固定连接于基板1上，锡银凸点4固定连接于芯片3上；所述锡银凸点4与镍金焊盘2的中心线重合并焊接连接；所述胶膜5填充基板1与芯片3之间的空隙，并包围镍金焊盘2和锡银凸点4。
芯片3通过锡银凸点4、镍金焊盘2、基板1和锡球8构成了电路电源和信号的通道。
如图所示，一种以胶膜替代底填料的单芯片封装件的制作工艺，其按照如下步骤进行：
第一步、贴胶膜5：首先，在整个晶圆表面均匀地旋转涂布一层化学胶膜5，厚度150μm，使化学胶膜5完全覆盖锡银凸点4；其次，将晶圆放在加热平台上加热，温度在80—100摄氏度，使胶膜5一次固化；最后，用金刚石刀片或者激光将晶圆切割成单个芯片3。芯片3贴膜后剖面图如图3所示。
　 第二步、上芯、回流焊：首先，芯片3被精确地定位在基板1上，使芯片3的锡银凸点4与基板1的镍金焊盘2的中心线重合并接触；其次，设置回流焊炉各温区的温度为255±5℃，锡银凸点4与镍金焊盘2先有效形成焊接结，即金属间化合物；同时，胶膜5受热熔化填充芯片3与基板1之间的空隙并二次固化，保护封装件。基板镍金焊盘2上无需刷助焊剂，芯片3上的锡银凸点4与基板1的镍金焊盘2在回流焊接后没有助焊剂残留，胶膜5受热溶化填充时可以避免空洞的产生。上芯、后固化后产品剖面图如4所示。
　 第三步、晶圆背面减薄；用金刚石研磨轮先进行粗磨，然后精磨，最终减薄厚度减薄至100μm以下，如图5和如图6所示的粗磨部分6和精磨部分7。
　 第四步、植球、检验、包装、入库均同传统工艺。植球后产品如图7。
　 以胶膜替代底填料的单芯片封装件芯片背面减薄技术优点是：1）易于晶圆安全传递与运输；2）晶圆划片前不需要背面减薄；3）易于晶圆切割，减少了切割时的崩边与裂片；4）在flip chip封装过程的芯片裂片可能性大大降底；5）晶圆背面减薄，有利用芯片工作时的散热，从而提高了产品的寿命；6）晶圆在切割和封装过程中有一定厚度，大大降底芯片封装时的crack风险，进而提升了产品封装良率。

Claims (2)

1.一种以胶膜替代底填料的单芯片封装件，其特征在于：主要由基板（1）、镍金焊盘（2）、芯片（3）、锡银凸点（4）、胶膜（5）和锡球（8）组成；所述镍金焊盘（2）固定连接于基板（1）上，锡银凸点(4）固定连接于芯片（3）上；所述锡银凸点（4）与镍金焊盘（2）的中心线重合并焊接连接；所述胶膜（5）填充基板（1）与芯片（3）之间的空隙，并包围镍金焊盘（2）和锡银凸点（4）。
2.一种以胶膜替代底填料的单芯片封装件的制作工艺，其特征在于：其按照如下步骤进行：
第一步、贴胶膜（5）：首先，在整个晶圆表面均匀地旋转涂布一层化学胶膜（5），厚度150μm，使胶膜（5）完全覆盖锡银凸点（4）；其次，将晶圆放在加热平台上加热，温度在80--100℃，使胶膜（5）一次固化；最后，用金刚石刀片或者激光将晶圆切割成单个芯片（3）；
第二步、上芯、回流焊：首先，芯片（3）被精确地定位在基板（1）上，使芯片（3）的锡银凸点（4）与基板（1）的镍金焊盘（2）的中心线重合并接触；其次，设置回流焊炉各温区的温度为255±5℃，锡银凸点（4）与镍金焊盘（2）先有效形成焊接结，即金属间化合物；同时，胶膜（5）受热熔化填充芯片（3）与基板（1）之间的空隙并二次固化；
第三步、晶圆背面减薄；用金刚石研磨轮先进行粗磨，然后精磨，最终减薄厚度减薄至100μm以下；
第四步、植球、检验、包装、入库均同传统工艺。
CN2012105342237A 2012-12-12 2012-12-12 一种以胶膜替代底填料的单芯片封装件及其制作工艺 Pending CN103021988A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012105342237A CN103021988A (zh) 2012-12-12 2012-12-12 一种以胶膜替代底填料的单芯片封装件及其制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012105342237A CN103021988A (zh) 2012-12-12 2012-12-12 一种以胶膜替代底填料的单芯片封装件及其制作工艺

Publications (1)

Publication Number Publication Date
CN103021988A true CN103021988A (zh) 2013-04-03

Family

ID=47970420

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012105342237A Pending CN103021988A (zh) 2012-12-12 2012-12-12 一种以胶膜替代底填料的单芯片封装件及其制作工艺

Country Status (1)

Country Link
CN (1) CN103021988A (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105478995A (zh) * 2015-09-14 2016-04-13 深圳光韵达光电科技股份有限公司 一种激光加工键盘触点的方法
CN107240555A (zh) * 2017-05-31 2017-10-10 江苏长电科技股份有限公司 一种倒装芯片和球焊芯片堆叠的封装结构的制造方法
KR20180058825A (ko) * 2015-10-10 2018-06-01 센젠 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 어레이 기판 및 그 제조 방법
CN110828327A (zh) * 2018-08-13 2020-02-21 鹏鼎控股(深圳)股份有限公司 组件的电性连接方法和设备
CN111315118A (zh) * 2020-04-02 2020-06-19 江西兆信精密电子有限公司 一种电竞笔电键盘电路板及其制备方法
CN116741648A (zh) * 2023-08-11 2023-09-12 四川遂宁市利普芯微电子有限公司 一种倒装芯片封装方法及倒装芯片封装结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063515A (ja) * 2002-07-25 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US20060003550A1 (en) * 2004-07-01 2006-01-05 Agency For Science, Technology And Research Method for ultra thinning bumped wafers for flip chip
CN101853791A (zh) * 2009-04-03 2010-10-06 南茂科技股份有限公司 倒装芯片封装的制造方法、其结构及晶片涂布的结构
CN203103274U (zh) * 2012-12-12 2013-07-31 华天科技（西安）有限公司 一种以胶膜替代底填料的单芯片封装件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063515A (ja) * 2002-07-25 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US20060003550A1 (en) * 2004-07-01 2006-01-05 Agency For Science, Technology And Research Method for ultra thinning bumped wafers for flip chip
CN101853791A (zh) * 2009-04-03 2010-10-06 南茂科技股份有限公司 倒装芯片封装的制造方法、其结构及晶片涂布的结构
CN203103274U (zh) * 2012-12-12 2013-07-31 华天科技（西安）有限公司 一种以胶膜替代底填料的单芯片封装件

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105478995A (zh) * 2015-09-14 2016-04-13 深圳光韵达光电科技股份有限公司 一种激光加工键盘触点的方法
KR20180058825A (ko) * 2015-10-10 2018-06-01 센젠 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 어레이 기판 및 그 제조 방법
KR102097226B1 (ko) 2015-10-10 2020-04-03 센젠 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 어레이 기판 및 그 제조 방법
CN107240555A (zh) * 2017-05-31 2017-10-10 江苏长电科技股份有限公司 一种倒装芯片和球焊芯片堆叠的封装结构的制造方法
CN107240555B (zh) * 2017-05-31 2020-04-07 江苏长电科技股份有限公司 一种倒装芯片和球焊芯片堆叠的封装结构的制造方法
CN110828327A (zh) * 2018-08-13 2020-02-21 鹏鼎控股(深圳)股份有限公司 组件的电性连接方法和设备
CN111315118A (zh) * 2020-04-02 2020-06-19 江西兆信精密电子有限公司 一种电竞笔电键盘电路板及其制备方法
CN116741648A (zh) * 2023-08-11 2023-09-12 四川遂宁市利普芯微电子有限公司 一种倒装芯片封装方法及倒装芯片封装结构
CN116741648B (zh) * 2023-08-11 2023-11-17 四川遂宁市利普芯微电子有限公司 一种倒装芯片封装方法及倒装芯片封装结构

Similar Documents

Publication Publication Date Title
CN103021988A (zh) 一种以胶膜替代底填料的单芯片封装件及其制作工艺
TWI379367B (en) Chip packaging method and structure thereof
US8492890B2 (en) Semiconductor device and method for manufacturing thereof
CN103022021B (zh) 半导体装置及其制造方法
CN101221946B (zh) 半导体封装、及系统级封装模块的制造方法
TW201517185A (zh) 用於製造半導體封裝之方法以及使用其製造的半導體封裝
CN203055899U (zh) 一种带有铜柱的晶圆减薄的单芯片封装件
CN102231372B (zh) 多圈排列无载体ic芯片封装件及其生产方法
US10872845B2 (en) Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package
CN203103274U (zh) 一种以胶膜替代底填料的单芯片封装件
CN103050465A (zh) 一种带有铜柱的晶圆减薄的单芯片封装件及其制作工艺
CN108233890A (zh) Fbar滤波器封装结构及封装方法
CN102194707B (zh) 制造半导体结构的方法
CN103094236A (zh) 一种底填料固化后晶圆减薄的单芯片封装件及其制作工艺
US20110298124A1 (en) Semiconductor Structure
CN208796987U (zh) 一种引线框架及其超薄型小外形倒装封装件
CN102651323B (zh) 半导体封装结构的制法
CN102231376A (zh) 多圈排列无载体双ic芯片封装件及其生产方法
CN203103281U (zh) 一种底填料固化后晶圆减薄的单芯片封装件
US6838311B2 (en) Flip chip package and method for forming the same
US8058109B2 (en) Method for manufacturing a semiconductor structure
CN203339142U (zh) 一种底填料填充的fcqfn封装件
CN203839371U (zh) 一种dram双芯片堆叠封装结构
CN103325693A (zh) 一种采用塑封技术优化fcbga封装的封装件及其制作工艺
CN202196776U (zh) 一种扁平无载体无引线引脚外露封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130403