CN103094239B - 一种引线框架增加辅助贴膜引脚的封装件及其制作工艺 - Google Patents

一种引线框架增加辅助贴膜引脚的封装件及其制作工艺 Download PDF

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CN103094239B
CN103094239B CN201210542014.7A CN201210542014A CN103094239B CN 103094239 B CN103094239 B CN 103094239B CN 201210542014 A CN201210542014 A CN 201210542014A CN 103094239 B CN103094239 B CN 103094239B
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马利
王希有
李涛涛
王虎
谌世广
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Huatian Technology Xian Co Ltd
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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Abstract

本发明公开了一种引线框架增加辅助贴膜引脚的封装件及其制作工艺，所述封装件主要由引线框架、芯片、粘片胶、键合丝、塑封体和、锡球、胶膜、切割线、辅助贴膜引脚组成；所述引线框架为蚀刻处理，在其切割道以外有两圈半辅助贴膜引脚，所述引线框架由粘片胶与芯片粘接，所述键合丝连接芯片上的焊点与蚀刻框架上的引脚，所述封装件由塑封体和包封，所述锡球与背面蚀刻的引线框架露出的引脚相连，所述胶膜粘附在锡球上，胶膜覆盖所有锡球区域和辅助贴膜引脚。所述制作工艺按照以下步骤进行：框架半蚀刻、上芯、压焊、一次塑封、框架背面蚀刻、植球和锡膏回流、贴膜和二次塑封、揭膜、切割和分离。本发明因为增加了辅助贴膜引脚减少了废品率，优化了二次塑封质量，改善了产品性能，节约了成本。

Description

一种引线框架增加辅助贴膜引脚的封装件及其制作工艺
技术领域
本发明涉及半导体封装技术领域，具体是一种引线框架增加辅助贴膜引脚的封装件及其制作工艺。
背景技术
随着技术的不断发展，电子封装不但要提供芯片的保护，同时还要在一定的成本下满足不断增加的性能、可靠性、散热、功率分配等要求，这对封装技术提出了新的要求与挑战。激烈的市场竞争推动着封装技术的不断进步，而塑封作为半导体封装技术的关键环节之一，也由一次塑封发展到二次塑封，塑封工序的好坏直接影响着产品的可靠性与成本、性能等问题。
目前，在进行二次塑封时根据模盒设计，在整条框架背面锡球上贴膜时必须以单个Block为单位，按照普通的框架引脚设计，贴膜后的产品进行二次塑封后存在以下问题：（1）二次塑封出现包封不满问题。对普通框架上的锡球进行贴膜时，若胶膜裁剪过大，则胶膜的覆盖面超过了锡球区域，这样胶膜可能粘附在锡球外围的塑封体上，在二次塑封时，由于胶膜与外围塑封体的粘接可能会阻塞塑封料的流动，而使二次塑封出现包封不满问题；（2）每个Block最外圈产品的外形不合格问题。若胶膜按锡球区域的大小裁剪并贴膜时，二次塑封后对产品切割时，为了保证切割不影响产品性能，切割位置必须与外缘锡球保持一定距离，然而，由于贴膜时胶膜大小与锡球区域一致，
外围锡球与切割线之间的塑封体由于未受到胶膜高度限制，该区域的塑封体高度可能与胶膜内锡球周围的塑封体高度不一致，这样会出现每个Block最外圈产品的外形不合格问题。以每个Block以4×4个封装体为例，普通的半蚀刻框架设计的每个Block二次塑封后将报废12只产品。
发明内容
为了克服上述普通框架引脚设计存在的问题，本发明提供一种引线框架增加辅助贴膜引脚的封装件及其制作工艺，目的是优化当前AAQFN半蚀刻框架设计，在半蚀刻框架的每个Block四周增加两圈引脚来辅助背面贴膜，确保二次塑封的质量。
本发明的技术方案是：一种引线框架增加辅助贴膜引脚的封装件主要由引线框架、芯片、粘片胶、键合丝、塑封体、锡球、胶膜、切割线、辅助贴膜引脚组成；所述引线框架为蚀刻处理，在其切割道以外有两圈半辅助贴膜引脚，所述引线框架由粘片胶与芯片粘接，所述键合丝连接芯片上的焊点与蚀刻框架上的引脚，所述封装件由塑封体和包封，所述锡球与背面蚀刻的引线框架露出的引脚相连，所述胶膜粘附在锡球上，胶膜覆盖所有锡球区域和辅助贴膜引脚。
一种引线框架增加辅助贴膜引脚的封装件的制作工艺按照以下步骤进行：框架半蚀刻、上芯、压焊、一次塑封、框架背面蚀刻、植球和锡膏回流、贴膜和二次塑封、揭膜、切割和分离。
本发明的有益效果在于：由于胶膜覆盖了锡球以外的辅助引脚，产品切割位置是在外围锡球与辅助引脚之间，由于外围辅助引脚对胶膜的支撑，从而避免了普通引脚设计包封时出现的胶膜粘附塑封体而引起的包封不满问题，另一方面，也避免了由于产品切割后由于外围塑封体高度不一致而出现的每个Block最外圈产品的外形不合格问题。此外，框架增加辅助贴膜引脚设计也减少了产品报废问题，优化二次塑封质量，改善了产品性能，节约成本。
说明书附图
图1整体产品剖面图；
图2普通的框架引脚设计产品剖面图；
图3引线框架剖面图；
图4上芯后产品剖面图；
图5压焊后产品剖面图；
图6一次塑封后产品剖面图；
图7框架背面蚀刻后产品剖面图；
图8刷锡膏回流焊后产品剖面；
图9二次塑封前贴膜产品剖面图；
图10 二次塑封后产品剖面图；
图11 产品成品剖面图。
图中，1为引线框架、2为芯片、3为粘片胶、 4为键合丝、5和8为塑封体、6为锡球、7为胶膜、9为切割线、10为辅助贴膜引脚。
具体实施方式
下面结合附图对本发明做进一步详细叙述。
如图所示，一种引线框架增加辅助贴膜引脚的封装件主要由引线框架1、芯片2、粘片胶3、键合丝4、塑封体5和8、锡球6、胶膜7、切割线9、辅助贴膜引脚10组成；蚀刻后的引线框架1的切割道以外添加了两圈半辅助贴膜引脚10，在随后的上芯、压焊、一次塑封完成后，引线框架1的被背面蚀刻，塑封体5背面引脚露出，蚀刻后所有引脚与植入的锡球6相连接，胶膜7粘附在锡球6上，胶膜7覆盖所有产品的锡球6区域以及最外圈的框架辅助贴膜引脚10，随后完成产品的切割。由于胶膜7覆盖所有产品的锡球6区域以及最外圈的框架辅助贴膜引脚10，在二次塑封过程中，避免了无辅助贴膜引脚10的普通框架存在的包封不满与最外层产品外形不合格问题，从而优化了二次塑封。
如图所示，一种引线框架增加辅助贴膜引脚的封装件的制作工艺，其按照以下步骤进行：
第一步、框架半蚀刻：将引线框架1进行半蚀刻，通过成熟的涂胶、曝光、显影、电镀及腐蚀等工艺，蚀刻引线框架1，在引线框架1上蚀刻出载体，并在引线框架1的切割道以外蚀刻两圈半辅助贴膜引脚10，在I/O Pad确定I/O Pad大小、脚间距和它们各自的位置；如图3所示；
第二步、上芯：用粘片胶3将芯片2粘接到引线框架1载体上；如图4所示；
第三步、压焊：将芯片2上的焊点与半蚀刻后的引线框架1的引脚用键合丝4连接；
第四步、一次塑封：将压焊后的产品自动传送到塑封模具中，用塑封料5对压焊后的产品进行包封；
第五步、框架背面蚀刻：对引线框架1底部进行蚀刻，蚀刻后的引线框架1如图7所示；
第六步、植球和锡膏回流：对蚀刻后的所有引脚植球6并进行回流；如图8所示；
第七步、贴膜和二次塑封：如图9所示，对锡球6贴一层胶膜7，将贴膜后的产品自动传送到塑封模具中，用塑封料8对贴膜后的产品进行包封；
如图2所示的普通引线框架设计产品剖面图与如图10所示的优化后二次塑封产品剖面图，图10中的引线框架与图2相比,在产品的切割道以外，即在普通引线框架基础上添加了两圈半辅助贴膜引脚10，图10中胶膜7覆盖所有锡球6区域与最外圈的框架辅助贴膜引脚10，这样，由于胶膜覆盖了锡球6以外的辅助贴膜引脚10，产品切割位置是在外围锡球6与辅助贴膜引脚10之间，由于外围辅助贴膜引脚10对胶膜7的支撑，避免了图2中普通引脚设计包封时，由于胶膜过长出现的因胶膜粘附塑封体，阻塞塑封体流动而引起的包封不满问题；另一方面，也避免了普通引脚设计包封时，若胶膜按锡球区域的大小裁剪贴膜，二次塑封后切割时由于胶膜下塑封体与外围未贴膜部分的塑封体高度不一致从而导致的每个Block最外圈产品的外形不合格问题；
第八步、揭膜和切割分离：将锡球6上的胶膜7揭膜，如图10所示；对塑封好的产品切割分离，产品成形剖面图如图11所示。

Claims (2)

1.一种引线框架增加辅助贴膜引脚的封装件，其特征在于：主要由引线框架(1)、芯片(2)、粘片胶(3)、键合丝(4)、塑封体(5)和(8)、锡球(6)、胶膜(7)、切割线(9)、辅助贴膜引脚(10)组成；所述引线框架(1)为蚀刻处理，在其切割道以外有辅助贴膜引脚(10)，所述引线框架(1)由粘片胶(3)与芯片(2)粘接，所述键合丝(4)连接芯片(2)上的焊点与刻蚀的引线框架(1)上的引脚，所述封装件由塑封体(5)和(8)包封，所述锡球(6)与背面蚀刻的引线框架(1)露出的引脚相连，所述胶膜(7)粘附在锡球(6)上，胶膜(7)覆盖所有锡球(6)区域和辅助贴膜引脚(10)。
2.一种引线框架增加辅助贴膜引脚的封装件的制作工艺，其特征在于：其按照以下步骤进行：
第一步、框架半蚀刻：将引线框架(1)进行半蚀刻，通过成熟的涂胶、曝光、显影、电镀及腐蚀工艺，蚀刻引线框架(1)，在引线框架(1)上蚀刻出载体，并在引线框架(1)的切割道以外蚀刻辅助贴膜引脚(10)，在I/O Pad确定I/O Pad大小、脚间距和它们各自的位置；
第二步、上芯：用粘片胶(3)将芯片(2)粘接到引线框架(1)载体上；
第三步、压焊：将芯片(2)上的焊点与半蚀刻后的引线框架(1)的引脚用键合丝(4)连接；
第四步、一次塑封：将压焊后的产品自动传送到塑封模具中，用塑封料
(5)对压焊后的产品进行包封；
第五步、框架背面蚀刻：对引线框架(1)底部进行蚀刻；
第六步、植球和锡膏回流：对蚀刻后的所有引脚植球(6)并进行回流；
第七步、贴膜和二次塑封：对锡球(6)贴一层胶膜(7)，将贴膜后的产品自动传送到塑封模具中，用塑封料(8)对贴膜后的产品进行包封；
第八步、揭膜和切割分离：将锡球(6)上的胶膜(7)揭膜；对塑封好的产品切割分离。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005432A (zh) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 四面无引脚封装结构及其封装方法
CN202394910U (zh) * 2011-11-25 2012-08-22 江苏长电科技股份有限公司 无基岛芯片倒装球栅阵列封装结构
CN203055902U (zh) * 2012-12-14 2013-07-10 华天科技（西安）有限公司 一种引线框架增加辅助贴膜引脚的封装件

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KR100564623B1 (ko) * 2004-05-06 2006-03-30 삼성전자주식회사 크랙을 예방하는 반도체 패키지 및 그 제조방법
TWI311352B (en) * 2006-03-24 2009-06-21 Chipmos Technologies Inc Fabricating process of leadframe-based bga packages and leadless leadframe utilized in the process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005432A (zh) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 四面无引脚封装结构及其封装方法
CN202394910U (zh) * 2011-11-25 2012-08-22 江苏长电科技股份有限公司 无基岛芯片倒装球栅阵列封装结构
CN203055902U (zh) * 2012-12-14 2013-07-10 华天科技（西安）有限公司 一种引线框架增加辅助贴膜引脚的封装件

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