CN109065518A - 一种半导体芯片封装阵列 - Google Patents

一种半导体芯片封装阵列 Download PDF

Info

Publication number
CN109065518A
CN109065518A CN201810608530.2A CN201810608530A CN109065518A CN 109065518 A CN109065518 A CN 109065518A CN 201810608530 A CN201810608530 A CN 201810608530A CN 109065518 A CN109065518 A CN 109065518A
Authority
CN
China
Prior art keywords
groove
load bearing
bearing unit
pin
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810608530.2A
Other languages
English (en)
Other versions
CN109065518B (zh
Inventor
石磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Tongfu Microelectronics Co Ltd
Original Assignee
Nantong Tongfu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Tongfu Microelectronics Co Ltd filed Critical Nantong Tongfu Microelectronics Co Ltd
Priority to CN201810608530.2A priority Critical patent/CN109065518B/zh
Publication of CN109065518A publication Critical patent/CN109065518A/zh
Priority to US16/440,773 priority patent/US10937745B2/en
Application granted granted Critical
Publication of CN109065518B publication Critical patent/CN109065518B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/45111—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/4516—Iron (Fe) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45171—Chromium (Cr) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8146—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85418—Zinc (Zn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85471—Chromium (Cr) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请公开了一种半导体芯片封装阵列，包括：引线框架，引线框架包括：多个矩阵排列的承载单元、自引线框架的第一表面向第二表面延伸的第一凹槽、自第二表面向第一表面延伸的第二凹槽、自第二表面向第一表面延伸的第三凹槽，其中，第一凹槽与第二凹槽相通以形成通孔，第三凹槽连接相邻的承载单元；芯片，芯片设置在承载单元上，且与承载单元电性连接；塑封层，塑封料将芯片和至少部分承载单元包裹，第一凹槽被塑封料填充，以构成塑封层；电镀层，电镀层设置在引线框架的第二表面，且延伸入第三凹槽、或第三凹槽和第二凹槽。通过上述方式，本申请能够增加半导体封装阵列的引脚供焊锡攀爬的面积。

Description

一种半导体芯片封装阵列
技术领域
本申请涉及半导体芯片技术领域，特别是涉及一种半导体芯片封装阵列。
背景技术
随着科学技术地快速发展，半导体芯片封装器件的研发、生产不断向着高密度、高性能、高可靠性和低成本的方向发展。这带来的结果是半导体芯片封装器件的体积不断减小，设置在半导体芯片封装器件上的引脚数量大大增加，引脚之间的距离越来越小，引脚的密度越来越大。
本申请的发明人在长期研究过程中发现，在对现有的半导体芯片封装器件(例如，四边扁平无引脚封装器件、方形扁平无引脚封装器件等)进行焊接的过程中，经常出现焊接性能不佳的情况，这是因为现有的半导体封装器件的引脚仅有底部很小的区域可供焊锡攀爬。
发明内容
本申请主要解决的技术问题是提供一种半导体芯片封装阵列，能够增加半导体封装器件的引脚供焊锡攀爬的面积。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种半导体芯片封装阵列，其中，所述半导体芯片封装阵列包括：
引线框架，所述引线框架包括：多个矩阵排列的承载单元、自引线框架的第一表面向第二表面延伸的第一凹槽、自所述第二表面向第一表面延伸的第二凹槽、自所述第二表面向第一表面延伸的第三凹槽，其中，所述第一凹槽与所述第二凹槽相通以形成通孔，所述第三凹槽连接相邻的承载单元；
芯片，所述芯片设置在所述承载单元上，且与所述承载单元电性连接；
塑封层，塑封料将芯片和至少部分所述承载单元包裹，所述第一凹槽被塑封料填充，以构成所述塑封层；
电镀层，所述电镀层设置在所述引线框架的第二表面，且延伸入所述第三凹槽、或所述第三凹槽和所述第二凹槽。
其中，所述承载单元设置有以所述通孔间隔的基岛和引脚，所述引脚包括位于所述引线框架的第一表面一侧的内引脚和位于所述引线框架的第二表面一侧的外引脚，所述芯片通过导线电性连接所述内引脚。
其中，所述内引脚的表面设有金属层，所述导线电性连接所述芯片与所述金属层。
其中，所述承载单元设置有以所述通孔间隔的引脚，所述引脚包括位于所述引线框架的第一表面一侧的内引脚和位于所述引线框架的第二表面一侧的外引脚，所述芯片表面设置有凸柱，所述凸柱电性连接所述通孔周围的所述内引脚。
其中，所述第二凹槽在所述第一表面上的投影覆盖所述第一凹槽在所述第一表面上的投影，所述塑封层填充所述第一凹槽且凸出于所述第二凹槽内。
其中，所述电镀层延伸入所述第三凹槽的侧边和底边；或者，所述电镀层延伸入所述第三凹槽的侧边和底边、以及所述第二凹槽未被所述塑封料覆盖的侧边和底边。
其中，所述塑封层由一个或多个塑封体构成，单个所述塑封体内包含多个矩阵排列的承载单元。
其中，所述塑封层由矩阵排列的多个分立的塑封体构成，且所述塑封体与承载单元一一对应。
其中，相邻所述塑封体间的间距大于所述第三凹槽。
其中，所述引脚在沿所述第二凹槽、所述第三凹槽连线方向的竖向截面为T形。
本申请的有益效果是：区别于现有技术的情况，本申请所提供的半导体芯片封装阵列包括：自引线框架的第二表面向第一表面延伸的第二凹槽和第三凹槽，电镀层覆盖金属板的第二表面且延伸入第三凹槽或者第二凹槽和第三凹槽内。通过上述方式，可以使半导体芯片封装阵列的引脚形成多面具有电镀层的结构，增加了供焊锡攀爬的面积，进而提高了焊接性能，增加了半导体芯片封装阵列的良率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本申请半导体芯片封装方法一实施方式的流程示意图；
图2是图1中步骤S101-S107对应的一实施方式的结构示意图；
图3是图1中步骤S103-S107对应的另一实施方式的结构示意图；
图4是图1中步骤S104-S107对应的另一实施方式的结构示意图；
图5是图1中步骤S104-S107对应的另一实施方式的结构示意图；
图6是本申请半导体芯片封装阵列一实施方式的结构示意图；
图7是本申请半导体芯片封装阵列另一实施方式的结构示意图；
图8是本申请半导体芯片封装阵列另一实施方式的结构示意图；
图9是本申请半导体芯片封装阵列另一实施方式的结构示意图；
图10是本申请半导体芯片封装阵列另一实施方式的结构示意图；
图11是本申请半导体芯片封装器件一实施方式的结构示意图；
图12是本申请半导体芯片封装器件另一实施方式的结构示意图；
图13是本申请半导体芯片封装器件另一实施方式的结构示意图；
图14是本申请半导体芯片封装器件另一实施方式的结构示意图；
图15是本申请半导体芯片封装器件另一实施方式的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1-图2，图1为本申请半导体芯片封装方法一实施方式的流程示意图，图2为图1中步骤S101-S107对应的一实施方式的结构示意图，图3为图1中步骤S103-S107对应的另一实施方式的结构示意图，图4为图1中步骤S104-S107对应的另一实施方式的结构示意图，图5为图1中步骤S104-S107对应的另一实施方式的结构示意图，该方法包括：
S101：提供一具有第一表面及第二表面的金属板。
具体地，请参阅图2a，金属板10包括第一表面100和第二表面102。在一个应用场景中，金属板10的材质可以为铜及其合金等，也可以为铁镍合金等具有良好导电性、导热性以及较好机械强度的材料，金属板10只需满足能够用于制作半导体芯片封装器件的引线框架的条件即可。
S102：在金属板的第一表面形成第一凹槽，以定义出多个矩阵排列的承载单元。
具体地，请参见图2b，在一个应用场景中，可以利用蚀刻等工艺在金属板10的第一表面100上形成多个第一凹槽12，进而定义出多个矩阵排列的承载单元(未标示)。所谓承载单元，是用于承载芯片的最小单元，其具体范围可由后续芯片正装还是倒装的方式决定，具体可参见下面的相关内容。本申请是在金属板10的一侧进行半蚀刻形成第一凹槽12，然后在该金属板10上进行后续芯片14塑封，与传统的在蚀通的引线框架进行芯片塑封相比，本申请所提供的方案增强了框架的强度。
S103：将芯片电性连接于承载单元。
具体地，在一个实施方式中，如图2c-2d所示，芯片14可以正装于承载单元16，承载单元16设置有以第一凹槽12间隔的基岛160和引脚162(仅示意标出一个，一个承载单元16可包含多个引脚162)，引脚162包括位于金属板10的第一表面100一侧的内引脚1620和位于金属板10的第二表面102一侧的外引脚1622，上述步骤S103具体包括：将芯片14安装在承载单元16的基岛160上，采用导线18电性连接芯片14与承载单元16的内引脚1620。在本实施例中，芯片14可通过导线18将信号传输给引脚162或通过导线18接收引脚162传输的信号。其中，导线18的材质可以为金、铝、铜以及铜-铁系、铜-镍-硅系、铜-铬系、铜-镍-锡系合金中的任一种或多种的组合物，只需该导线18具有导电功能且较好的机械强度，抗应力松弛特性即可。
在一个应用场景中，在上述步骤采用导线18电性连接芯片14与承载单元16的内引脚1620之前，还包括：在内引脚1620的表面形成金属层11；上述步骤采用导线18电性连接芯片14与承载单元16的内引脚1620包括：采用导线18电性连接芯片14与承载单元16的内引脚1620表面的金属层11。在本实施例中，在内引脚1620上形成金属层11的方式可以是电镀(例如，局部电镀、复合电镀、脉冲电镀、电铸、机械镀等)等方式，金属层11的材质可以为镍、铬、铜、锌、镉等具有导电性的金属材料，本申请对此不做限定。
在另一个实施方式中，如图3a所示，芯片14可以倒装于承载单元16a，承载单元16a设置有以第一凹槽12间隔的引脚162a(仅示意标出一个，一个承载单元16a可包含多个引脚162a)，引脚162a包括位于金属板10的第一表面100一侧的内引脚1620a和位于金属板10的第二表面102一侧的外引脚1622a，上述步骤S103具体包括：芯片14表面设置有凸柱140，凸柱140电性连接第一凹槽12周围的内引脚1620a。
S104：用塑封料对承载单元进行塑封以形成塑封层，第一凹槽被塑封料填充。
具体地，塑封料的材质可以是环氧树脂等透明或者非透明的材质。当芯片14采用正装的方式时，如图2e所示，上述步骤S104具体包括：形成矩阵排列的多个分立的塑封体13，塑封体13与承载单元16一一对应。在本实施例中，相邻塑封体13之间的塑封层15互不相连。塑封层15覆盖该承载单元16对应的第一凹槽12、芯片14、导线18、以及覆盖金属板10的第一表面100对应内引脚1620的区域。
当然，在其他应用场景中，当芯片14采用正装的方式时，形成塑封体的方式也可为其他，如图4a所示，上述步骤S104具体包括：形成一个或多个塑封体13a，单个塑封体13a内包含多个矩阵排列的承载单元16。
类似的，当芯片14采用倒装的方式时，塑封的方式与上述实施例中芯片14采用正装类似，具体可参见图3b和图5a，在此不再赘述。
S105：在金属板的第二表面形成第二凹槽和第三凹槽，第二凹槽与第一凹槽相通以形成通孔，第三凹槽连接相邻的承载单元。
具体地，在一个应用场景中，请参阅图2f-2g，上述步骤S105具体包括：
A、在金属板10的第二表面102形成图形化的掩膜17；
B、蚀刻金属板10的第二表面102的无掩膜17覆盖的区域，以形成第二凹槽190和第三凹槽192，并使第二凹槽190与第一凹槽12相通。
在本实施例中，在金属板10的第二表面102形成图形化的掩膜17，掩膜17覆盖金属板10的第二表面102不需要进行蚀刻的区域。第一凹槽12两侧的引脚162与基岛160对应第二表面102部分区域覆盖有掩膜17，掩膜17在第一凹槽12的下方形成开口(未标示)，第一凹槽12在金属板10第二表面102的正投影(未标示)位于该开口内，且该正投影的边界(未标示)与该开口的边界不接触。对金属板10的第二表面102没有覆盖掩膜17的区域进行蚀刻，以同时形成第二凹槽190和第三凹槽192。继续蚀刻金属板10的第二表面102无掩膜17区域，以使第二凹槽190的底面x1高于第一凹槽12的底面x2，进而使第二凹槽190与第一凹槽12相通。此时，第二凹槽190在第一表面100上的投影覆盖第一凹槽12在第一表面100上的投影，且第一凹槽12的底部x2凸出于第二凹槽190中以使第一凹槽12中的塑封料15凸出于第二凹槽190内。该塑封料15凸出的部分可以使形成的半导体芯片封装器件在进行焊接安装工作时避免引脚162与基岛160上的焊料连接，发生短路，并同时增强金属板10的强度。当然，在其他实施例中，蚀刻金属板10的第二表面102形成的第二凹槽190的底面x1还可与第一凹槽12的底面x2重合，本申请对此不作限定。
在另一个应用场景中，当上述步骤S104形成的塑封体13与承载单元16一一对应时，相邻塑封体13间的间距d1大于第三凹槽192的宽度d2，其中，相邻塑封体13之间的间距d1是指相邻塑封体13的相邻的塑封料15的边缘在第一表面100上的投影之间的距离，第三凹槽192的宽度d2是指第三凹槽192两个侧边在在第一表面100上的投影的之间的距离。这种设计方式可以避免后续进行塑封体13切割分离时，引脚162发生弯折或脱落现象。
在其他应用场景中，芯片14可以采取倒装的方式，且形成第二凹槽和第三凹槽的方式与上述类似，在此不再赘述，具体可参见图3c-3d，图4b-4c，图5b-5c。
S106：在金属板的第二表面形成电镀层，电镀层延伸入第三凹槽、或第二凹槽和第三凹槽内。
具体地，请参阅图2h，可以利用电镀等工艺在金属板10的第二表面102形成电镀层110，电镀层110的材质可以是锡、铜、金、镍、铅等金属构成。在本实施例中，电镀层110延伸入第二凹槽190和第三凹槽192，电镀层110可以仅覆盖这两个凹槽的侧壁，也可以还覆盖这两个凹槽的底面。在其他实施例中，电镀层110也可以只延伸入第三凹槽192或第二凹槽190。
在其他应用场景中，芯片14采取倒装的方式，形成电镀层方式与上述类似，在此不再赘述，具体可参见图3e，图4d，图5d。
S107：分离塑封层以形成独立的半导体芯片封装器件。
具体地，该步骤S107包括：对塑封层15进行分割，得到独立的半导体芯片封装器件2，使半导体芯片封装器件2的引脚162在沿第二凹槽190、第三凹槽192连线方向的竖向截面为T形。
在一个应用场景中，可以采用冲切或切割的方式分离塑封层15，得到独立的半导体芯片封装器件2，其中，获得的每个半导体封装器件2均为一个完整的芯片封装单元，该半导体封装器件2包括芯片14、覆盖芯片14的塑封层15，以及与芯片14对应的导线18。在对塑封层15进行分离时，需要沿经过金属板10的分离线111对塑封层15进行分离，其中，分离线111位于第三凹槽192对应的区域，分离线111可以位于第三凹槽192对应的中央区域，也可偏离中央区域，本申请对此不作限定。
在另一个应用场景中，在分离塑封层15时，为防止金属板10上的引脚162在分离时弯折，还可在第二凹槽190和第三凹槽192的下方设置垫块(图未示)，其中，垫块可以完全填充金属板10第二表面102的第二凹槽190和第三凹槽192。在其他实施例中，垫块还可以仅充满第三凹槽192，或部分支撑第三凹槽192的底面，本申请对此不做限定。
总而言之，采用本申请所提供的半导体封装方法所形成的外引脚1622除包含传统的可供焊锡攀爬的第二表面102对应的区域外，还包括可供焊锡攀爬的台阶部(例如，第三凹槽192、第二凹槽190形成的区域)，该台阶部的侧边和底边均可供焊锡攀爬，进而增加了外引脚1622供焊锡攀爬的面积，进而提高了焊接性能，增加了半导体芯片封装器件的良率。
请参阅图6-图10，图6为本申请半导体芯片封装阵列一实施方式的结构示意图，图7为本申请半导体芯片封装阵列另一实施方式的结构示意图，图8为本申请半导体芯片封装阵列另一实施方式的结构示意图，图9为本申请半导体芯片封装阵列另一实施方式的结构示意图，图10为本申请半导体芯片封装阵列另一实施方式的结构示意图。该半导体芯片封装阵列3由上述方法S101-S106制备获得。具体地，该半导体芯片封装阵列3包括：
引线框架30，引线框架30包括：多个矩阵排列的承载单元300、自引线框架30的第一表面302向第二表面304延伸的第一凹槽306、自第二表面304向第一表面302延伸的第二凹槽308、自第二表面304向第一表面302延伸的第三凹槽301，其中，第一凹槽306与第二凹槽308相通以形成通孔，第三凹槽301连接相邻的承载单元300；
芯片32，芯片32设置在承载单元300上，且与承载单元300电性连接；在一个应用场景中，如图6所示，芯片32采用正装的方式与承载单元300电性连接。承载单元300设置有以通孔(或第一凹槽306)间隔的基岛3000和引脚3002，引脚3002包括位于引线框架30的第一表面302一侧的内引脚A和位于引线框架30的第二表面304一侧的外引脚B，芯片32通过导线C电性连接内引脚A。在一个实施方式中，内引脚A的表面设有金属层D，导线C电性连接芯片32与金属层D。在本实施例中，引脚3002在沿第二凹槽308、第三凹槽301连线方向的竖向截面为T形，当然，在其他实施例中，引脚3002也可为其他形状，本申请对此不作限定。在另一个应用场景中，如图7所示，芯片32也可采用倒装的方式与承载单元300′电连接。承载单元300′设置有以通孔(或第一凹槽306′)间隔的引脚3002′，引脚3002′包括位于引线框架30′的第一表面302′一侧的内引脚A′和位于引线框架30′的第二表面304′一侧的外引脚B′，芯片32表面设置有凸柱320，凸柱320电性连接通孔周围的内引脚A′。
塑封层34，塑封料将芯片32和至少部分承载单元300包裹，第一凹槽306被塑封料填充，以构成塑封层34；在一个应用场景中，第二凹槽308在第一表面302上的投影覆盖第一凹槽306在第一表面302上的投影，塑封层34填充第一凹槽306且凸出于第二凹槽308内，当然，在其他应用场景中，塑封层34也可只填充第一凹槽306且不凸出于第二凹槽308，本申请对此不作限定。在另一个应用场景中，请继续参阅图6，塑封层34由矩阵排列的多个分立的塑封体(未标示)构成，且塑封体与承载单元300一一对应。相邻塑封体间的间距d3大于第三凹槽的宽度d4。在另一个应用场景中，如图8所示，塑封层34″由一个或多个塑封体构成，单个塑封体内包含多个矩阵排列的承载单元300。当芯片采取倒装的形式时，塑封层的结构与上述类似，在此不再赘述，具体可参见图7和图9。
电镀层36，电镀层36设置在引线框架30的第二表面304，且延伸入第三凹槽301和第二凹槽308，具体而言，电镀层36延伸入第三凹槽301的侧边(未标示)和底边(未标示)、以及第二凹槽308未被塑封料覆盖的侧边(未标示)和底边(未标示)。在其他实施方式中，如图10所示，电镀层36″也可只延伸入第三凹槽308″的侧边和底边。
请参阅图11-图15，图11为本申请半导体芯片封装器件一实施方式的结构示意图，图12为本申请半导体芯片封装器件另一实施方式的结构示意图，图13为本申请半导体芯片封装器件另一实施方式的结构示意图，图14为本申请半导体芯片封装器件另一实施方式的结构示意图，图15为本申请半导体芯片封装器件另一实施方式的结构示意图。该半导体芯片封装器件4由上述方法S101-S107制备获得。具体地，该半导体芯片封装器件4包括：
引线框架40，包括自引线框架40的第一表面400向第二表面402延伸的第一凹槽404、自第二表面402向第一表面400延伸的第二凹槽406、自第二表面402向第一表面400延伸的第三凹槽408，其中，第一凹槽404与第二凹槽406相通以形成通孔，第三凹槽408位于引线框架40的边缘；在一个应用场景中，如图11所示，第二凹槽406在第一表面400上的投影覆盖第一凹槽404在第一表面400上的投影，第二凹槽406在第一表面400上的投影可以比第一凹槽404在第一表面400上的投影大，也可以相同，本申请对此不作限定；在另一个应用场景中，请继续参阅图11，第三凹槽408在引线框架40的端部形成台阶部，该台阶部使得半导体封装器件4的引脚401在沿第二凹槽406、第三凹槽408连线方向的竖向截面为T形。当然，在其他应用场景中，第三凹槽408也可在引线框架40的端部形成其他形状，例如斜坡等，本申请对此不作限定。
芯片42，电性连接引线框架40；在一个应用场景中，如图11所示，芯片42采用正装的方式电性连接引线框架40；引线框架40包括基岛403和位于基岛403周围的引脚401，引脚401包括位于第一表面400一侧的内引脚E和位于第二表面402一侧的外引脚F，基岛403和引脚401之间以通孔(或第一凹槽404)间隔，芯片42安装于基岛403上，且芯片42通过导线G与内引脚E电性连接。在本实施例中，内引脚E的表面还形成有金属层H，芯片42通过导线G与金属层H电性连接。在另一个实施方式中，如图12所示，芯片42采用倒装的方式与引线框架40′电性连接。引线框架40′包括以通孔(或第一凹槽404)间隔的引脚401′，引脚401′包括位于第一表面400′一侧的内引脚E′和位于第二表面402′一侧的外引脚F′，芯片42表面设置有凸柱420，凸柱420电性连接通孔周围的内引脚E′。
塑封层44，塑封料将引线框架40的全部或部分第一侧面400、以及芯片42包裹，第一凹槽404被塑封料填充，以构成塑封层44；在本实施例中，塑封层44填充第一凹槽404且凸出于第二凹槽406内，当然，在其他实施例中，塑封层44也可只填充第一凹槽404而不凸出于第二凹槽406内。另外，在本实施例中，请继续参阅图11，塑封层44部分覆盖引线框架40的第一表面400，台阶部(即第三凹槽408)包括靠近塑封层44的竖直方向上的侧边J，侧边J位于塑封层44的投影区外。在另一个实施方式中，请参阅图13，塑封层44′完全覆盖引线框架40的第一表面400，台阶部(即第三凹槽408)的边缘位于塑封层44′的投影区内。类似的，当芯片42采用倒装的方式时，塑封层的结构可参见图12和14，在此不再赘述。
电镀层46，电镀层46设置在引线框架40的第二表面402，且延伸入第三凹槽408和第二凹槽406。具体地，电镀层46延伸入第三凹槽408的侧边(未标示)和底边(未标示)、以及第二凹槽406未被塑封料覆盖的侧边(未标示)和底边(未标示)。在其他实施例中，请参阅图15，电镀层46′也可只延伸入第三凹槽408的侧边和底边，而不延伸入第二凹槽406。
总而言之，区别于现有技术的情况，本申请所提供的半导体芯片封装阵列包括：自引线框架的第二表面向第一表面延伸的第二凹槽和第三凹槽，电镀层覆盖金属板的第二表面且延伸入第三凹槽或者第二凹槽和第三凹槽内。通过上述方式，可以使半导体芯片封装阵列的引脚形成多面具有电镀层的结构，增加了供焊锡攀爬的面积，进而提高了焊接性能，增加了半导体芯片封装阵列的良率。。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

1.一种半导体芯片封装阵列，其特征在于，包括：
引线框架，所述引线框架包括：多个矩阵排列的承载单元、自引线框架的第一表面向第二表面延伸的第一凹槽、自所述第二表面向第一表面延伸的第二凹槽、自所述第二表面向第一表面延伸的第三凹槽，其中，所述第一凹槽与所述第二凹槽相通以形成通孔，所述第三凹槽连接相邻的承载单元；
芯片，所述芯片设置在所述承载单元上，且与所述承载单元电性连接；
塑封层，塑封料将芯片和至少部分所述承载单元包裹，所述第一凹槽被塑封料填充，以构成所述塑封层；
电镀层，所述电镀层设置在所述引线框架的第二表面，且延伸入所述第三凹槽、或所述第三凹槽和所述第二凹槽。
2.根据权利要求1所述的半导体芯片封装阵列，其特征在于，
所述承载单元设置有以所述通孔间隔的基岛和引脚，所述引脚包括位于所述引线框架的第一表面一侧的内引脚和位于所述引线框架的第二表面一侧的外引脚，所述芯片通过导线电性连接所述内引脚。
3.根据权利要求2所述的半导体芯片封装阵列，其特征在于，
所述内引脚的表面设有金属层，所述导线电性连接所述芯片与所述金属层。
4.根据权利要求1所述的半导体芯片封装阵列，其特征在于，
所述承载单元设置有以所述通孔间隔的引脚，所述引脚包括位于所述引线框架的第一表面一侧的内引脚和位于所述引线框架的第二表面一侧的外引脚，所述芯片表面设置有凸柱，所述凸柱电性连接所述通孔周围的所述内引脚。
5.根据权利要求1所述的半导体芯片封装阵列，其特征在于，
所述第二凹槽在所述第一表面上的投影覆盖所述第一凹槽在所述第一表面上的投影，所述塑封层填充所述第一凹槽且凸出于所述第二凹槽内。
6.根据权利要求5所述的半导体芯片封装阵列，其特征在于，
所述电镀层延伸入所述第三凹槽的侧边和底边；或者，所述电镀层延伸入所述第三凹槽的侧边和底边、以及所述第二凹槽未被所述塑封料覆盖的侧边和底边。
7.根据权利要求1至6任一项所述的半导体芯片封装阵列，其特征在于，所述塑封层由一个或多个塑封体构成，单个所述塑封体内包含多个矩阵排列的承载单元。
8.根据权利要求1至6任一项所述的半导体芯片封装阵列，其特征在于，所述塑封层由矩阵排列的多个分立的塑封体构成，且所述塑封体与承载单元一一对应。
9.根据权利要求8所述的半导体芯片封装阵列，其特征在于，相邻所述塑封体间的间距大于所述第三凹槽。
10.根据权利要求2至4任一项所述的半导体芯片封装阵列，其特征在于，所述引脚在沿所述第二凹槽、所述第三凹槽连线方向的竖向截面为T形。
CN201810608530.2A 2018-06-13 2018-06-13 一种半导体芯片封装阵列 Active CN109065518B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810608530.2A CN109065518B (zh) 2018-06-13 2018-06-13 一种半导体芯片封装阵列
US16/440,773 US10937745B2 (en) 2018-06-13 2019-06-13 Semiconductor chip package array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810608530.2A CN109065518B (zh) 2018-06-13 2018-06-13 一种半导体芯片封装阵列

Publications (2)

Publication Number Publication Date
CN109065518A true CN109065518A (zh) 2018-12-21
CN109065518B CN109065518B (zh) 2020-12-25

Family

ID=64820738

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810608530.2A Active CN109065518B (zh) 2018-06-13 2018-06-13 一种半导体芯片封装阵列

Country Status (2)

Country Link
US (1) US10937745B2 (zh)
CN (1) CN109065518B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11545418B2 (en) * 2018-10-24 2023-01-03 Texas Instruments Incorporated Thermal capacity control for relative temperature-based thermal shutdown
JP7450575B2 (ja) * 2021-03-18 2024-03-15 株式会社東芝 半導体装置及びその製造方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1666338A (zh) * 2002-07-01 2005-09-07 株式会社瑞萨科技 半导体器件及其制造方法
CN102779761A (zh) * 2011-05-10 2012-11-14 Nxp股份有限公司 用于封装半导体管芯的引线框架和方法
CN103021994A (zh) * 2012-12-28 2013-04-03 华天科技（西安）有限公司 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺
CN103021890A (zh) * 2012-12-17 2013-04-03 北京工业大学 一种qfn封装器件的制造方法
CN103681535A (zh) * 2012-09-01 2014-03-26 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法
CN103730429A (zh) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 封装结构
CN103928353A (zh) * 2014-04-14 2014-07-16 矽力杰半导体技术(杭州)有限公司 无外引脚封装构造及其制造方法与导线框架
CN105097571A (zh) * 2015-06-11 2015-11-25 矽力杰半导体技术(杭州)有限公司 芯片封装方法及封装组件
CN204834611U (zh) * 2015-07-29 2015-12-02 嘉盛半导体(苏州)有限公司 引线框架及其单元、半导体封装结构及其单元
CN108109972A (zh) * 2017-12-29 2018-06-01 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847458A (en) * 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
US9899349B2 (en) * 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
CN102473651B (zh) * 2009-07-06 2014-12-17 瑞萨电子株式会社 半导体器件的制造方法
US8890301B2 (en) * 2012-08-01 2014-11-18 Analog Devices, Inc. Packaging and methods for packaging
US20160172275A1 (en) * 2014-12-10 2016-06-16 Stmicroelectronics S.R.L. Package for a surface-mount semiconductor device and manufacturing method thereof
US9578744B2 (en) * 2014-12-22 2017-02-21 Stmicroelectronics, Inc. Leadframe package with pre-applied filler material
JP6770853B2 (ja) * 2016-08-31 2020-10-21 新光電気工業株式会社 リードフレーム及び電子部品装置とそれらの製造方法
US9972558B1 (en) * 2017-04-04 2018-05-15 Stmicroelectronics, Inc. Leadframe package with side solder ball contact and method of manufacturing
US10199312B1 (en) * 2017-09-09 2019-02-05 Amkor Technology, Inc. Method of forming a packaged semiconductor device having enhanced wettable flank and structure
US11062980B2 (en) * 2017-12-29 2021-07-13 Texas Instruments Incorporated Integrated circuit packages with wettable flanks and methods of manufacturing the same
US11127661B2 (en) * 2018-06-13 2021-09-21 Tongfu Microelectronics Co., Ltd. Semiconductor chip package method and semiconductor chip package device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1666338A (zh) * 2002-07-01 2005-09-07 株式会社瑞萨科技 半导体器件及其制造方法
CN102779761A (zh) * 2011-05-10 2012-11-14 Nxp股份有限公司 用于封装半导体管芯的引线框架和方法
CN103681535A (zh) * 2012-09-01 2014-03-26 万国半导体股份有限公司 带有厚底部基座的晶圆级封装器件及其制备方法
CN103021890A (zh) * 2012-12-17 2013-04-03 北京工业大学 一种qfn封装器件的制造方法
CN103021994A (zh) * 2012-12-28 2013-04-03 华天科技（西安）有限公司 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺
CN103730429A (zh) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 封装结构
CN103928353A (zh) * 2014-04-14 2014-07-16 矽力杰半导体技术(杭州)有限公司 无外引脚封装构造及其制造方法与导线框架
CN105097571A (zh) * 2015-06-11 2015-11-25 矽力杰半导体技术(杭州)有限公司 芯片封装方法及封装组件
CN204834611U (zh) * 2015-07-29 2015-12-02 嘉盛半导体(苏州)有限公司 引线框架及其单元、半导体封装结构及其单元
CN108109972A (zh) * 2017-12-29 2018-06-01 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺

Also Published As

Publication number Publication date
CN109065518B (zh) 2020-12-25
US10937745B2 (en) 2021-03-02
US20190385955A1 (en) 2019-12-19

Similar Documents

Publication Publication Date Title
US11127661B2 (en) Semiconductor chip package method and semiconductor chip package device
US8551794B2 (en) LED package and mold of manufacturing the same
US20150034371A1 (en) Structure for microelectronic packaging with bond elements to encapsulation surface
US9543235B2 (en) Semiconductor package and method therefor
TW200818458A (en) Stackable packages for three-dimensional packaging of semiconductor dice
US8133759B2 (en) Leadframe
CN103745931B (zh) 引线框架和封装结构的形成方法
CN101060087A (zh) 电极及其制造方法,以及具有该电极的半导体器件
CN109065519A (zh) 一种半导体芯片封装器件
CN108109972A (zh) 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN109037077A (zh) 一种半导体芯片封装方法
TWM556934U (zh) 具有接點溝槽的預成形導線架
CN109065518A (zh) 一种半导体芯片封装阵列
CN105845585A (zh) 一种芯片封装方法及芯片封装结构
CN108198790A (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN109037183A (zh) 一种半导体芯片封装阵列和半导体芯片封装器件
CN103021892B (zh) 无外引脚半导体封装构造及其制造方法与导线架条
CN101944520B (zh) 半导体封装结构与半导体封装工艺
CN103745967A (zh) 引线框架和封装结构
CN103021879B (zh) 无外引脚半导体封装构造及其制造方法与导线架条
CN105428507A (zh) 芯片封装结构及方法
CN101325191A (zh) 芯片上具有图案的四方扁平无引脚封装结构
CN108198804A (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN205141022U (zh) 芯片封装结构
CN101937850A (zh) 封装制造方法和半导体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant