CN105118787A - 一种采用激光烧铜的产品加工工艺 - Google Patents
一种采用激光烧铜的产品加工工艺 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/361—Removing material for deburring or mechanical trimming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
本发明公开了一种采用激光烧铜的产品加工工艺，包括如下步骤：（1）蚀刻：对目标铜板进行正面蚀刻；（2）对步骤（1）中蚀刻完成的铜板进行固晶、打线和模压；（3）烧铜：对模压后的产品进行烧铜工艺，实现端电极露铜；（4）切割：对烧铜后的产品进行切割，完成产品的加工；其中，步骤（3）中烧铜工艺中采用的是激光烧铜的干式蚀刻工艺。通过采用激光蚀刻的方式完成模压后的烧铜工序，提高了烧铜精度，减小了产品误差，且不会有废水产生，制程时间也更短。
Description
技术领域
本发明涉及了一种采用激光烧铜的产品加工工艺，属于电子产品加工技术领域。
背景技术
在电阻等电子产品的加工过程中，通常会涉及到如下工艺：正面蚀刻、固晶、打线、模压、烧铜、切割等六大工艺步骤。
现有的制作工艺通常是在烧铜工艺中采用湿式蚀刻的方式，即采用腐蚀性液体对其铜板完成烧铜。但是湿式蚀刻法会在蚀刻面处存在一定的公差，而且会有大量的蚀刻废水需要处理，且需要的蚀刻时间也较长，不利用缩短整个产品的加工周期。
发明内容
本发明所要解决的技术问题是提供一种采用激光烧铜的产品加工工艺，采用激光蚀刻的方式完成模压后的烧铜工序，提高了烧铜精度，减小了产品误差，且不会有废水产生，制程时间也更短。
为了解决上述技术问题，本发明所采用的技术方案是：
一种采用激光烧铜的产品加工工艺，包括如下步骤：
（1）蚀刻：对目标铜板进行正面蚀刻；
（2）对步骤（1）中蚀刻完成的铜板进行固晶、打线和模压；
（3）烧铜：对模压后的产品进行烧铜工艺，实现端电极露铜；
（4）切割：对烧铜后的产品进行切割，完成产品的加工；
步骤（3）中烧铜工艺中采用的是激光烧铜的干式蚀刻工艺。
前述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（1）中所采用的铜板厚度为0.1mm，正面蚀刻的厚度为0.05mm。
前述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（2）中固晶的尺寸为200um*200um，厚度为100um；打线的线高不大于160um；模压的深度不大于250um。
前述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（1）中正面蚀刻后的切割道的宽度为0.16mm。
前述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（2）中所采用的打线材质为金线。
本发明的有益效果是：
1、激光烧铜为干式蚀刻，较之湿式蚀刻，有较小的尺寸公差；
2、没有湿式蚀刻的因之产生的废水处理的问题；
3、激光烧铜比湿式蚀刻铜制程时间为短，约缩短约30%的制程时间。
附图说明
图1是本发明的产品在完成蚀刻后的结构示意图；
图2是本发明的产品在完成固晶、打线后的结构示意图；
图3是本发明的产品在模压后的结构示意图；
图4是本发明的产品在烧铜后的结构示意图；
图5是本发明产品的结构示意图。
具体实施方式
下面将结合说明书附图，对本发明作进一步的说明。
一种采用激光烧铜的产品加工工艺，包括如下步骤：（1）蚀刻：对目标铜板进行正面蚀刻；其中铜板厚度为0.1mm，正面蚀刻的厚度为0.05mm，其蚀刻的深度越深越好，以不蚀穿即可，正面蚀刻后的切割道的宽度为0.16mm，如图1所示。
（2）对步骤（1）中蚀刻完成的铜板进行固晶、打线和模压；其中固晶的尺寸为200um*200um，厚度为100um；采用金线进行打线，线高不大于160um；模压的深度不大于250um，如图2和图3所示。
（3）烧铜：对模压后的产品进行烧铜工艺，实现端电极露铜；其中烧铜工艺中采用的是激光烧铜的干式蚀刻工艺，相比较与传统的湿式蚀刻法，采用激光烧铜的干式蚀刻，在蚀刻面不会产生偏差，产品尺寸公差较小，且没有湿式蚀刻的因之产生的废水处理的问题；激光干式烧铜比湿式蚀刻铜制程时间为短，约缩短约30%的制程时间，如图4所示。
（4）切割：对烧铜后的产品进行切割，完成产品的加工，如图5所示。
综上所述，本发明提供了一种采用激光烧铜的产品加工工艺，采用激光蚀刻的方式完成模压后的烧铜工序，提高了烧铜精度，减小了产品误差，且不会有废水产生，制程时间也更短。
以上显示和描述了本发明的基本原理、主要特征及优点。本行业的技术人员应该了解，本发明不受上述实施例的限制，上述实施例和说明书中描述的只是说明本发明的原理，在不脱离本发明精神和范围的前提下，本发明还会有各种变化和改进，这些变化和改进都落入要求保护的本发明范围内。本发明要求保护范围由所附的权利要求书及其等效物界。
Claims (5)
1.一种采用激光烧铜的产品加工工艺，包括如下步骤：
（1）蚀刻：对目标铜板进行正面蚀刻；
（2）对步骤（1）中蚀刻完成的铜板进行固晶、打线和模压；
（3）烧铜：对模压后的产品进行烧铜工艺，实现端电极露铜；
（4）切割：对烧铜后的产品进行切割，完成产品的加工；
其特征在于：步骤（3）中烧铜工艺中采用的是激光烧铜的干式蚀刻工艺。
2.根据权利要求1所述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（1）中所采用的铜板厚度为0.1mm，正面蚀刻的厚度为0.05mm。
3.根据权利要求2所述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（2）中固晶的尺寸为200um*200um，厚度为100um；打线的线高不大于160um；模压的深度不大于250um。
4.根据权利要求3所述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（1）中正面蚀刻后的切割道的宽度为0.16mm。
5.根据权利要求4所述的一种采用激光烧铜的产品加工工艺，其特征在于：步骤（2）中所采用的打线材质为金线。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1650410A (zh) * | 2002-04-29 | 2005-08-03 | 先进互联技术有限公司 | 部分构图的引线框架及其制造方法以及在半导体封装中的使用 |
| CN101866867A (zh) * | 2010-06-18 | 2010-10-20 | 日月光封装测试(上海)有限公司 | 无外引脚半导体封装构造的导线架制造方法 |
| CN202003988U (zh) * | 2011-02-22 | 2011-10-05 | 苏州日月新半导体有限公司 | 四方扁平无外引脚封装构造及其导线架条 |
| CN103021994A (zh) * | 2012-12-28 | 2013-04-03 | 华天科技（西安）有限公司 | 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺 |
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- 2015-04-22 CN CN201510191597.7A patent/CN105118787A/zh active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1650410A (zh) * | 2002-04-29 | 2005-08-03 | 先进互联技术有限公司 | 部分构图的引线框架及其制造方法以及在半导体封装中的使用 |
| CN101866867A (zh) * | 2010-06-18 | 2010-10-20 | 日月光封装测试(上海)有限公司 | 无外引脚半导体封装构造的导线架制造方法 |
| CN202003988U (zh) * | 2011-02-22 | 2011-10-05 | 苏州日月新半导体有限公司 | 四方扁平无外引脚封装构造及其导线架条 |
| CN103021994A (zh) * | 2012-12-28 | 2013-04-03 | 华天科技（西安）有限公司 | 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺 |
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