JP6471885B2 - 実装構造体の製造方法 - Google Patents
実装構造体の製造方法 Download PDFInfo
- Publication number
- JP6471885B2 JP6471885B2 JP2013257358A JP2013257358A JP6471885B2 JP 6471885 B2 JP6471885 B2 JP 6471885B2 JP 2013257358 A JP2013257358 A JP 2013257358A JP 2013257358 A JP2013257358 A JP 2013257358A JP 6471885 B2 JP6471885 B2 JP 6471885B2
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- JP
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- Prior art keywords
- solder
- substrate
- electronic component
- joint
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/8192—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Description
前記基板の反りに伴い、前記電子部品の下面と前記基板上面との間隔が狭くなる接合部に供給する前記はんだペーストの供給量を、メタルマスクを用いて少なく調整し、
はんだ量が多い接合部の前記電子部品と前記基板との間隔をt、はんだ量が少ない接合部の前記電子部品と前記基板との間隔をt’、その差t−t’を接合部の反りとし、前記はんだ量が多い接合部に対する前記はんだ量が少ない接合部の反りの比aを、
a=(t−t’)/t×100とし、
前記はんだ量が多い接合部に前記はんだペーストを供給する前記メタルマスクの開口面積をSとした場合、はんだ量が少ないメタルマスクの開口面積S’が、
2/3×S ≦ S’ ≦ S−S×a/100
の範囲となるように設定されていることを特徴とする。
2/3×S ≦ S’ ≦ S−S×a/100
の関係となるようにメタルマスクの開口面積を設定する。
(電子部品)
LGAパッケージCMOSセンサー
サイズ:14×14mm
電極径:0.4mm
ピッチ:0.8mm
(基板)
厚み:0.8mm
電極径:0.4mm
(メタルマスク)
開口径(S):0.4mm
厚さ:0.12mm
開口面積:S=0.126mm2
また、はんだペーストとして表1に示す配合成分、配合量のものを用いた。なお、配合量は質量%を表す。
11 電極
2 基板
21 電極
5 メタルマスク
Claims (3)
- 電子部品下面に設けられた電極と基板上面に形成された電極とを、熱硬化性樹脂バインダーを含むはんだペーストを用いて接合した後、さらに前記基板の下面に設けられた電極と回路基板表面に備えられた電極とを接合する実装構造体の製造方法であって、
前記基板の反りに伴い、前記電子部品の下面と前記基板上面との間隔が狭くなる接合部に供給する前記はんだペーストの供給量を、メタルマスクを用いて少なく調整し、
はんだ量が多い接合部の前記電子部品と前記基板との間隔をt、はんだ量が少ない接合部の前記電子部品と前記基板との間隔をt’、その差t−t’を接合部の反りとし、前記はんだ量が多い接合部に対する前記はんだ量が少ない接合部の反りの比aを、
a=(t−t’)/t×100とし、
前記はんだ量が多い接合部に前記はんだペーストを供給する前記メタルマスクの開口面積をSとした場合、はんだ量が少ないメタルマスクの開口面積S’が、
2/3×S ≦ S’ ≦ S−S×a/100
の範囲となるように設定されていることを特徴とする実装構造体の製造方法。 - 前記電子部品の最外周の接合部より中心部の接合部のはんだペーストの供給量を少なく調整することを特徴とする請求項1に記載の実装構造体の製造方法。
- 前記はんだペーストが、融点が240℃以下のはんだ粒子、熱硬化性樹脂バインダー、フラックス成分を含むことを特徴とする請求項1又は2に記載の実装構造体の製造方法。
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---|---|---|---|
JP2013257358A JP6471885B2 (ja) | 2013-12-12 | 2013-12-12 | 実装構造体の製造方法 |
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---|---|---|---|
JP2013257358A JP6471885B2 (ja) | 2013-12-12 | 2013-12-12 | 実装構造体の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018190792A Division JP2019009470A (ja) | 2018-10-09 | 2018-10-09 | 実装構造体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015115500A JP2015115500A (ja) | 2015-06-22 |
JP6471885B2 true JP6471885B2 (ja) | 2019-02-20 |
Family
ID=53529027
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---|---|---|---|
JP2013257358A Active JP6471885B2 (ja) | 2013-12-12 | 2013-12-12 | 実装構造体の製造方法 |
Country Status (1)
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JP (1) | JP6471885B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7410444B1 (ja) | 2023-03-31 | 2024-01-10 | 千住金属工業株式会社 | 電子装置の製造方法および電子装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174312A (ja) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | 半導体装置およびはんだバンプの形成方法 |
JP2003243818A (ja) * | 2002-02-15 | 2003-08-29 | Denso Corp | 半導体電子部品の実装方法 |
JP4134976B2 (ja) * | 2004-10-26 | 2008-08-20 | 松下電器産業株式会社 | 半田接合方法 |
JP2010232388A (ja) * | 2009-03-26 | 2010-10-14 | Panasonic Electric Works Co Ltd | 半導体パッケージ及び半導体部品の実装構造 |
JP2010283080A (ja) * | 2009-06-03 | 2010-12-16 | Fdk Module System Technology Corp | 電子部品の実装方法、およびソルダーマスクの設計方法 |
JP2012069772A (ja) * | 2010-09-24 | 2012-04-05 | Fujikura Ltd | 半導体装置およびその製造方法 |
JP5588287B2 (ja) * | 2010-09-27 | 2014-09-10 | パナソニック株式会社 | 熱硬化性樹脂組成物及び半導体部品実装基板 |
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