JP5621019B2 - 半導体部品の実装構造 - Google Patents
半導体部品の実装構造 Download PDFInfo
- Publication number
- JP5621019B2 JP5621019B2 JP2013146002A JP2013146002A JP5621019B2 JP 5621019 B2 JP5621019 B2 JP 5621019B2 JP 2013146002 A JP2013146002 A JP 2013146002A JP 2013146002 A JP2013146002 A JP 2013146002A JP 5621019 B2 JP5621019 B2 JP 5621019B2
- Authority
- JP
- Japan
- Prior art keywords
- thermosetting resin
- sealing material
- solder
- resin composition
- semiconductor component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
この式中の−X−は、−O−、−S−、−S−S−のうちのいずれかである。
この式中の−X−は、−O−、−S−、−S−S−のうちのいずれかである。すなわち、有機酸として、下記構造式(2)で示されるジグリコール酸、下記構造式(3)で示されるチオジグリコール酸、下記構造式(4)で示されるジチオジグリコール酸のうちの少なくとも一種を用いることができる。
HOOCH2C−S−CH2COOH …(3)
HOOCH2C−S−S−CH2COOH …(4)
また、3個のカルボキシル基を有する有機酸としては、1,2,3−ベンゼントリカルボン酸、クエン酸等を用いることができる。なお、有機酸が有するカルボキシル基の個数の上限は、特に限定されるものではないが、実質的には、4個程度である。
2 半導体部品
3 端子
4 回路基板
5 電極
6 接合部
7 はんだ部
8 樹脂硬化部
9 封止材
Claims (2)
- エポキシ樹脂を含む熱硬化性樹脂バインダー、はんだ粒子及びフラックス成分を含有する熱硬化性樹脂組成物を用いて半導体部品の端子と回路基板の電極とを接合する接合部を設けて形成された半導体部品の実装構造において、前記フラックス成分が下記構造式(1)で示される化合物であり、前記接合部が、前記はんだ粒子が溶融一体化したはんだ部と、前記はんだ部の周囲を被覆する樹脂硬化部とで形成されていると共に、フラックス成分を含有しない封止材が、前記接合部の周囲を封止していることを特徴とする半導体部品の実装構造。
HOOCH2C−X−CH2COOH…(1)
この式中の−X−は、−O−、−S−、−S−S−のうちのいずれかである。 - はんだ粒子及びフラックス成分を含有する熱硬化性樹脂組成物を用いて複数の回路基板の電極間を接合する接合部を設け、前記接合部が、前記はんだ粒子が溶融一体化したはんだ部と、前記はんだ部の周囲を被覆する樹脂硬化部とで形成されていると共に、フラックス成分を含有しない封止材が、前記接合部の周囲を封止していることを特徴とする請求項1に記載の半導体部品の実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013146002A JP5621019B2 (ja) | 2013-07-12 | 2013-07-12 | 半導体部品の実装構造 |
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---|---|---|---|
JP2013146002A JP5621019B2 (ja) | 2013-07-12 | 2013-07-12 | 半導体部品の実装構造 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010037823A Division JP5385822B2 (ja) | 2010-02-23 | 2010-02-23 | 半導体部品の実装方法 |
Publications (2)
Publication Number | Publication Date |
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JP2013219393A JP2013219393A (ja) | 2013-10-24 |
JP5621019B2 true JP5621019B2 (ja) | 2014-11-05 |
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JP2013146002A Active JP5621019B2 (ja) | 2013-07-12 | 2013-07-12 | 半導体部品の実装構造 |
Country Status (1)
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JP (1) | JP5621019B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6379635B2 (ja) | 2014-04-28 | 2018-08-29 | 日本電気株式会社 | 電力配分決定装置、制御方法、及びプログラム |
JPWO2018134860A1 (ja) * | 2017-01-17 | 2019-11-07 | パナソニックIpマネジメント株式会社 | 半導体実装品 |
JP6812919B2 (ja) * | 2017-07-12 | 2021-01-13 | 昭和電工マテリアルズ株式会社 | 半導体パッケージ |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003100810A (ja) * | 2001-09-27 | 2003-04-04 | Toshiba Corp | 半導体装置とその製造方法 |
JP2006152312A (ja) * | 2006-02-20 | 2006-06-15 | Tdk Corp | 封止材料、はんだ付け用フラックス、はんだぺースト、電子部品装置、電子回路モジュール及び電子回路装置 |
JP5032938B2 (ja) * | 2007-10-24 | 2012-09-26 | パナソニック株式会社 | 熱硬化性樹脂組成物及びその製造方法 |
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2013
- 2013-07-12 JP JP2013146002A patent/JP5621019B2/ja active Active
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