JP2020150146A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2020150146A
JP2020150146A JP2019046972A JP2019046972A JP2020150146A JP 2020150146 A JP2020150146 A JP 2020150146A JP 2019046972 A JP2019046972 A JP 2019046972A JP 2019046972 A JP2019046972 A JP 2019046972A JP 2020150146 A JP2020150146 A JP 2020150146A
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Japan
Prior art keywords
wiring
insulating layer
opening
layer
connection terminal
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JP2019046972A
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English (en)
Inventor
崇浩 森
Takahiro Mori
崇浩 森
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Kioxia Corp
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Kioxia Corp
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Publication date
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Priority to JP2019046972A priority Critical patent/JP2020150146A/ja
Priority to CN201910789328.9A priority patent/CN111696945B/zh
Priority to TW108130441A priority patent/TWI728438B/zh
Priority to US16/559,374 priority patent/US10985153B2/en
Publication of JP2020150146A publication Critical patent/JP2020150146A/ja
Pending legal-status Critical Current

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Abstract

【課題】プリント配線板の配線のクラックを防止する。【解決手段】半導体装置は、基板と、基板の上の配線層と、配線層の上の第１の絶縁層と、を備え、配線層が接続端子と前記接続端子に電気的に接続された配線とを有し、第１の絶縁層が接続端子および配線の一部を第１の絶縁層から露出させる開口と、開口の縁に設けられるとともに配線に重畳する凸部または凹部と、を有する、プリント配線板と、プリント配線板に搭載された半導体チップと、接続端子と半導体チップとを電気的に接続するボンディングワイヤと、半導体チップおよびボンディングワイヤを覆うとともに開口を埋める第２の絶縁層と、を具備する。【選択図】図１

Description

実施形態の発明は、半導体装置に関する。
近年、通信技術や情報処理技術の発達に伴い、メモリ等の半導体装置の小型化および高速化が要求されている。これに対応するため、複数の半導体チップを積層させた３次元構造を有する半導体パッケージの開発が進められている。
上記半導体パッケージは、例えばプリント配線板の上に半導体チップを搭載し、プリント配線板のボンディングパッドと半導体チップとをボンディングワイヤにより接続し、ダイアタッチフィルムにより半導体チップおよびボンディングワイヤを覆うことにより形成されるフィルムオンデバイス（ＦＯＤ）構造を有する。
特開２００３−０６９１６８号公報
実施形態の発明が解決しようとする課題は、プリント配線板の配線のクラックを防止することである。
実施形態の半導体装置は、基板と、基板の上の配線層と、配線層の上の第１の絶縁層と、を備え、配線層が接続端子と前記接続端子に電気的に接続された配線とを有し、第１の絶縁層が接続端子および配線の一部を第１の絶縁層から露出させる開口と、開口の縁に設けられるとともに配線に重畳する凸部または凹部と、を有する、プリント配線板と、プリント配線板に搭載された半導体チップと、接続端子と半導体チップとを電気的に接続するボンディングワイヤと、半導体チップおよびボンディングワイヤを覆うとともに開口を埋める第２の絶縁層と、を具備する。
プリント配線板の構造例を示す上面模式図である。 プリント配線板の構造例を示す上面模式図である。 半導体装置の構造例を示す上面模式図である。 半導体装置の構造例を示す断面模式図である。 半導体装置の構造例を示す断面模式図である。 プリント配線板の他の構造例を示す断面模式図である。 プリント配線板の他の構造例を示す断面模式図である。
以下、実施形態について、図面を参照して説明する。図面に記載された各構成要素の厚さと平面寸法との関係、各構成要素の厚さの比率等は現物と異なる場合がある。また、実施形態において、実質的に同一の構成要素には同一の符号を付し適宜説明を省略する。
実施形態の半導体装置に適用可能なプリント配線板の構造について図１および図２を参照して説明する。図１および図２はプリント配線板１の構造例を示す上面模式図であり、プリント配線板１のチップ搭載面のＸ軸とＸ軸に直交するＹ軸とを含むＸ−Ｙ平面の一部を示す。
プリント配線板１は、基板１０と、基板１０の上に設けられた配線層１１と、配線層１１の上に設けられた絶縁層１２と、を備える。基板１０の内部には、複数の内部配線層（図示せず）が形成されていてもよい。内部配線層は、配線層１１と電気的に接続していてもよい。
基板１０としては、例えばガラス基板、セラミック基板、ガラスエポキシ等の樹脂基板等を用いることができる。また、基板１０はフレキシブルであってもよい。
配線層１１は、接続端子１１ａと、接続端子１１ａに電気的に接続された配線１１ｂと、を有する。配線層１１は、例えば銅や銀を主成分とした金属膜または銅や銀を含む導電性ペーストを用い、必要に応じて表面にニッケルめっきや金めっき等を施すことにより形成される。
接続端子１１ａとしては、例えばボンディングパッドやランド等が挙げられる。複数の接続端子１１ａは、例えば基板１０の表面に並置され、それぞれが対応する配線１１ｂに電気的に接続される。
配線１１ｂは、接続端子１１ａの種類に応じて信号配線または電源配線としての機能を有する。複数の配線１１ｂは、基板１０の表面に並置される。なお、複数の配線１１ｂの一つは、図１および図２に示すように、複数の配線１１ｂの他の一つと異なる方向に延在していてもよい。
絶縁層１２としては、例えばソルダーレジストを用いることができる。絶縁層１２は、開口１２０と、凸部１２１と、凹部１２２と、平坦部１２３と、を有する。凸部１２１、凹部１２２、および平坦部１２３は、開口１２０の縁に設けられる。開口１２０、凸部１２１、凹部１２２、および平坦部１２３は、例えば絶縁層１２の一部をエッチングすることにより形成される。なお、絶縁層１２は、凸部１２１および凹部１２２の一つを有していなくてもよい。
開口１２０は、接続端子１１ａおよび配線１１ｂの一部を絶縁層１２から露出させる。なお、開口１２０に面する角の少なくとも一つ、凸部１２１の角の少なくとも一つ、または凹部１２２の角の少なくとも一つは、図２に示すように曲面Ｒを有していてもよい。また、図１および図２において開口１２０の縁は、配線１１ｂの延在方向と垂直な方向（Ｙ軸方向）に沿って延在しているが、これに限定されず、配線１１ｂの延在方向と交差する方向に沿って延在していればよい。
凸部１２１は、例えば開口１２０の縁から開口１２０の内側に向かって突出するように延在する。凸部１２１は、複数の配線１１ｂの一つに重畳する。凸部１２１は、隣接する２以上の配線１１ｂに重畳していてもよい。凸部１２１の幅は、例えば配線１１ｂの幅よりも広い。
凹部１２２は、例えば開口１２０の縁から開口１２０の外側に向かって窪むように延在する。凹部１２２は、複数の配線１１ｂの一つに重畳する。凹部１２２は、隣接する２以上の配線１１ｂに重畳していてもよい。凹部１２２の幅は、例えば配線１１ｂの幅よりも広い。
平坦部１２３は、例えば凸部１２１または凹部１２２に隣接する。平坦部１２３は、図１に示すように凸部１２１の間や凹部１２２の間にも設けられ、隣接する配線１１ｂの間の領域に重畳する。
次に、上記プリント配線板を用いた半導体装置の構造例について説明する。図３は半導体装置のＸ−Ｙ平面を示す図である。図４は半導体装置のＹ−Ｚ断面を示す図である。図５は半導体装置のＸ−Ｚ断面を示す図である。
半導体装置は、プリント配線板１と、半導体チップ２と、ボンディングワイヤ３と、絶縁層４と、半導体チップ６と、ボンディングワイヤ７と、封止樹脂層８と、を具備する。
プリント配線板１は、第１の面に設けられた配線層１１と、配線層１１の上の絶縁層１２と、第２の面に設けられるとともに基板１０を貫通するビア１３を介して接続端子１１ａに電気的に接続され、グランド端子、信号端子、または電源端子としての機能を有する導電層１４と、導電層１４の一部を露出させる開口を有するソルダーレジスト等の絶縁層１５と、を備える。
半導体チップ２としては、例えばメモリコントローラに用いられる半導体チップが挙げられる。半導体チップ２は、プリント配線板１の第１の面に搭載され、ダイアタッチフィルム等の有機接着層を介して絶縁層１２の上に設けられている。半導体チップ２は表面に電極を有する。
ボンディングワイヤ３は、配線層１１の接続端子１１ａの一つと半導体チップ２の電極とを電気的に接続する。ボンディングワイヤ３としては、例えば金ワイヤ、銀ワイヤ、銅ワイヤ等が挙げられる。銅ワイヤの表面がパラジウム膜により覆われていてもよい。
絶縁層４は、半導体チップ２およびボンディングワイヤ３を覆う。絶縁層４としては、例えばダイアタッチフィルムを用いることができる。
半導体チップ６としては、例えばＮＡＮＤ型フラッシュメモリ等のメモリ素子に用いられる半導体チップが挙げられる。半導体チップ６は、ダイアタッチフィルム等の有機接着層を介して絶縁層４の上に搭載される。半導体チップ６は、電極を有し、電極を露出させるように多段に積層されている。多段に積層された半導体チップ６は、ダイアタッチフィルム等の有機接着層を介して順に接着されている。多段に積層された半導体チップ６の電極は、ボンディングワイヤ７により配線層１１の接続端子１１ａの一つと電気的に接続されている。半導体チップ６は、配線層１１の接続端子１１ａおよび配線１１ｂを介して半導体チップ２に電気的に接続される。
ボンディングワイヤ７は、配線層１１の接続端子１１ａの一つと半導体チップ６の電極とを電気的に接続する。ボンディングワイヤ７としては、ボンディングワイヤ３に適用可能なワイヤを用いることができる。
封止樹脂層８は、半導体チップ６を封止する。封止樹脂層８は、ＳｉＯ２等の無機充填材を含有する。また、無機充填材は、ＳｉＯ２に加え、例えば水酸化アルミニウム、炭酸カルシウム、酸化アルミニウム、窒化ホウ素、酸化チタン、またはチタン酸バリウム等を含んでいてもよい。無機充填材は、例えば粒状であり、封止樹脂層８の粘度や硬度等を調整する機能を有する。封止樹脂層８中の無機充填材の含有量は、例えば６０％以上９０％以下である。封止樹脂層８としては、例えば無機充填材と絶縁性の有機樹脂材料との混合物を用いることができる。有機樹脂材料としては、例えばエポキシ樹脂が挙げられる。なお、無機充填材は、封止樹脂層８の表面に露出していてもよい。
図１および図２に示す開口１２０、凸部１２１、凹部１２２、および平坦部１２３は、例えば配線層１１の接続端子１１ａの一つとボンディングワイヤ３との接続部に形成される。これに限定されず、例えば配線層１１の接続端子１１ａの一つとボンディングワイヤ７との接続部に開口１２０を形成してもよい。
配線層１１の接続端子１１ａの一つとボンディングワイヤ３との接続部に開口１２０を形成する場合、開口１２０は、絶縁層４により埋められる。絶縁層４の線膨張係数が絶縁層１２の線膨張係数よりも大きい場合、開口１２０により露出する配線１１ｂには温度変化により応力が加わりやすい。例えば絶縁層１２に用いられるソルダーレジストの線膨張係数は、約３０ｐｐｍ／℃であり、絶縁層４に用いられるダイアタッチフィルムの線膨張係数は、約１００ｐｐｍ／℃である。
応力は、開口１２０の縁に沿って集中しやすい。特に、配線基板としてプリント配線板を用いる場合は応力が加わりやすいため、例えば開口１２０の縁に沿って配線１１ｂにクラックが発生し、配線１１ｂが断線する場合がある。
これに対し、開口１２０の縁に凸部１２１または凹部１２２を設けることにより、開口１２０の縁に沿って加わる応力を分散し、配線１１ｂと開口１２０の縁との交差角によらず配線１１ｂに加わる応力を低減することができる。よって、配線１１ｂのクラックを防止することができる。
さらに、凸部１２１および凹部１２２とともに平坦部１２３を設けることにより絶縁層１２の剥がれを抑制することができる。仮に、開口１２０の縁の全てに凸部１２１や凹部１２２を設けると絶縁層４との接触面積が大き過ぎるため絶縁層１２が基板１０から剥がれやすくなる。
図４において、プリント配線板１に設けられ、ボンディングワイヤ７が接続するパッドを露出する開口が形成されている。この開口においては、開口１２０のように、凸部１２１、凹部１２２を有せず、縁にすべて平坦部１２３のみを有していてもよい。なぜならば、絶縁層１２を形成するソルダーレジスト等の線膨張係数と、封止樹脂層８との線膨張整数との差は、ソルダーレジスト等の線膨張係数と、絶縁層４を形成するダイアタッチフィルムとの線膨張係数の差よりも小さい場合がある。ボンディングワイヤ７に電気的に接続される接続端子１１ａを露出する開口は封止樹脂層８により埋められる。このため、線膨張係数の差による応力が小さく、配線１１ｂにクラックが発生しにくいからである。
プリント配線板１の構成は、図１および図２に示す構成に限定されない。図６および図７はプリント配線板１の他の構造例を示す上面模式図であり、プリント配線板１のＸ−Ｙ平面の一部を示す。
図６および図７に示すプリント配線板１は、図１に示すプリント配線板１と比較して、配線層１１がダミー配線１１ｃをさらに有する点が異なる。図１に示すプリント配線板１の構成要素と同じ部分については上記説明を適宜援用することができる。また、図１に示すプリント配線板１の構成要素と異なる部分については適宜組み合わせることができる。
ダミー配線１１ｃは、配線１１ｂとともに基板１０の表面に並置され、例えば基板１０の第１の方向（例えばＸ軸方向）に沿って並置される。ダミー配線１１ｃは、接続端子１１ａや配線１１ｂと電気的に接続または分離する。ダミー配線１１ｃは、例えば２以上の配線１１ｂの間に設けられていてもよい。ダミー配線１１ｃの一部は、開口１２０により絶縁層１２から露出する。なお、図７に示すように２以上のダミー配線１１ｃが電気的に接続され、接続端子１１ａと電気的に分離していてもよい。
ダミー配線１１ｃを設けることにより、開口１２０における配線密度（配線１１ｂおよびダミー配線１１ｃの間隔）の均一性を高めることができる。これにより、配線１１ｂへの応力集中をさらに抑制することができる。よって、配線１１ｂのクラックを防止することができる。
ダミー配線１１ｃの延在方向の端部は、凸部１２１の延在方向の端部から第１の方向と交差する第２の方向（例えばＹ方向）に沿って離れていることが好ましい。ダミー配線１１ｃの延在方向の端部が凸部１２１の延在方向の端部と第２の方向に沿って揃っていると例えば絶縁層４により開口１２０を埋める場合に配線１１ｂやダミー配線１１ｃに応力が集中しやすくなる。
上記実施形態は例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施し得るものであり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると共に、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１…プリント配線板、２…半導体チップ、３…ボンディングワイヤ、４…絶縁層、６…半導体チップ、７…ボンディングワイヤ、８…封止樹脂層、１０…基板、１１…配線層、１１ａ…接続端子、１１ｂ…配線、１１ｃ…ダミー配線、１２…絶縁層、１２０…開口、１２１…凸部、１２２…凹部、１２３…平坦部。

Claims (6)

  1. 基板と、前記基板の上の配線層と、前記配線層の上の第１の絶縁層と、を備え、前記配線層が接続端子と前記接続端子に電気的に接続された配線とを有し、前記第１の絶縁層が前記接続端子および前記配線の一部を前記第１の絶縁層から露出させる開口と、前記開口の縁に設けられるとともに前記配線に重畳する凸部または凹部と、を有する、プリント配線板と、
    前記プリント配線板に搭載された半導体チップと、
    前記接続端子と前記半導体チップとを電気的に接続するボンディングワイヤと、
    前記半導体チップおよび前記ボンディングワイヤを覆うとともに前記開口を埋める第２の絶縁層と、
    を具備する、半導体装置。
  2. 前記第２の絶縁層の線膨張係数は、前記第１の絶縁層の線膨張係数よりも大きい、請求項１に記載の半導体装置。
  3. 前記第１の絶縁層は、ソルダーレジストであり、
    前記第２の絶縁層は、ダイアタッチフィルムである、請求項１または請求項２に記載の半導体装置。
  4. 前記第１の絶縁層は、前記開口の縁に設けられた平坦部をさらに有する、請求項１ないし請求項３のいずれか一項に記載の半導体装置。
  5. 前記配線層は、ダミー配線をさらに有し、
    前記開口は、前記ダミー配線の一部を露出させる、請求項１ないし請求項４のいずれか一項に記載の半導体装置。
  6. 前記第１の絶縁層は、前記凸部を有し、
    前記配線および前記ダミー配線は、前記基板の第１の方向に沿って並置され、
    前記ダミー配線の端部は、前記凸部の端部から前記第１の方向と交差する第２の方向に沿って離間する、請求項５に記載の半導体装置。
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JP2003069168A (ja) * 2001-08-28 2003-03-07 Nagoya Industrial Science Research Inst プリント配線基板又は集積回路における回路パターン及びこれを備えたプリント配線基板と集積回路
US7309244B2 (en) * 2003-06-12 2007-12-18 Jsr Corporation Anisotropic conductive connector device and production method therefor and circuit device inspection device
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