CN111696945B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN111696945B
CN111696945B CN201910789328.9A CN201910789328A CN111696945B CN 111696945 B CN111696945 B CN 111696945B CN 201910789328 A CN201910789328 A CN 201910789328A CN 111696945 B CN111696945 B CN 111696945B
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Prior art keywords
wiring
insulating layer
connection terminal
opening
semiconductor chip
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CN111696945A (zh
Inventor
森崇浩
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Kioxia Corp
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Kioxia Corp
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Abstract

根据一个实施方式，半导体装置具备：印刷布线板，具有衬底、衬底之上的布线层、及布线层之上的第1绝缘层，布线层具有连接端子、及与所述连接端子电性连接的布线，第1绝缘层具有使连接端子及布线的一部分从第1绝缘层露出的开口、及设置在开口的边缘并且与布线重叠的凸部或凹部；半导体芯片，装载在印刷布线板上；接合线，将连接端子与半导体芯片电性连接；及第2绝缘层，将半导体芯片及接合线覆盖，并且将开口填满。

Description

半导体装置
[相关申请案]
本申请案以2019年3月14日提出申请的现有的日本专利申请案第2019-046972号的优先权利益为基础，且寻求该利益，其内容整体通过援引而包含于此。
技术领域
此处说明的多种形式的实施方式概括而言涉及一种半导体装置。
背景技术
近年来，随着通信技术或信息处理技术发展，存储器等半导体装置被要求小型化及高速化。为应对此要求，具有将多个半导体芯片积层而成的3维构造的半导体封装体不断推进开发。
所述半导体封装体具有片上薄膜(FOD)构造，该片上薄膜(FOD)构造是通过例如将半导体芯片装载在印刷布线板之上，利用接合线将印刷布线板的接合垫与半导体芯片连接，利用芯片粘结膜将半导体芯片及接合线覆盖而形成。
发明内容
本发明的实施方式提供一种可防止印刷布线板的布线裂痕的半导体装置。
根据实施方式的半导体装置装置，具备印刷布线板，具有衬底、衬底之上的布线层、及布线层之上的第1绝缘层，布线层具有连接端子、及与所述连接端子电性连接的布线，第1绝缘层具有使连接端子及布线的一部分从第1绝缘层露出的开口、及设置在开口的边缘并且与布线重叠的凸部或凹部；半导体芯片，装载在印刷布线板上；接合线，将连接端子与半导体芯片电性连接；及第2绝缘层，将半导体芯片及接合线覆盖，并且将开口填满。
根据如上所述的构成，可防止印刷布线板的布线裂痕。
附图说明
图1是表示印刷布线板的构造例的俯视示意图。
图2是表示印刷布线板的构造例的俯视示意图。
图3是表示半导体装置的构造例的俯视示意图。
图4是表示半导体装置的构造例的剖视示意图。
图5是表示半导体装置的构造例的剖视示意图。
图6是表示印刷布线板的其他构造例的剖视示意图。
图7是表示印刷布线板的其他构造例的剖视示意图。
具体实施方式
以下，对于实施方式，参照附图进行说明。附图中记载的各构成要素的厚度与平面尺寸的关系、各构成要素的厚度比率等存在与实物不同的情况。而且，在实施方式中，对于实质上相同的构成要素标注同一符号，而适当省略说明。
对于可适用于实施方式的半导体装置的印刷布线板的构造，参照图1及图2进行说明。图1及图2是表示印刷布线板1的构造例的俯视示意图，且表示包含印刷布线板1的芯片装载面的X轴及与X轴正交的Y轴的X-Y平面的一部分。
印刷布线板1具备衬底10、设置在衬底10之上的布线层11、及设置在布线层11之上的绝缘层12。在衬底10的内部，也可形成多个内部布线层(未图示)。内部布线层也可与布线层11电性连接。
作为衬底10，可使用例如玻璃衬底、陶瓷衬底、玻璃环氧树脂等树脂衬底等。而且，衬底10也可为挠性。
布线层11具有作为第1连接端子的连接端子11a、及与连接端子11a电性连接的布线11b。布线层11是通过使用例如以铜或银为主成分的金属膜、或者含铜或银的导电膏，视需要对表面实施镀镍或镀金等而形成。
作为连接端子11a，可列举例如接合垫或焊盘等。多个连接端子11a例如并置在衬底10的表面，且与各自所对应的布线11b电性连接。
布线11b根据连接端子11a的种类，具有作为信号布线或电源布线的功能。多个布线11b并置在衬底10的表面上。另外，多个布线11b中的一个也可如图1及图2所示，在与多个布线11b中的其他一个不同的方向上延伸。
可将例如阻焊膜用作作为第1绝缘层的绝缘层12。绝缘层12具有作为第1开口的开口120、凸部121、凹部122、及平坦部123。凸部121、凹部122、及平坦部123设置在开口120的边缘。开口120、凸部121、凹部122、及平坦部123通过例如刻蚀绝缘层12的一部分而形成。另外，绝缘层12也可不具有凸部121及凹部122中的一个。
开口120使连接端子11a及布线11b的一部分从绝缘层12露出。另外，面向开口120的角的至少一个、凸部121的角的至少一个、或凹部122的角的至少一个也可如图2所示具有曲面R。而且，在图1及图2中，开口120的边缘是沿着与布线11b的延伸方向垂直的方向(Y轴方向)延伸，但不限于此，沿着与布线11b的延伸方向交叉的方向延伸即可。
凸部121是例如以从开口120的边缘朝向开口120的内侧突出的方式延伸。凸部121与多个布线11b中的一个重叠。凸部121也可与相邻的2个以上布线11b重叠。凸部121的宽度大于例如布线11b的宽度。
凹部122是例如以从开口120的边缘朝向开口120的外侧凹陷的方式延伸。凹部122与多个布线11b中的一个重叠。凹部122也可与相邻的2个以上布线11b重叠。凹部122的宽度大于例如布线11b的宽度。
平坦部123与例如凸部121或凹部122相邻。平坦部123也如图1所示设置在凸部121之间或凹部122之间，且与相邻的布线11b之间的区域重叠。
其次，对使用所述印刷布线板的半导体装置的构造例进行说明。图3是表示半导体装置的X-Y平面的图。图4是表示半导体装置的Y-Z截面的图。图5是表示半导体装置的X-Z截面的图。
半导体装置具有印刷布线板1、作为第1半导体芯片的半导体芯片2、作为第1接合线的接合线3、作为第2绝缘层的绝缘层4、作为第2半导体芯片的半导体芯片6、作为第2接合线的接合线7、及作为第3绝缘层的密封树脂层8。
印刷布线板1具有：布线层11，设置在第1面；布线层11之上的绝缘层12；导电层14，设置在第2面，并且经由将衬底10贯通的通孔13而与连接端子11a电性连接，且具有作为接地端子、信号端子、或电源端子的功能；及阻焊膜等绝缘层15，具有使导电层14的一部分露出的开口。
作为半导体芯片2，可列举例如用于存储控制器的半导体芯片。半导体芯片2装载在印刷布线板1的第1面，且隔着芯片粘结膜等有机黏着层，设置在绝缘层12之上。半导体芯片2在表面具有电极。
接合线3将布线层11的连接端子11a的一个与半导体芯片2的电极电性连接。作为接合线3，可列举例如金线、银线、铜线等。铜线的表面也可由钯膜覆盖。
绝缘层4覆盖半导体芯片2及接合线3。作为绝缘层4，可使用例如芯片粘结膜。
作为半导体芯片6，可列举例如用于NAND型闪速存储器等存储元件的半导体芯片。半导体芯片6隔着芯片粘结膜等有机黏着层，装载在绝缘层4之上。半导体芯片6具有电极，且以使电极露出的方式多级地积层。多级地积层而成的半导体芯片6隔着芯片粘结膜等有机黏着层依次地黏着。多级地积层而成的半导体芯片6的电极利用接合线7而与布线层11的一个连接端子11a电性连接。半导体芯片6经由布线层11的连接端子11a及布线11b而与半导体芯片2电性连接。
接合线7将布线层11的一个连接端子11a与半导体芯片6的电极电性连接。作为接合线7，可使用能够适用于接合线3的线。
密封树脂层8将半导体芯片6密封。密封树脂层8含有SiO2等无机填料。而且，无机填料除了可含有SiO2以外，也可含有例如氢氧化铝、碳酸钙、氧化铝、氮化硼、氧化钛、或钛酸钡等。无机填料为例如粒状，具有调整密封树脂层8的粘度或硬度等的功能。密封树脂层8中无机填料的含量为例如60％以上90％以下。作为密封树脂层8，可使用例如无机填料与绝缘性有机树脂材料的混合物。作为有机树脂材料，可列举例如环氧树脂。另外，无机填料也可在密封树脂层8的表面露出。
图1及图2中所示的开口120、凸部121、凹部122、及平坦部123形成在例如布线层11的一个连接端子11a与接合线3的连接部。但不限于此，也可在例如布线层11的一个连接端子11a与接合线7的连接部形成开口120。
当在布线层11的一个连接端子11a与接合线3的连接部形成开口120时，开口120被绝缘层4填满。在绝缘层4的线膨胀系数大于绝缘层12的线膨胀系数的情况下，因开口120而露出的布线11b中，容易因温度变化而受到应力。例如绝缘层12中使用的阻焊膜的线膨胀系数约为30ppm/℃，绝缘层4中使用的芯片粘结膜的线膨胀系数约为100ppm/℃。
应力容易沿着开口120的边缘而集中。尤其，在将印刷布线板用作布线衬底的情况下，容易受到应力，因此，存在例如沿着开口120的边缘在布线11b中产生裂痕，导致布线11b断线的情况。
相对于此，可通过在开口120的边缘设置凸部121或凹部122，而将沿着开口120的边缘所受的应力分散，不依赖布线11b与开口120的边缘的交叉角而减少布线11b中所受的应力。由此，便可防止布线11b的裂痕。
进而，凸部121及凹部122均可通过设置平坦部123而抑制绝缘层12剥落。假设在开口120的所有边缘设置凸部121或凹部122，则与绝缘层4的接触面积过大，因此，绝缘层12容易从衬底10剥落。
在图4中，形成有设置在印刷布线板1，使接合线7所连接的作为第2连接端子的焊垫16露出的作为第2开口的开口17。在该开口中，也可如开口120般不具有凸部121及凹部122，在边缘均仅具有平坦部123。其原因在于，存在形成绝缘层12的阻焊膜等的线膨胀系数与密封树脂层8的线膨胀系数之差小于阻焊膜等的线膨胀系数与形成绝缘层4的芯片粘结膜的线膨胀系数之差的情况。使与接合线7电性连接的焊垫16露出的开口17被密封树脂层8填满。因而，其原因在于线膨胀系数之差引起的应力较小，布线11b中难以产生裂痕。例如，密封树脂层8的线膨胀系数也可为约5ppm/℃～约50ppm/℃。尤其，约15ppm/℃～约30ppm因与形成绝缘层12的阻焊膜等的线膨胀系数之差变小而较为合适。
印刷布线板1的构成不限于图1及图2中所示的构成。图6及图7是表示印刷布线板1的其他构造例的俯视示意图，且示出印刷布线板1的X-Y平面的一部分。
图6及图7中所示的印刷布线板1与图1中所示的印刷布线板1相比，布线层11更具有虚设布线11c的方面不同。对于与图1中所示的印刷布线板1的构成要素相同的部分，可适当引用所述说明。而且，对于与图1中所示的印刷布线板1的构成要素不同的部分，可适当进行组合。
虚设布线11c与布线11b一同地并置在衬底10的表面，例如沿着衬底10的第1方向(例如X轴方向)并置。虚设布线11c与连接端子11a或布线11b电性连接或分离。虚设布线11c也可设置在例如2个以上的布线11b之间。虚设布线11c的一部分通过开口120从绝缘层12露出。另外，如图7所示，也可将2个以上的虚设布线11c电性连接，而与连接端子11a电性分离。而且，虚设布线也可连接于电源。虚设布线也可接地。虚设布线也可为电浮状态。而且，虚设布线中也可连接或不连接作为虚设的接合线。
通过设置虚设布线11c，可提升开口120中的布线密度(布线11b及虚设布线11c的间隔)的均匀性。由此，可进而抑制对布线11b的应力集中。因此，可防止布线11b的裂痕。
虚设布线11c的延伸方向的端部优选从凸部121的延伸方向的端部沿着与第1方向交叉的第2方向(例如Y方向)分离。若虚设布线11c的延伸方向的端部沿着第2方向与凸部121的延伸方向的端部对齐，则在例如利用绝缘层4填满开口120的情况下，应力容易集中于布线11b或虚设布线11c。
所述实施方式是作为示例而提示，并非意图限定发明范围。该等新颖的实施方式可以其他各种方式实施，且在不脱离发明主旨的范围内可进行各种省略、置换、及变更。该等实施方式或其变化包含于发明的范围或主旨中，并且也包含于专利申请范围中记载的发明及其均等的范围内。

Claims (10)

1.一种半导体装置，具备：
印刷布线板，具有衬底、所述衬底之上的布线层、及所述布线层之上的第1绝缘层，所述布线层具有第1连接端子、与所述第1连接端子电性连接的第1布线、第2连接端子、及与所述第2连接端子电性连接的第2布线，所述第1绝缘层具有使所述第1连接端子、所述第1布线的一部分、所述第2连接端子、及所述第2布线的一部分从所述第1绝缘层露出的第1开口、及设置在所述第1开口的边缘并且与所述第1布线重叠的凸部及与所述第2布线重叠的凹部；
第1半导体芯片，装载在所述印刷布线板上；
第1接合线，将所述第1连接端子与所述第1半导体芯片电性连接；
第2接合线，将所述第2连接端子与所述第1半导体芯片电性连接；及
第2绝缘层，将所述第1半导体芯片、所述第1接合线及所述第2接合线覆盖，并且将所述第1开口填满。
2.一种半导体装置，具备：
印刷布线板，具有衬底、所述衬底之上的布线层、及所述布线层之上的第1绝缘层，所述布线层具有第1连接端子、与所述第1连接端子电性连接的布线、及虚设布线，所述第1绝缘层具有使所述第1连接端子、所述布线的一部分、及所述虚设布线从所述第1绝缘层露出的第1开口、及设置在所述第1开口的边缘并且与所述布线重叠的凸部或凹部；
第1半导体芯片，装载在所述印刷布线板上；
第1接合线，将所述第1连接端子与所述第1半导体芯片电性连接；及
第2绝缘层，将所述第1半导体芯片及所述第1接合线覆盖，并且将所述第1开口填满。
3.根据权利要求1或2所述的半导体装置，其中所述第2绝缘层的线膨胀系数大于所述第1绝缘层的线膨胀系数。
4.根据权利要求1或2所述的半导体装置，其中所述第1绝缘层为阻焊膜，且
所述第2绝缘层为芯片粘结膜。
5.根据权利要求1或2所述的半导体装置，其中所述第1绝缘层更具有设置在所述开口的边缘的平坦部。
6.根据权利要求1或2所述的半导体装置，其中所述凸部在端部具有曲面。
7.根据权利要求1或2所述的半导体装置，其具备：
第2半导体芯片，设置在所述第2绝缘层；
第3接合线，将经由设置在所述衬底的第2开口从所述第1绝缘层露出的第3连接端子与所述第2半导体芯片连接；及
第3绝缘层，覆盖所述第2半导体芯片与所述第3接合线。
8.根据权利要求7所述的半导体装置，其中所述第2绝缘层与所述第1绝缘层的线膨胀系数之差大于所述第1绝缘层与所述第3绝缘层的线膨胀系数之差。
9.根据权利要求8所述的半导体装置，其中所述第2开口仅具有平坦部。
10.根据权利要求2所述的半导体装置，其中所述第1绝缘层具有所述凸部，
所述布线及所述虚设布线沿着所述衬底的第1方向并置，
所述虚设布线的端部从所述凸部的端部沿着与所述第1方向交叉的第2方向分离。
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