CN101930960B - 集成电路芯片封装和形成方法 - Google Patents

集成电路芯片封装和形成方法 Download PDF

Info

Publication number
CN101930960B
CN101930960B CN201010212275.3A CN201010212275A CN101930960B CN 101930960 B CN101930960 B CN 101930960B CN 201010212275 A CN201010212275 A CN 201010212275A CN 101930960 B CN101930960 B CN 101930960B
Authority
CN
China
Prior art keywords
solder element
plane
electrology characteristic
pcb
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010212275.3A
Other languages
English (en)
Other versions
CN101930960A (zh
Inventor
J·R·贝胡恩
D·B·斯通
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN101930960A publication Critical patent/CN101930960A/zh
Application granted granted Critical
Publication of CN101930960B publication Critical patent/CN101930960B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19015—Structure including thin film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明涉及集成电路芯片封装和形成方法。一种结构包括：焊料元件，其用于电学耦合集成电路(IC)芯片封装的衬底和印刷电路板(PCB)；以及第一电学特性改变、基本上平面的构件，其位于所述衬底的接合衬垫和所述PCB的接合衬垫中的至少一个与所述焊料元件之间。在另一实施例中，所述第一电学特性改变、基本上平面的构件可被应用于IC芯片与封装衬底之间的焊料元件。

Description

集成电路芯片封装和形成方法
技术领域
本公开一般而言涉及集成电路(IC)封装，更具体而言，涉及包括电学特性改变、平面的构件的结构，其中该构件具有IC芯片封装的焊料元件。
背景技术
在集成电路(IC)封装中，通过对层叠衬底上的接合衬垫(landing pad)施加焊膏，在焊膏上设置焊料球，以及回流所产生的结构，从而形成球栅阵列(BGA)连接。可选地，焊料元件可以设置在已被助焊剂涂覆的接合衬垫上，并且在接合衬垫上回流焊料球。在这些IC封装中，高速差分对信号(例如，以10-Gb/s操作的HSS)时常需要直流(DC)滤波器，以允许高速交流(AC)信号通过而没有有害影响，例如DC噪声，该DC噪声来自系统或来自与在不同电势下操作的其他模块的通信。典型地，DC滤波是通过信号线的串联设置的电容器(d-帽)，其通过离散表面安装技术而设置。然而，这种类型的滤波不总是可能的，因为其需要可能无法获得的特定空间量，导致差分耦合的中断，并且需要沿Z方向的额外的布线，这增加了耦合噪声问题。
发明内容
本公开的第一方面提供一种结构，包括：焊料元件，其用于电学耦合集成电路(IC)芯片封装的衬底和印刷电路板(PCB)；以及第一电学特性改变、基本上平面的构件，其位于所述衬底的接合衬垫和所述PCB的接合衬垫中的一个与所述焊料元件之间。
本公开的第二方面提供一种集成电路(IC)芯片封装，包括：位于衬底上的IC芯片；从所述IC芯片延伸的引线；印刷电路板(PCB)；以及电学特性改变、基本上平面的构件，其将所述引线电学耦合到所述PCB。
本公开的第三方面提供一种方法，包括：提供用于安装IC芯片的衬底，所述衬底包括在其表面上的第一连接器阵列；提供印刷电路板(PCB)，所述PCB包括在其表面上的第二连接器阵列；在所述第一和第二阵列的每一个连接器上产生接合衬垫；在所述第一和第二阵列中的选定的一个之上产生掩模，所述掩模包括选定数目的开口，每一个开口暴露接合衬垫；在每一个开口中和各接合衬垫上形成电学特性改变、基本上平面的构件；去除所述掩模；在所述第一和第二阵列的所述选定的一个之上产生球栅阵列(BGA)；以及使用所述球栅阵列电学耦合所述衬底和所述PCB。
本发明的第四方面提供一种结构，包括：焊料元件，其用于电学耦合集成电路(IC)芯片和其封装衬底；以及第一电学特性改变、基本上平面的构件，其位于所述IC芯片的接合衬垫和所述封装衬底的接合衬垫中的至少一个与所述焊料元件之间。
本公开的示例性的各方面被设计为解决这里描述的问题和/或未讨论的其他问题。
附图说明
通过以下结合附图进行的对本公开的各方面的详细描述，将更容易理解本公开的这些和其他方面，这些附图示出了本公开的各实施例，其中：
图1示出了被耦合到包括根据本发明的实施例的结构的PCB的IC芯片封装的局部截面图；
图2示出了被耦合到包括根据可选实施例的结构的PCB的IC芯片封装的局部截面图；
图3示出了根据本发明的实施例的电学特性改变、平面的构件的截面图；
图4示出了根据可选实施例的电学特性改变、平面的构件的截面图；
图5示出了被耦合到包括根据可选实施例的结构的PCB的IC芯片封装的局部截面图；
图6示出了用于选择性地产生用以形成构件的开口的在IC芯片封装衬底或PCB之上的掩模；
图7示出了用于选择性地产生用以形成构件的开口的在IC芯片封装衬底和PCB之上的掩模对；
图8示出了被耦合到包括根据可选实施例的结构的PCB的IC芯片封装的局部截面图；以及
图9示出了被耦合到包括根据可选实施例的结构的其衬底封装的IC芯片的局部截面图。
应注意，本公开的附图未按比例绘制。这些附图旨在仅仅示出本公开的典型方面，因此不应被视为限制本公开的范围。在附图中，相似的标号代表附图之间相似的要素。
具体实施方式
如上所述，本公开提供一种结构，其集成电路(IC)芯片封装和/或印刷电路板(PCB)的接合衬垫与焊料元件之间包括电学特性改变、平面的构件。图1示出了结构100的实施例，结构100包括用于电学耦合IC芯片封装106的衬底104和PCB 108的焊料元件102。本领域技术人员将理解，为了清楚起见而简化了附图，并且这些附图中没有包括例如底填料、热界面材料、芯片盖、粘合剂、表面安装器件、堆积层、焊料掩模等等。另外，为了清楚起见，仅仅示出了一个焊料元件102，但典型地可以提供焊料元件的阵列(参见图6-7)。焊料元件102可包括任何焊料连接，例如焊料球(未示出)、焊料柱、柱、鸥形翼、引线等等。衬底104包括任何现在已知或将来发展的层叠材料、陶瓷或典型地用于安装和按比例增加IC芯片110的其他材料。衬底104的所示出的一些细节包括芯112、多个镀敷通孔(PTH)114和布线116。PCB 108包括任何平板，其在互连过孔导电路线(轨迹，未示出)的层中保持电学部件。
衬底104或PCB 108的希望从其中引出电互连的每一个区域具有通过各自的接合衬垫120C、120P而与其耦合的焊料元件102。接合衬垫120C表示使用与IC芯片封装106的互连，接合衬垫120P表示与PCB 108的互连。每一个接合衬垫130C、130P分别包括作为焊料元件102与衬底104或PCB 108中的电路线的焊料可润湿衬垫。接合衬垫130C、130P也称为球限制冶金(BLM)，并且，例如，其包括诸如铬或钛钨(TiW)的粘合层以及诸如铜(Cu)或镍(Ni)的焊料可回流层。焊料元件102包括有助于减少在锡(Sn)与接合衬垫120中的铜之间的反应的铅/锡(Pb/Sn)合金(或无铅合金，例如SnCu、SnAgCu)。接合衬垫120的尺寸被配置为提供可靠的机械、电学和热学稳定性。
除了上述常规特征之外，结构100还包括位于衬底104的接合衬垫120C和PCB 108的接合衬垫120P中的至少一个与焊料元件102之间的电学特性改变、基本上平面的构件130C、130P。图1示出了其中在衬底104和PCB 108二者与焊料元件102之间都使用电学特性改变、基本上平面的构件130P、130C(以下简称为“构件”)的实施例。也就是，第一构件130C设置在焊料元件102与衬底104的接合衬垫120C之间，第二构件130P设置在焊料元件102与PCB 108的接合衬垫120P之间。图2示出了其中仅仅在焊料元件102与PCB 108之间使用构件130P的实施例。应理解，同样可以使用构件130C(图1)而不使用构件130P。在任何情况下，构件130C、130P在衬底104或PCB 108的外表面132的外部。
构件130P、130C基本上为平面的，以最小化垂直间隔需要量。构件130P、130C改变的电学特性可依赖于构件的结构而变化。构件130C和/或130P包括能够获得希望的电学效果的任何形式的材料，例如，单一材料或多层材料。在一个实施例中，电学特性改变、平面的构件130C和/或130P包括电容器。在该情况下，如图3所示，构件130P和/或130C包括通过电介质142而与第二金属层144分隔的第一金属层140。金属层140、144包括诸如但不限于铜、镍、铝等等的导体，并且电介质142包括诸如但不限于氮化硅、二氧化硅、聚酰亚胺等等的绝缘体。在一个实施例中，电介质142延伸超出第一金属层140和第二金属层144的边缘146，以防止在两个层之间的短路。然而，这不是在所有情况下都必需的。关于电容器，构件130C、130P用作DC滤波器，允许AC信号通过而过滤出低频(DC)波动。在另一个实施例中，平面的构件130C和/或130P包括电阻器或电感器。在该情况下，如图4所示，构件130C、130P包括可以产生希望的电学效果的诸如绝缘体的材料的一个或多个层150，绝缘体包括但不限于：氮化硅、二氧化硅、聚酰亚胺等等。此外，如仅仅图4所示，每一个构件130C、130P包括在与接合衬垫120交界的表面上以及与焊料元件102交界的表面上的焊料可润湿层152。每一个焊料可润湿表面被设置为不延伸到构件的边缘。
图5示出了其中多个焊料元件的焊料元件102中的至少一个包括构件130C和/或130P(全部示出为包括二者)的可选实施例。然而，在该情况下，在衬底104和PCB 108中的至少一个中在焊料元件102之间制造电连接160，以在两个或多个焊料元件102与构件130P、130C之间产生并联连接。以该方式，可以并联耦合构件130P、130C，以获得希望的电学特性改变。应理解，可以以该方式耦合任何数目的焊料元件102。
在一个实施例中，球栅阵列中的每一个焊料元件102包括一个或多个构件130C、130P。(如果使用球栅阵列，其可以采取任何现在已知的或将来发展的形式，例如倒装芯片塑性球栅阵列(FC-PBGA)、增强的塑性球栅阵列(EPBGA)、陶瓷球栅阵列(CBGA)、陶瓷柱栅阵列(CCGA)、或者包括诸如鸥形翼的线接合封装、细间距球栅阵列(FBGA)、包含诸如
Figure BSA00000161886300051
封装的产品的芯片级封装等等的其他形式)。可选地，虽然采用了多个焊料元件102，但在另一实施例中，焊料元件102中的仅仅选定的一个包括构件130C、130P。在该情况下，如图6和7所示，可以设置用于保持IC芯片110(在该阶段，IC芯片110可以或可以不被耦合)的衬底104，在这里，衬底104包括在其表面162上的第一连接器阵列(在接合衬垫120之下)。类似地，PCB 108可包括在其表面164上的第二连接器阵列(在接合衬垫120之下)。可以以任何现在已知的或将来发展的方式在第一和第二阵列的每一个连接器上形成接合衬垫120。如图6所示，然后，在第一和第二阵列的选定的一个(如所示的衬底104)之上形成掩模170，该掩模包括选定数目的开口172(与掩模的描绘阴影不同，没有全部标注)，每一个开口172暴露接合衬垫120。掩模170可以包括任何现在已知的或将来发展的掩模材料。然后，使用任何现在已知的或将来发展的工艺在每一个开口172中以及各自的接合衬垫120上形成构件130P、130C，这些技术为例如材料的沉积、材料的粘附、焊接、减蚀等等。然后，使用任何现在已知的或将来发展的蚀刻工艺(例如反应离子蚀刻)，去除掩模170。然后，以已知的方式在第一和第二阵列的选定的一个之上形成BGA(焊料元件102)，并且使用该球栅阵列电学耦合衬底104和PCB 108。以该方式，设计者可以将任何电学特性改变应用于芯片封装106与PCB108之间的希望的电路径。
在图7所示的可选实施例中，可以在第一和第二阵列(即，衬底104和PCB 108)二者之上产生掩模170，每一个掩模包括选定数目的开口172，每一个开口暴露接合衬垫120。然后，在每一个开口172中形成构件130C、130P(图1-2)，并且去除两个掩模。在任一实施例中，可以在耦合衬底104和PCB 108之前测试构件130C、130P。
在另一可选实施例中，如图8所示，在阵列内的所有焊料元件102可以在其上形成有构件130C和/或构件130P。在该情况下，选定的焊料元件可以具有围绕其构件130C、130P或者在如所示设置二者的情况下130C、130P的组的短路(short)180。以该方式，构件130C、130P变为电学透明的。可以以任何现在已知的或将来发展的方式，例如，通过使焊料元件102具有足够的体积以延伸围绕一个或两个构件、通过热处理以引起贯穿构件的短路等等，使构件130C、130P短路。该工艺可减轻制造复杂性并提供成本优势。
如在此所述的，无论是否被使用，构件130P、130C没有给芯片封装110带来物理设计差异。另外，可以在将衬底提交到IC芯片110的接合之前以及在接合到PCB 108之前利用构件130C原位测试衬底104。该物理结构的附加厚度极小，从而，无论接合衬垫具有构件130C和/或130P还是省略接合衬垫，现有的焊料元件和焊料体积的使用不受影响。
参考图9，示例出可以与上述实施例分离地或组合地使用的另一实施例。在该实施例中，将上述教导应用于在IC芯片110与封装衬底104之间的焊料元件202。也就是，在IC芯片110的硅与封装衬底104之间，焊料元件202采取例如可控塌陷芯片连接(C4)阵列的形式，该阵列包括多个焊料元件。在该情况下，结构200包括用于电耦合IC芯片110和封装衬底104的焊料元件202、以及位于IC芯片110的接合衬垫220U和封装衬底104的接合衬垫220L中的至少一个与焊料元件202之间的第一电学特性改变、基本上平面的构件230U、230L。图9示出了两个构件230U、230L，但可以采用仅仅一个。与上面一样，构件230U、230L可采取电容器、电阻器或电感器的形式。如果构件230U、230L包括电容器，则它们可包括通过电介质而与第二金属层分隔的第一金属层，如关于图3-4所述。
在制造集成电路芯片封装时使用上述结构和方法。可以将上述教导应用于单芯片封装(例如塑性载体，其引线被固定到母板或其他更高级的载体)或多芯片封装(例如陶瓷载体，其具有一个或两个表面互连或掩埋互连)。在任何情况下，该芯片可以接着与其他芯片、分立电路元件和/或其他信号处理器件集成而作为(a)中间产品(例如母板)或(b)最终产品的一部分。该最终产品可以为包括集成电路芯片的任何产品，其范围从玩具和其他低端应用到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
以上附图示出了根据本公开的几个实施例的一些有关处理。关于这一点，每个附图或流程图中的块或附图的顺序代表与所述方法的实施例相关的处理。还应注意，在一些可选实施方式中，附图或块中标注的动作可以不按该图所标注的顺序发生，例如，实际上，可以按基本上当前的或相反的顺序执行，这依赖于所涉及的动作。并且，本领域技术人员将意识到，可以添加用于描述处理的附加的块。
在此使用的术语仅仅用于描述特定实施例的目的，并不旨在限制本公开。在此使用的单数形式“一”、“一个”和“该”旨在还包括复数形式，除非上下文另有说明。此外，应理解，在该说明书中使用的术语“包括”和/或“包含”规定所述特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其组合的存在。
在下面的权利要求中的所有方式或步骤加功能要素的对应结构、材料、动作和等价物旨在包括用于与具体地要求保护的其他要求保护的要素组合地执行功能的任何结构、材料或动作。已为了示例和说明的目的而给出了本公开的说明书，但其不旨在穷举性的或以所公开的形式局限于本公开。对于本领域普通技术人员而言，许多修改和变化是显而易见的而不脱离本公开的精神和范围。为了最好地解释本公开的原理和实际应用，并且为了能够使本领域其他普通技术人员能够理解本公开的具有适于所预期的特定用途的各种修改的各种实施例，选择和描述了这些实施例。

Claims (20)

1.一种用于集成电路芯片封装的结构，包括：
焊料元件，其用于电学耦合集成电路芯片封装的衬底和印刷电路板；以及
电学特性改变、平面的构件，以最小化垂直间隔需要量，其位于所述衬底的接合衬垫和所述印刷电路板的接合衬垫中的至少一个与所述焊料元件之间并被用作直流滤波器，其中所述电学特性改变、平面的构件包括电容器。
2.根据权利要求1的结构，所述电容器包括通过电介质而与第二金属层分隔的第一金属层。
3.根据权利要求2的结构，其中所述电介质延伸超出所述第一金属层和所述第二金属层的边缘。
4.根据权利要求1的结构，其中所述焊料元件是包括多个焊料元件的球栅阵列的一部分。
5.根据权利要求1的结构，包括位于所述衬底的所述接合衬垫与所述焊料元件之间的第一电学特性改变、平面的构件；以及
位于所述印刷电路板的所述接合衬垫与所述焊料元件之间的第二电学特性改变、平面的构件。
6.根据权利要求1的结构，其中所述焊料元件包括多个焊料元件，所述焊料元件中的至少一个包括位于所述衬底的所述接合衬垫和所述印刷电路板的所述接合衬垫中的至少一个与各自的焊料元件之间的所述电学特性改变、平面的构件。
7.根据权利要求6的结构，其中所述多个焊料元件中的每一个包括位于所述衬底的所述接合衬垫与所述焊料元件之间的第一电学特性改变、平面的构件；以及
位于所述印刷电路板的所述接合衬垫与所述焊料元件之间的第二电学特性改变、平面的构件，并且
还包括通过至少一个选定的焊料元件的所述第一和第二电学特性改变、平面的构件的短路，以使所述构件电学透明。
8.根据权利要求6的结构，其中包括所述电学特性改变、平面的构件的所述焊料元件中的至少一个包括多个焊料元件，所述多个焊料元件包括电学特性改变、平面的构件，并且还包括在所述衬底和所述印刷电路板中的至少一个中的电连接，以在所述焊料元件中的一个或多个与所述多个电学特性改变、平面的构件之间产生并联连接。
9.根据权利要求1的结构，其中所述电学特性改变、平面的构件在所述衬底或所述印刷电路板的外表面的外部。
10.根据权利要求1的结构，其中所述电学特性改变、平面的构件包括在与所述接合衬垫交界的表面上以及与所述焊料元件交界的表面上的焊料可润湿层，每一个焊料可润湿层被设置为不延伸到所述构件的边缘。
11.根据权利要求1的结构，其中所述焊料元件是倒装芯片塑性球栅阵列、增强的塑性球栅阵列、陶瓷球栅阵列、陶瓷柱栅阵列、或细间距球栅阵列中的一个的一部分。
12.一种集成电路芯片封装，包括：
位于衬底上的集成电路芯片；
从所述集成电路芯片延伸的引线；
印刷电路板；以及
电学特性改变、平面的构件，以最小化垂直间隔需要量，其将所述引线电学耦合到所述印刷电路板并被用作直流滤波器，其中所述电学特性改变、平面的构件包括电容器。
13.根据权利要求12的集成电路芯片封装，其中所述电容器包括通过电介质而与第二金属层分隔的第一金属层，所述电介质延伸超出所述第一金属层和所述第二金属层的边缘。
14.根据权利要求12的集成电路芯片封装，其中所述电学特性改变、平面的构件在所述衬底或所述印刷电路板的外表面的外部。
15.一种集成电路封装方法，包括：
提供用于安装集成电路芯片的衬底，所述衬底包括在其表面上的第一连接器阵列；
提供印刷电路板，所述印刷电路板包括在其表面上的第二连接器阵列；
在所述第一和第二连接器阵列的每一个连接器上产生接合衬垫；
在所述第一和第二连接器阵列中至少一个之上产生掩模，所述掩模包括选定数目的开口，每一个开口暴露接合衬垫；
在每一个开口中和各自的接合衬垫上形成电学特性改变、平面的构件，其中，所述电学特性改变、平面的构件包括电容器；
去除所述掩模；
在所述第一和第二连接器阵列的选定的一个之上产生球栅阵列；以及
使用所述球栅阵列电学耦合所述衬底和所述印刷电路板。
16.根据权利要求15的方法，其中：
所述掩模产生包括在所述第一和第二连接器阵列之上产生掩模，每一个掩模包括选定数目的开口，每一个开口暴露接合衬垫；
所述形成包括在每一个开口中形成电学特性改变、平面的构件；以及
所述去除包括去除两个掩模。
17.一种用于集成电路芯片封装的结构，包括：
焊料元件，其用于电学耦合集成电路芯片和其封装衬底；以及
电学特性改变、平面的构件，以最小化垂直间隔需要量，其位于所述集成电路芯片的接合衬垫和所述封装衬底的接合衬垫中的至少一个与所述焊料元件之间并被用作直流滤波器，其中所述电学特性改变、平面的构件包括电容器。
18.根据权利要求17的结构，其中所述电容器包括通过电介质而与第二金属层分隔的第一金属层。
19.根据权利要求17的结构，其中所述焊料元件是包括多个焊料元件的可控塌陷芯片连接阵列的一部分。
20.根据权利要求17的结构，包括位于所述集成电路芯片与所述焊料元件之间的第一电学特性改变、平面的构件以及位于所述焊料元件与所述封装衬底之间的第二电学特性改变、平面的构件。
CN201010212275.3A 2009-06-25 2010-06-23 集成电路芯片封装和形成方法 Active CN101930960B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/491,438 2009-06-25
US12/491,438 US8044512B2 (en) 2009-06-25 2009-06-25 Electrical property altering, planar member with solder element in IC chip package

Publications (2)

Publication Number Publication Date
CN101930960A CN101930960A (zh) 2010-12-29
CN101930960B true CN101930960B (zh) 2014-05-28

Family

ID=43370032

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010212275.3A Active CN101930960B (zh) 2009-06-25 2010-06-23 集成电路芯片封装和形成方法

Country Status (4)

Country Link
US (1) US8044512B2 (zh)
JP (1) JP5704840B2 (zh)
KR (1) KR20100138753A (zh)
CN (1) CN101930960B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147923A1 (en) * 2009-12-21 2011-06-23 Jiun Hann Sir Surface Mounting Integrated Circuit Components
US9711879B2 (en) * 2014-08-05 2017-07-18 Infinera Corporation Clamp interconnect
CN106257661B (zh) * 2015-06-16 2019-03-05 华为技术有限公司 芯片封装载板、芯片和电路板
US10477684B2 (en) * 2015-09-25 2019-11-12 Intel Corporation Apparatus, system, and method including a bridge device for interfacing a package device with a substrate
CN112243312A (zh) * 2020-10-16 2021-01-19 恒为科技（上海）股份有限公司 一种pcb板及其制备方法
CN113113375B (zh) * 2021-04-09 2024-05-28 中国科学技术大学 一种用于毫米波频段芯片封装的垂直互连结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369913A (zh) * 2001-02-15 2002-09-18 矽统科技股份有限公司 降低电气杂讯的球阵列封装装置

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787718A (en) 1972-08-08 1974-01-22 Sondell Res Deve Co Spherical electronic components
JP2502581B2 (ja) * 1987-04-09 1996-05-29 松下電器産業株式会社 半導体素子の突起電極形成方法
US5367437A (en) 1993-04-06 1994-11-22 Sundstrand Corporation Multiple layer capacitor mounting arrangement
US5551627A (en) * 1994-09-29 1996-09-03 Motorola, Inc. Alloy solder connect assembly and method of connection
JPH10242411A (ja) 1996-10-18 1998-09-11 Sony Corp 半導体メモリセルのキャパシタ構造及びその作製方法
US6336262B1 (en) 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US5808853A (en) 1996-10-31 1998-09-15 International Business Machines Corporation Capacitor with multi-level interconnection technology
US6297559B1 (en) * 1997-07-10 2001-10-02 International Business Machines Corporation Structure, materials, and applications of ball grid array interconnections
US6005777A (en) 1998-11-10 1999-12-21 Cts Corporation Ball grid array capacitor
GB2344550A (en) * 1998-12-09 2000-06-14 Ibm Pad design for electronic package
US6812718B1 (en) * 1999-05-27 2004-11-02 Nanonexus, Inc. Massively parallel interface for electronic circuits
JP2001185649A (ja) * 1999-12-27 2001-07-06 Shinko Electric Ind Co Ltd 回路基板、半導体装置、その製造方法および回路基板用材料片
JP2001291637A (ja) 2000-04-10 2001-10-19 Shinko Electric Ind Co Ltd 球状キャパシタと該キャパシタの製造方法と球状キャパシタの実装構造と配線基板と該配線基板の製造方法
US6858941B2 (en) * 2000-12-07 2005-02-22 International Business Machines Corporation Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
JP3671351B2 (ja) * 2001-05-23 2005-07-13 カシオ計算機株式会社 半導体装置並びにその製造方法および実装方法
US7189595B2 (en) * 2001-05-31 2007-03-13 International Business Machines Corporation Method of manufacture of silicon based package and devices manufactured thereby
JP3860000B2 (ja) * 2001-09-07 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
US6808955B2 (en) * 2001-11-02 2004-10-26 Intel Corporation Method of fabricating an integrated circuit that seals a MEMS device within a cavity
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
JP4554152B2 (ja) * 2002-12-19 2010-09-29 株式会社半導体エネルギー研究所 半導体チップの作製方法
SG120123A1 (en) * 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
US7218007B2 (en) * 2004-09-28 2007-05-15 Intel Corporation Underfill material to reduce ball limiting metallurgy delamination and cracking potential in semiconductor devices
JP4632870B2 (ja) * 2005-06-10 2011-02-16 Ｎｅｃシステムテクノロジー株式会社 Ｌｓｉパッケージ及び回路基板
US20070075430A1 (en) * 2005-09-30 2007-04-05 Daewoong Suh Solder joint intermetallic compounds with improved ductility and toughness
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
SG155793A1 (en) * 2008-03-19 2009-10-29 Micron Technology Inc Upgradeable and repairable semiconductor packages and methods
JP5386481B2 (ja) * 2008-05-09 2014-01-15 パナソニック株式会社 半導体装置、およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369913A (zh) * 2001-02-15 2002-09-18 矽统科技股份有限公司 降低电气杂讯的球阵列封装装置

Also Published As

Publication number Publication date
JP5704840B2 (ja) 2015-04-22
CN101930960A (zh) 2010-12-29
US8044512B2 (en) 2011-10-25
US20100327405A1 (en) 2010-12-30
JP2011009742A (ja) 2011-01-13
KR20100138753A (ko) 2010-12-31

Similar Documents

Publication Publication Date Title
US7350298B2 (en) Method for fabricating circuit board with conductive structure
CN105390472B (zh) 用于嵌入式半导体器件封装的电气互连结构及其制造方法
TW444236B (en) Bumpless flip chip assembly with strips and via-fill
CN110233112A (zh) 电子封装件及其制法
CN101930960B (zh) 集成电路芯片封装和形成方法
US20150043190A1 (en) Embedded packaging with preformed vias
US20080257595A1 (en) Packaging substrate and method for manufacturing the same
CN106033752B (zh) 半导体衬底及具有半导体衬底的半导体封装结构
US20140367850A1 (en) Stacked package and method of fabricating the same
US20120037411A1 (en) Packaging substrate having embedded passive component and fabrication method thereof
CN109390306A (zh) 电子封装件
JP2009105139A (ja) 配線基板及びその製造方法と半導体装置
CN107154388B (zh) 半导体封装件及其制造方法
US20090102050A1 (en) Solder ball disposing surface structure of package substrate
US9508677B2 (en) Chip package assembly and manufacturing method thereof
KR20240017393A (ko) 반도체 장치 및 이의 제조 방법
US20130258623A1 (en) Package structure having embedded electronic element and fabrication method thereof
WO2014204771A1 (en) Method of forming a microelectronic assembly by plating metal connectors after assemblying first and second components and corresponding device
KR101211724B1 (ko) 반도체 패키지 및 그 제조방법
CN102774804A (zh) 具微机电元件的封装件及其制造方法
CN104779176A (zh) 嵌埋有晶片的封装结构的制法
US20110061907A1 (en) Printed circuit board and method of manufacturing the same
US20110220403A1 (en) Side packaged type printed circuit board
CN113539850A (zh) 一种系统级封装方法及封装结构
CN104124180A (zh) 芯片封装结构的制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171113

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171113

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right