TWI695450B - 半導體裝置及其製作方法 - Google Patents

半導體裝置及其製作方法 Download PDF

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TWI695450B
TWI695450B TW105135349A TW105135349A TWI695450B TW I695450 B TWI695450 B TW I695450B TW 105135349 A TW105135349 A TW 105135349A TW 105135349 A TW105135349 A TW 105135349A TW I695450 B TWI695450 B TW I695450B
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Taiwan
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dielectric
conductive
semiconductor device
semiconductor
substrate
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TW105135349A
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TW201735231A (zh
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陳承先
黃育智
陳玉芬
潘國龍
鄭余任
李明機
普翰屏
張緯森
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台灣積體電路製造股份有限公司
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Abstract

本揭露之實施例揭示一種半導體裝置，其包含：半導體基板；導電墊，其位於該半導體基板上；及第一介電質，其位於該半導體基板上方。該半導體裝置亦包含：導電層，其放置於該第一介電質中；及第二介電質，其放置於該導電層上。在該半導體裝置中，該導電層之至少一部分自該第一介電質及該第二介電質暴露。該半導體裝置進一步包含導電跡線，該導電跡線部分地位於該第二介電質上方且與該導電層之該經暴露部分接觸。在該半導體裝置中，該導電跡線在一端處連接至該導電墊。

Description

半導體裝置及其製作方法
本揭露涉及一種半導體裝置及一種製作半導體裝置之方法。
涉及半導體裝置之電子裝備係我們日常生活不可或缺的。隨著電子技術之進步，電子裝備變得較複雜且涉及用於執行所要多功能性之較大量之積體電路。因此，電子裝備之製作包含越來越多之裝配及處理步驟以及用於生產電子裝備中之半導體裝置之材料。因此，存在對簡化生產步驟、增加生產效率及降低對每一電子裝備之相關聯製作成本之持續需求。 在製作半導體裝置之操作期間，半導體裝置裝配有包含具有熱性質差異之各種材料之若干個整合式組件。如此，在半導體裝置之固化之後，整合式組件呈不期望組態。不期望組態將導致半導體裝置之良率損失、組件之間的不良接合性、裂縫形成、組件之脫層等。此外，半導體裝置之組件包含數量有限且因此成本高之各種金屬材料。組件之不期望組態及半導體裝置之良率損失將進一步加劇材料浪費且因此製作成本將增加。 由於涉及具有不同材料之不同組件且半導體裝置之製作操作之複雜性增加，因此存在修改半導體裝置之結構並改良製作操作之較多挑戰。如此，存在對改良用於製作半導體之方法及解決以上缺陷之持續需求。
在某些實施例中，一種半導體裝置包含：半導體基板；導電墊，其位於該半導體基板上；及第一介電質，其位於該半導體基板上方。該半導體裝置亦包含：導電層，其放置於該第一介電質中；及第二介電質，其放置於該導電層上。在該半導體裝置中，該導電層之至少一部分自該第一介電質及該第二介電質暴露。該半導體裝置進一步包含導電跡線，該導電跡線部分地位於該第二介電質上方且與該導電層之該經暴露部分接觸。在該半導體裝置中，該導電跡線在一端處連接至該導電墊。 在某些實施例中，一種半導體裝置包含：半導體基板；導電墊，其位於該半導體基板上；及介電質，其位於該半導體基板上方。該半導體裝置亦包含模塑料，該模塑料環繞該半導體基板、該導電墊及該介電質。在該半導體裝置中，該模塑料包括自該模塑料與該半導體基板之間的界面凹陷之拐角。 在某些實施例中，一種製作半導體裝置之方法包含：提供基板；將導電跡線放置於基板上方；及將介電質放置於該導電跡線上。該方法進一步包含：提供半導體晶粒且將該半導體晶粒翻轉倒置以將該半導體晶粒附接至該基板；及移除半導體基板以暴露該導電跡線。
以下揭露提供用於實施所提供標的物之不同構件之諸多不同實施例或實例。下文闡述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且並非意欲為限制性的。舉例而言，在以下說明中第一構件在第二構件上方或該第二構件上形成可包含其中第一構件與第二構件直接接觸地形成之實施例且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件與第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複參考編號及/或字母。此重複係出於簡單及清晰目的且並非本質上指示所論述之各種實施例及/或組態之間的關係。 此外，可在本文中為易於闡述而使用空間相對術語(諸如「下面」、「下方」、「下部」、「上面」、「上部」及諸如此類)來闡述一個元件或構件與另一元件或構件之關係，如各圖中所圖解說明。該等空間相對術語意欲囊括在使用或操作中之裝置之除圖中所繪示之定向之外的不同定向。設備可以其他方式定向(旋轉90度或以其他定向)且可因此同樣地理解本文中所使用之空間相對描述語。 在本揭露中，提供具有用於實現佈線區域減小及較佳佈線能力之創新堆疊互連件之半導體裝置。在本揭露中，半導體組件包含以圓環形狀或C形狀設計之堆疊互連件。圓環形狀或C形狀互連件經提出以增加在精細間距扇出封裝中之導電跡線佈線之可行性。藉由本揭露，可達成佈線區域減小及較佳佈線能力。 在本揭露中，導電跡線經組態以沿著膜堆疊之凹槽佈線。膜堆疊可為複合介電質結構且內部包含某些互連導電跡線。導電跡線在一端處連接至導電墊且延伸至複合介電質結構上方。在導電跡線之另一端上，導電凸塊或UBM連接於其中。導電跡線與複合介電質內部之互連導電跡線之一部分接觸，使得在互連導電跡線與導電墊之間形成電連接。 圖1係半導體裝置100之實施例。半導體裝置100包含半導體基板102。在某些實施例中，半導體基板102包含半導體材料(諸如矽)且在半導體基板102內製造有藉由各種操作(諸如光微影、蝕刻、沈積、鍍覆等)產生之預定功能電路。在某些實施例中，半導體基板102藉由機械或雷射刀片自矽晶圓單粒化。在某些實施例中，半導體基板102呈四邊形、矩形或正方形形狀。 圖1A係圖1中之半導體裝置100之一部分100a之放大視圖。半導體基板102包含表面102b且導電墊102a放置於表面102b上。在某些實施例中，導電墊102a與半導體基板102外部之電路電連接，使得半導體基板102內部之電路透過導電墊102a與半導體基板102外部之電路電連接。在某些實施例中，導電墊102a經組態以用於透過附接於導電墊102a上之導電跡線與導電凸塊電耦合，使得半導體基板102內部之電路透過導電跡線自導電墊102a至導電凸塊地與半導體基板102外部之電路連接。在某些實施例中，導電墊102a包含金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。 在某些實施例中，鈍化層103放置於半導體基板102之表面102b上方且部分地覆蓋導電墊102a。在某些實施例中，鈍化層103環繞導電墊102a。導電墊102a之一部分自鈍化層103中之凹槽103a暴露。在某些實施例中，鈍化層103部分地覆蓋導電墊102a之頂部表面102c。鈍化層103經組態以用於為半導體基板102提供電絕緣及濕氣防護，使得半導體基板102與周圍環境隔離。在某些實施例中，用介電質材料(諸如旋塗玻璃(SOG)、氧化矽、氮氧化矽、氮化矽或諸如此類)形成鈍化層103。在某些實施例中，利用氣相沈積或旋塗製程形成鈍化層103。 在某些實施例中，介電質105放置於鈍化層103上方。介電質105放置於鈍化層103之頂部表面103b上。在某些實施例中，介電質105包含聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗銲劑(SR)、ABF膜及諸如此類。鈍化層103由介電質105部分地覆蓋。然而，鈍化層103之一部分透過介電質105中之凹槽105a自介電質105暴露。介電質105中之凹槽105a與鈍化層103中之凹槽103a實質上對準，使得導電跡線108能夠沿著介電質105中之凹槽105a行進且進一步向下行進至鈍化層103中之凹槽103a。導電跡線108著陸於導電墊102a之一部分上，其中該部分透過凹槽103a自鈍化層103暴露。在某些實施例中，導電跡線108沿著凹槽103a及凹槽105a保形地佈線。在某些實施例中，凹槽105a具有寬度W2 且寬度W2 等於或大於凹槽103a之寬度W1 。 除凹槽105a之外，導電跡線108亦沿著介電質105之另一部分行進。如圖1A中所展示，導電跡線108亦沿著表面105e佈線，該表面實質上配置成正交於凹槽105a之側壁。表面105e係和鈍化層103與介電質105之間的界面相對之平面。 導電層106實質上接近於表面105e而放置，表面105e係介電質105與介電質107之間的界面。在某些實施例中，導電層106和介電質105與鈍化層103之間的界面間隔開預定距離。在某些實施例中，該預定距離大於0。導電層106由介電質105部分地環繞但具有自介電質105暴露之至少一側。導電層106放置於與導電墊102a不同之層級處且平行於導電墊102a。導電層106與導電墊102a之間的隔離至少由鈍化層103及介電質105組成。鈍化層103與介電質105之間的界面位於導電層106與導電墊102a之間。 導電層106之一側不被介電質105覆蓋或環繞而由放置於介電質105及鈍化層103上方之介電質107部分地覆蓋。在某些實施例中，介電質107包含聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗銲劑(SR)、ABF膜及諸如此類。導電層106之一部分106e透過介電質107中之凹槽107a自介電質107暴露。導電層106之經暴露部分106e位於導電跡線108之行進路徑處。導電層106之經暴露部分106e亦接近於介電質105之拐角，其中該拐角供導電跡線108行進通過。導電跡線108電連接至導電層106之經暴露部分。在某些實施例中，與導電跡線108連接之經暴露部分與表面105e實質上共面。透過導電跡線108，導電層106電連接至導電墊102a。 導電層106具有平行於導電墊102a之兩個側。平行側中之一個平行側(106f)面對鈍化層103與介電質105之間的界面且與介電質105介接。另一平行側106s背對鈍化層103與介電質105之間的界面但與介電質107介接。在某些實施例中，另一平行側106s與介電質107接觸。與導電跡線108連接之經暴露部分106e位於背對鈍化層103與介電質105之間的界面之平行側處。 導電跡線108行進穿過經暴露部分106e且進一步沿著凹槽107a之側壁佈線。在某些實施例中，導電跡線108沿著凹槽107a之側壁佈線且進一步彎曲至不同方向。導電跡線108之一部分沿著介電質107之表面行進，其中該表面實質上平行於導電層106。 導電層106及導電跡線108兩者皆可組態為重佈層(RDL)或鈍化後互連件(post passivation interconnect) (PPI)。由於導電跡線108之一部分伸展至導電層106上面，因此導電跡線108亦經組態以連接至凸塊下金屬(UBM)或導電凸塊。導電跡線108之一部分亦組態為導電層106與導電墊102a之間的互連件。導電跡線108之一端連接至導電墊102a，接著向上延伸且沿著凹槽103a、凹槽105a及凹槽107a之輪廓佈線。在延伸跨度中，導電跡線108將其他層間RDL (諸如導電層106)與導電墊102a電耦合。 透過導電跡線108，可節省用於放置導電層106與導電墊102a之間的中間通路之佈局區域。導電跡線108可同時組態為頂部層級RDL及用以耦合頂部層級RDL與導電墊102a之間的導電層之互連件。 模塑料104環繞半導體基板102、鈍化層103及介電質105。在某些實施例中，模塑物104毗鄰於半導體基板102之側壁102d而放置。在某些實施例中，模塑物104毗鄰於鈍化層103之側壁103d及介電質105之側壁105d而放置。在某些實施例中，介電質105之頂部表面105b與模塑物104之頂部表面104a實質上共面。在某些實施例中，模塑物104之拐角104b呈臺階式組態。拐角104b凹陷遠離模塑物104與半導體基板102之間的界面104c。 在某些實施例中，介電質105進一步橫向延伸且延伸跨越界面104c。介電質105之一部分105c安置於模塑物104上方。模塑物104包含各種材料，舉例而言環氧樹脂、酚系硬化劑、二氧化矽、觸媒、色素、脫模劑及諸如此類中之一或多者。用於形成模塑料之材料具有高導熱率、低濕氣吸收率、高撓曲強度(在板安裝溫度下)或此等之組合。 在某些實施例中，介電質109放置於導電跡線108上方。在某些實施例中，介電質109包含用於接納導電材料(諸如銅等)之凹槽109a。在某些實施例中，介電質109包含聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗銲劑(SR)、ABF膜及諸如此類。介電質107可透過導電跡線108部分地暴露且與介電質109接觸。 導電跡線108由介電質109部分地覆蓋，該介電質經設計以使導電跡線108與濕氣或反應隔離。然而，導電跡線108在介電質107上之至少一部分透過介電質109中之凹槽109a自介電質109暴露。介電質109使凹槽109a暴露導電跡線108之一部分以便提供用於接納凸塊下金屬(UBM) 110之頂部表面108a。導電凸塊115放置於UBM 110上。在某些實施例中，用金、銀、銅、鎳、鎢、鋁、鈀及/或其合金形成UBM 110。在某些實施例中，凸塊下金屬(UBM)係選用構件，使得導電凸塊115直接放置於導電跡線108上。 仍參考圖1A，半導體裝置100中之導電構件可分類成三個不同層級。將半導體基板102作為最底部層級之參考以便較佳地理解以下說明。導電墊102a位於半導體基板102上方且稱作第一層級導體。導電層106稱作第二層級導體。在某些實施例中，在介電質105或鈍化層103內不存在通路或互連件。換言之，第一層級導體與第二層級導體之間的介電質複合物不含導電構件。導電跡線108組態為部分第三層級導體且亦經延伸以與第一層級導體及第二層級導體接觸。第一層級導體(導電墊102a)與第二層級導體(導電層106)透過第一層級導體與第二層級導體之間的介電質外部之導體電連接。 第三層級導體之一部分沿著鈍化層103中之凹槽103a之形態佈線。在某些實施例中，第三層級導體係作為翼(wing)且自導電墊102a對稱地橫跨。介電質複合物(介電質105及介電質107)共同具有包含呈臺階式組態之拐角之凹槽且第三層級導體之一部分沿著臺階式拐角佈線。 圖1B展示半導體裝置100之一部分。上部剖面圖包含導電墊102a及導電層106。省略導電跡線108以便簡化圖解說明。在剖面圖之下圖解說明導電墊102a及導電層106之俯視圖。在圖1B中，RA 定義為凹槽103a之直徑、RB 定義為凹槽105a之直徑且RC 定義為導電層106之直徑。在某些實施例中，直徑RA 小於直徑RB ，且直徑RB 小於直徑RC 。在某些實施例中，導電墊102a之頂部表面102c之一部分透過凹槽103a及凹槽105a暴露。自俯視圖角度來看，導電層106組態為環路且導電墊102a位於該環路內部。在某些實施例中，自俯視圖角度來看，導電層106之佈局不與導電墊102a重疊。 圖2展示半導體裝置300之另一實施例。半導體裝置300包含類似於圖1B中之半導體100之結構，使得在本文中不對利用相同數字標記來指示之元件之細節重複。圍繞導電墊102a之導電層106不呈閉合環路組態。自俯視圖角度(圖中之下部部分)來看，導電層106呈具有一端開口之C形狀。在剖面圖中，導電層106僅展示在對應導電墊102a之一側中。 圖3係放置於導電跡線108之下的導電層之俯視圖。導電層包含數個C形環106b。每一C形環106b由對應導電跡線108部分地覆蓋。每一C形環106b亦連接至延伸部分106c。在某些實施例中，延伸部分106c係延展之RDL。 圖4A至圖4K包含製作圖1中之半導體裝置100之方法之操作。該方法包含操作201、202、203、204、205、206、207、208、209及210，如對應圖式中所展示。 在操作201中，提供基板400作為載體或支撐件。將犧牲膜401放置於基板400上(如圖4A中)。在操作202中，將導電層106放置於犧牲膜401上(如圖4B中)。導電層106之形成可包含圖案化光阻劑且接著將導電材料電鍍至光阻劑中之經圖案化孔或溝槽中。在形成經圖案化導電層106之後，將光阻劑剝除。 在操作203中，將介電質105放置於犧牲膜401及導電層106上(如圖4C中)。介電質之形成可包含用以在導電層106及犧牲膜401上方生長毯覆膜之某些沈積製程。引入圖案化製程以移除過多介電質材料以形成經圖案化介電質105。 在操作204中，提供半導體晶粒402，且將半導體晶粒402翻轉倒置並附接至基板400 (如圖4D中)。主動表面(與半導體基板102之背側相對)面朝導電層106。在某些實施例中，半導體晶粒402包含半導體基板102、半導體基板102之表面102b上之導電墊102a及表面102b上之鈍化層103。在某些實施例中，將基板400翻轉倒置並附接至半導體晶粒402。在某些實施例中，半導體晶粒402係自晶圓單粒化之半導體晶片。在放置於基板400上方之前，半導體晶粒402可經歷一系列晶圓層級半導體操作。舉例而言，提供半導體晶圓且在半導體基板中形成諸如CMOS、二極體等裝置。 在某些實施例中，透過介電質至介電質接合而將鈍化層103接合至介電質105。在某些實施例中，介電質105之邊緣不與半導體基板102之邊緣對準。如圖4D中，半導體晶粒402之側壁邊緣102d不與介電質105之外部邊緣對準。在某些實施例中，將半導體晶粒402附接於一位置中，使得介電質105之一部分105c進一步突出遠離側壁102d。 在操作205中，將模塑物104放置於基板400上方以環繞半導體晶粒402。將基板400翻轉倒置(如圖4E中)。將模塑物104放置於犧牲膜401上以環繞半導體晶粒402。引入移除或平坦化操作以移除模塑物104之一部分以便暴露半導體基板102之背側102d。在某些實施例中，在背側102d上不保留模塑物104。在某些實施例中，藉由諸如蝕刻或研磨等操作將模塑物104移除以便係共面的。 在操作206中，將基板400及犧牲膜401移除(如圖4F中)。導電層106之一側自介電質105暴露。在操作207中，將介電質107放置於介電質105及導電層106上方(如圖4G中)。在某些實施例中，將介電質107放置於介電質105及導電層106之一部分上。在某些實施例中，導電層106之一部分106e透過介電質107之凹槽107a自介電質107暴露。 在操作208中，將導電跡線108放置於半導體晶粒402上方(如圖4H中)。在某些實施例中，藉由電鍍或濺鍍而放置導電跡線108。在某些實施例中，導電跡線108經放置使得導電跡線108沿著鈍化層103之凹槽103a、介電質105之凹槽105a、介電質107之凹槽107a及介電質107之頂部表面107b行進。在某些實施例中，介電質107包含聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗銲劑(SR)、ABF膜及諸如此類。 在操作209中，將介電質109放置於導電跡線108上方，形成凹槽109a以暴露導電跡線108之一部分108b，且如圖4I中放置接墊110。在某些實施例中，介電質109包含聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗銲劑(SR)、ABF膜及諸如此類。在某些實施例中，接墊110形成於導電跡線108之一部分108b及介電質109上面。在某些實施例中，接墊110填充凹槽109a且自介電質109之頂部表面109b延伸至導電跡線108之部分108b，使得接墊110與導電跡線108電連接。在某些實施例中，接墊110係凸塊下金屬(UBM)墊，該凸塊下金屬墊係用於接納凸塊且將接墊110與半導體晶粒402外部之電路電連接之可焊接表面。 在操作210中，將凸塊115放置於接墊110上(如圖4J中)。在某些實施例中，凸塊115係焊料凸塊、銲球、焊料膏等。在某些實施例中，凸塊115經組態以用於與另一晶粒、另一基板或另一半導體封裝上之墊附接。在某些實施例中，凸塊115係導電凸塊或導電接頭。在某些實施例中，導電墊102a透過導電跡線108及接墊110而與凸塊115電連接。 在操作211中，將圖4J中所展示之結構翻轉倒置並附接至圖4K之底部處之另一基板120。基板120可為封裝基板、板(例如，印刷電路板(PCB))、晶圓、晶粒、中介層基板或其他適合基板。凸塊結構透過各種導電附接點耦合至基板120。舉例而言，導電區122形成且圖案化於基板120上。導電區122係接點墊或導電跡線(其由遮罩層124呈現)之一部分。在一項實施例中，遮罩層124係形成且圖案化於基板120上以暴露導電區122之抗銲劑層。遮罩層124具有遮罩開口，該遮罩開口提供用於焊料接頭形成之窗。舉例而言，可將包含錫、鉛、銀、銅、鎳、鉍或其組合之合金之焊料層提供於導電區122上。半導體裝置100可透過接墊110與導電區122之間的接頭焊料結構126耦合至基板120。例示性耦合製程包含助銲劑施加、晶片安放、熔融焊料接頭之回銲及/或助銲劑殘渣之清潔。半導體基板102、接頭焊料結構126及其他基板120可稱為封裝總成或在當前實施例中稱為覆晶封裝總成。 在某些實施例中，半導體裝置100藉由封裝凸塊與另一封裝接合以變為堆疊式封裝(package on package) (PoP)。在某些實施例中，半導體裝置100透過封裝凸塊與另一封裝電連接。在某些實施例中，半導體裝置100之數個導電部件透過數個封裝凸塊與另一封裝之數個封裝墊對應地接合以變為PoP。 在某些實施例中，一種半導體裝置包含：半導體基板；導電墊，其位於該半導體基板上；及第一介電質，其位於該半導體基板上方。該半導體裝置亦包含：導電層，其放置於該第一介電質中；及第二介電質，其放置於該導電層上。在該半導體裝置中，該導電層之至少一部分自該第一介電質及該第二介電質暴露。該半導體裝置進一步包含導電跡線，該導電跡線部分地位於該第二介電質上方且與該導電層之該經暴露部分接觸。在該半導體裝置中，該導電跡線在一端處連接至該導電墊。 在某些實施例中，一種半導體裝置包含：半導體基板；導電墊，其位於該半導體基板上；及介電質，其位於該半導體基板上方。該半導體裝置亦包含模塑料，該模塑料環繞該半導體基板、該導電墊及該介電質。在該半導體裝置中，該模塑料包括自該模塑料與該半導體基板之間的界面凹陷之拐角。 在某些實施例中，一種製作半導體裝置之方法包含：提供基板；將導電跡線放置於基板上方；及將介電質放置於該導電跡線上。該方法進一步包含：提供半導體晶粒且將該半導體晶粒翻轉倒置以將該半導體晶粒附接至該基板；及移除半導體基板以暴露該導電跡線。 前述內容概述數個實施例之構件，使得熟習此項技術者可較佳地理解本揭露之態樣。熟習此項技術者應瞭解，其可容易地使用本揭露作為設計或修改用於實施與本文中介紹之實施例相同之目的及/或達成與該等實施例相同之優點之其他製程及結構之基礎。熟習此項技術者亦應認識到，此等等效構造並不背離本揭露之精神及範疇，且其可在不背離本揭露之精神及範疇之情況下在本文中做出各種改變、替換及更改。
100‧‧‧半導體裝置/半導體100a‧‧‧部分102‧‧‧半導體基板102a‧‧‧導電墊102b‧‧‧表面102c‧‧‧頂部表面102d‧‧‧側壁/側壁邊緣/背側103‧‧‧鈍化層103a‧‧‧凹槽103b‧‧‧頂部表面103d‧‧‧側壁104‧‧‧模塑料/模塑物104b‧‧‧拐角104c‧‧‧界面105‧‧‧介電質105a‧‧‧凹槽105b‧‧‧頂部表面105c‧‧‧部分105d‧‧‧側壁105e‧‧‧表面106‧‧‧導電層106b‧‧‧C形環106c‧‧‧延伸部分106e‧‧‧部分/經暴露部分106f‧‧‧平行側106s‧‧‧平行側107‧‧‧介電質107a‧‧‧凹槽107b‧‧‧頂部表面108‧‧‧導電跡線108a‧‧‧頂部表面108b‧‧‧部分109‧‧‧介電質109a‧‧‧凹槽109b‧‧‧頂部表面110‧‧‧凸塊下金屬/接墊115‧‧‧導電凸塊/凸塊120‧‧‧基板122‧‧‧導電區124‧‧‧遮罩層126‧‧‧接頭焊料結構300‧‧‧半導體裝置400‧‧‧基板401‧‧‧犧牲膜402‧‧‧半導體晶粒RA‧‧‧直徑RB‧‧‧直徑RC‧‧‧直徑W1‧‧‧寬度W2‧‧‧寬度
依據與附圖一起閱讀之以下詳細說明來最佳地理解本揭露之態樣。應注意，根據工業中之標準實踐，各種構件未按比例繪製。實際上，為論述清晰起見，可任意地增加或減小各種構件之尺寸。 圖1係根據某些實施例之半導體裝置。 圖1A係根據某些實施例之圖1中之半導體裝置之一部分之放大視圖。 圖1B係根據某些實施例之圖1A中之半導體裝置之一部分之局部視圖。 圖2係根據某些實施例之半導體裝置之一部分之局部視圖。 圖3係根據某些實施例之圖2中之半導體裝置之部分俯視圖。 圖4A至圖4K表示根據某些實施例之製作半導體裝置之方法之流程圖。
100‧‧‧半導體裝置/半導體
100a‧‧‧部分
102‧‧‧半導體基板

Claims (10)

  1. 一種半導體裝置，其包括：半導體基板；導電墊，其位於該半導體基板上；第一介電質，其位於該半導體基板上方；導電層，其放置於該第一介電質中；第二介電質，其放置於該導電層上，其中該導電層之至少一部分自該第一介電質及該第二介電質暴露；及，導電跡線，其部分地位於該第二介電質上方且與該導電層之該經暴露部分接觸，其中該導電跡線在一端處連接至該導電墊且與該導電墊直接接觸。
  2. 如請求項1之半導體裝置，其進一步包括環繞該半導體基板之模塑物。
  3. 如請求項1之半導體裝置，其進一步包括部分地覆蓋該導電墊之鈍化物。
  4. 如請求項1之半導體裝置，其中該導電跡線包括平行於該導電墊之兩個側。
  5. 如請求項4之半導體裝置，其中該兩個側中之一者與該第二介電質接 觸。
  6. 如請求項1之半導體裝置，其中該經暴露部分接近於該第一介電質之拐角。
  7. 如請求項1之半導體裝置，其中該導電跡線沿著該第一介電質中之凹槽保形地延行。
  8. 如請求項1之半導體裝置，其中該導電跡線沿著該第二介電質中之凹槽保形地延行。
  9. 一種半導體裝置，其包括：半導體基板；導電墊，其位於該半導體基板上；介電質，其位於該半導體基板上方；及模塑料，其環繞該半導體基板、該導電墊及該介電質；其中該模塑料包括自該模塑料與該半導體基板之間的界面凹陷之拐角，且該介電質延伸至自該模塑料之該界面凹陷之該拐角中。
  10. 一種製造半導體裝置之方法，其包括：提供基板；將導電跡線放置於基板上方；將介電質放置於該導電跡線上； 提供半導體晶粒且將該半導體晶粒翻轉倒置以將該半導體晶粒附接到該基板；及移除該基板以暴露該導電跡線。
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