TW201533810A - 半導體元件之封裝方法、封裝半導體元件及其設計方法 - Google Patents

半導體元件之封裝方法、封裝半導體元件及其設計方法 Download PDF

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TW201533810A
TW201533810A TW103145290A TW103145290A TW201533810A TW 201533810 A TW201533810 A TW 201533810A TW 103145290 A TW103145290 A TW 103145290A TW 103145290 A TW103145290 A TW 103145290A TW 201533810 A TW201533810 A TW 201533810A
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die
electrical connections
holes
packaged semiconductor
forming
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TW103145290A
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TWI548007B (zh
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Chuei-Tang Wang
Mon-Sen Liu
Chen-Hua Yu
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Taiwan Semiconductor Mfg Co Ltd
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    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Abstract

本發明有關於一種半導體元件之封裝方法、封裝半導體元件及其設計方法。在一些實施例中，半導體元件之封裝方法包括提供第一晶粒，以及將複數個第二晶粒耦合至第一晶粒。在第一晶粒以及每一第二晶粒之間形成電性連接。前述每一電性連接之一部份係設於前述第二晶粒之間。

Description

半導體元件之封裝方法、封裝半導體元 件及其設計方法
本發明是有關於一種半導體元件，且特別是有關於一種封裝半導體元件及其製造方法。
半導體元件可用於各式各樣的電子應用中，例如個人電腦、行動電話、數位相機及其他電子設備等。一般而言，半導體元件是在半導體基板上，依序沉積絕緣或介電層、導體層、半導體層等複數個材料層後，對上述各種材料層進行微影製程，以在其中形成線路構件及零件。
大體上，單一片半導體晶圓可製造數十或數百個積體電路。延著切割道切割積體電路，以切單化(singulated)成複數個單一晶粒。隨後，將前述單一晶粒各別封裝成例如多晶片模組、或其他封裝形式。
半導體業不斷改良各種電子構件(例如電晶體、二極體、電阻、電容等)之積集密度(integration density)，藉由持續縮減最小特徵尺寸，使預設區域內整合更多構件。在一些應用中，這些更小的電子構件也需要利用比過去封裝更小的區域，進行更小的封裝。
在一些實施例中，一種複數個半導體元件的封裝方法，包括提供第一晶粒，以及將複數個第二晶粒耦合至第一晶粒。在第一晶粒與每一第二晶粒之間形成一電性連接，其中每一電性連接之一部份係設於前述第二晶粒之間。
在一些實施例中，一種封裝半導體元件包括第一晶粒，以及複數個第二晶粒設置於第一晶粒上。在第一晶粒與每一第二晶粒之間設置複數個電性連接。每一電性連接之一部份係設於前述第二晶粒之間。
在一些實施例中，一種封裝半導體元件之設計方法包括提供第一晶粒設計，以及提供第二晶粒設計。第二晶粒設計之第二晶粒係用於堆疊至第一晶粒設計之第一晶粒上。第二晶粒設計則劃分成複數個第二晶粒。此方法包含設計封裝半導體元件之複數個電性連接。設計電性連接的步驟包含設計可耦合至複數個第二晶粒之水平電性連接，以及設計可耦合水平電性連接與第一晶粒之垂直電性連接。在一些實施例中，垂直電性連接可一次性使用於複數個第二晶粒之間。
100‧‧‧載板
100a‧‧‧第一載板
100b‧‧‧第二載板
102‧‧‧第一晶粒
104‧‧‧輸入/輸出區
106a/106b‧‧‧模塑化合物
108/124/134a/134b/138‧‧‧絕緣材料
110/140/140'‧‧‧內連線
120‧‧‧貫穿孔
122‧‧‧(第三)晶粒
132a/132b‧‧‧第二晶粒
146‧‧‧導體
150/150'/150"‧‧‧封裝半導體元件
152‧‧‧中介層
154‧‧‧種晶層
160‧‧‧流程圖
162‧‧‧提供第一晶粒之步驟
164‧‧‧將複數個第二晶粒耦合至第一晶粒之步驟
166‧‧‧在第一晶粒與每一第二晶粒之間形成電性連接，其中每一電性連接的一部份設於第二晶粒之間之步驟
從以下詳細說明配合所附的圖式，可對本揭露內容的各種觀點有較佳的理解。惟需留意的是，按照業界標準的做法，各種的特徵並未依比例繪製。事實上，為了討論清楚的緣故，各種的特徵的尺寸可任意放大或縮小。
〔圖1〕至〔圖7〕係繪示根據本發明一些實施例的一種半導體元件之封裝方法在不同階段的剖面示意圖。
〔圖8〕係〔圖7〕所示之封裝半導體元件的上視圖。
〔圖9〕至〔圖15〕係繪示根據本發明一些實施例的一種半導體元件之封裝方法在不同階段的剖面示意圖。
〔圖16〕係〔圖15〕所示之封裝半導體元件的上視圖。
〔圖17〕至〔圖23〕係繪示根據本發明一些實施例的一種半導體元件之封裝方法在不同階段的剖面示意圖。
〔圖24〕係〔圖23〕所示之封裝半導體元件的上視圖。
〔圖25〕係根據本發明一些實施例的一種半導體元件之封裝方法的流程圖。
下述揭露內容提供了許多不同的實施例或具體例，以實施所提供之客體之不同特徵。下述述之構件與安排的具體例是為了以簡化本揭露內容。但本揭露內容並不以這些具體例為限。舉例而言，在說明書中，第一特徵形成於第二特徵之上方或之上，可包含第一特徵與第二特徵直接接觸的實施例，亦可包含具有額外特徵可能形成在 第一特徵與第二特徵之間、使第一特徵與第二特徵並未直接接觸的實施例。此外，本揭露內容在不同具體例中會重複元件符號及/或字母。這類的重複是為了簡明的緣故，重複本身並非指所討論之不同實施例及/或配置之間就限於特定的關係。
再者，在此使用例如「之下(beneath)」、「下方(below)」、「較低(lower)」、「上方(above)」、「較高(upper)」等空間相對用語，是為了便於說明圖式繪示之一零件或特徵與另一(另一些)零件或特徵之關係。除了在圖中所繪示之方位外，這些空間相對用詞也隱含該元件在使用或操作中的不同方位。另外，設備可能以不同方式定位(旋轉90度或在其它方位上)，所以此處所使用的空間相對用語亦可做相應的解釋。
本揭露內容之一些實施例是有關於半導體元件的封裝方法及其結構。一些實施例則是有關於封裝半導體元件的設計方法。前述封裝半導體元件及其設計包括在堆疊在另一個晶粒上的複數個晶粒之間設置複數個貫穿孔(through-vias)。這些貫穿孔可設於模塑化合物中，或者這些貫穿孔可設於晶粒或中介層中，以下析述之。
圖1至圖7係繪示根據一些實施例的一種半導體元件之封裝方法在不同階段的剖面示意圖。請先參閱圖1，其係繪示第一晶粒102。在一些實施例中，第一晶粒102是用於進行第一功能。舉例而言，在一些實施例中，第一晶粒102可包含記憶元件。另一種方式，第一晶粒102可用 於進行其他型式的功能。在一些實施例中，第一晶粒102可例如利用較先進的晶圓節點(wafer node)製得。
第一晶粒102包括輸入/輸出區104，其中輸入/輸出區104是設於靠近第一晶粒102一側的表面。輸入/輸出區104可包括複數個連接元件，例如設於其表面的連接墊(圖未繪示)。在一些申請專利範圍中，此處所指的輸入/輸出區104又可稱為輸入/輸出介面。連接墊可耦合至第一晶粒102之內部線路，例如第一晶粒102之金屬層或多晶矽層中的介層窗(via)及/或導線(圖未繪示)。在一些實施例中，輸入/輸出區104的連接元件主要設於第一晶粒102之中間區域。另一種方式，輸入/輸出區104的連接元件可設於第一晶粒102之其他區域或第一晶粒102之整個表面之上方。在一些實施例中，輸入/輸出區104可例如包含寬型輸入/輸出(input/output；I/O)介面。在一些實施例中，I/O介面之連接，可包括例如約1μm至約300μm之線寬，以及例如約100至約1000或大於1000之I/O數量。另一種方式，輸入/輸出區104可包括其他線寬及其他I/O數量之I/O介面。
第一晶粒102係耦合至載板100，如圖1所示。第一晶粒102可利用例如黏著劑或膠水耦合至載板100。載板100可包含例如半導體晶圓之晶圓，或者載板100亦可包含有機基板或其他型式的基板。載板100包含犧牲構件，在第一晶粒102與其他晶粒封裝後，將移除犧牲構件，其中前述之其他晶粒可例如圖4所示之第二晶粒132a及第二 晶粒132b，另詳述於後。之後，載板100可予以清洗並用於例如封裝其他半導體元件。另一種方式，載板100可在封裝製程後丟棄。
依據一些實施例，第一晶粒102包含將與複數個第二晶粒(圖1未繪示，請參閱圖4所示之第二晶粒132a及第二晶粒132b)進行封裝的晶粒。
依據一些實施例，複數個第一晶粒102形成於載板100上(圖未繪示)。載板100上之複數個第一晶粒102可同時封裝後，再進行例如切單化(singulated)以形成複數個封裝半導體元件。
如圖2所示，在第一晶粒102之上方形成模塑化合物106a。模塑化合物106a包含模塑材料且可包含例如環氧樹脂、有機聚合物或添加矽基填充劑之聚合物。在一些實施例中，模塑化合物106a包含液態模塑材料(liquid molding compound；LMC)，其中液態模塑材料在應用時為膠態液體。另一種方式，模塑化合物106a可包含其他絕緣材料。倘若模塑化合物106a溢流至第一晶粒102之輸入/輸出區104中的連接元件之上表面，可去除例如輸入/輸出區104上的模塑化合物106a。在一些實施例中，模塑化合物106a係形成於第一晶粒102之周圍。
如圖2所示，絕緣材料108與內連線110係設於第一晶粒102與模塑化合物106a上。內連線110可包含後護層內連線(post-passivation interconnect；PPI)結構，而且在一些實施例中，絕緣材料108可包含例如聚苯 噁唑(polybenzoxazole；PBO)。另一種方式，內連線110與絕緣材料108可包含其他材料。
如圖3所示，晶粒122耦合至第一晶粒102上。在一些申請專利範圍中，此處所指之晶粒122又可稱為第三晶粒122。在一些實施例中，晶粒122包含例如輸入/輸出晶粒。晶粒122包含複數個貫穿孔120，且這些貫穿孔120形成在晶粒122內。晶粒122的一側可設有絕緣材料124。貫穿孔120或與貫穿孔120耦合之接觸墊的複數個端部係穿過絕緣材料124並暴露出來，以作為晶粒122的電性連接。貫穿孔120的複數個相對端部則耦合至第一晶粒102上之內連線110。依據一些實施例，貫穿孔120是預先形成於晶粒122中。貫穿孔120從晶粒122之一側延伸至另一側，並提供複數個垂直電性連接，其中垂直電性連接耦合至第一晶粒102。在一些實施例中，貫穿孔120之一端與內連線110連接，而內連線110設於第一晶粒102上並耦合至第一晶粒102。
在一些實施例中，貫穿孔120包含銅或銅合金。在一些實施例中，貫穿孔120可包括襯墊層、阻障層、種晶層以及導體填充材料。另一種方式，貫穿孔120可包含其他材料及材料層。在一些實施例中，貫穿孔120以較窄的線寬形成。舉例而言，在一些實施例中，貫穿孔120以第三晶粒122之較小特徵(minimum features)的尺寸(size)或關鍵尺寸(critical dimension；CD)形成。在一些實施例中，貫穿孔120之寬度可包含例如約1μm至約 200μm，其線寬可包含例如約1μm至約300μm。貫穿孔120之上視圖的外觀可包含例如圓形、橢圓形、矩型、長方形或其他形狀(圖未繪示)。另一種方式，貫穿孔120可包含其他形狀及尺寸。
依照一些實施例，貫穿孔120包含一部份的電性連接，而前述電性連接是形成在第一晶粒102與每一第二晶粒132a及第二晶粒132b之間。在一些實施例中，貫穿孔120包含例如複數個垂直電性連接。
在一些實施例中，晶粒122包含輸入/輸出控制器。在一些實施例中，晶粒122包含低階晶圓節點(low end wafer node)，例如塊狀平面節點。貫穿孔120可包含直通基板穿孔(through-substrate vias；TSVs)，其中直通基板穿孔是設於例如晶粒122內。在一些實施例中，貫穿孔120或耦合至貫穿孔120之接觸墊，可利用例如銅對銅銲接製程之金屬對金屬銲接製程，耦合至內連線120，其中在另一具體例中，貫穿孔120或耦合至貫穿孔120之接觸墊以及內連線120包含銅或銅合金。在一些實施例中，貫穿孔120包含設於晶粒122中的垂直電性連接，而垂直電性連接則電性耦合至第一晶粒102之輸入/輸出區104。
在載板100上同時封裝複數個第一晶粒102之實施例中，晶粒122係耦合至每一第一晶粒102。在一些實施例中，二個或二個以上晶粒122可耦合至第一晶粒102(圖未繪示)。
接著，如圖4所示，複數個第二晶粒132a與第二晶粒132b係耦合至第一晶粒102。圖式中只顯示二個第二晶粒132a與第二晶粒132b；然而，另一種方式，三個或三個以上的第二晶粒132a與第二晶粒132b可耦合至每一第一晶粒102(圖未繪示)。包括貫穿孔120之第三晶粒122係耦合至複數個第二晶粒132a與第二晶粒132b的二者之間。每一第二晶粒132a與第二晶粒132b可分別包括絕緣材料134a與絕緣材料134b，其中絕緣材料134a與絕緣材料134b係設於靠近第二晶粒132a與第二晶粒132b的表面上。連接元件例如接觸、接觸墊及/或銲墊(圖未繪示)，可設於絕緣材料134a與絕緣材料134b中，作為與第二晶粒132a與第二晶粒132b之電性連接。
在一些實施例中，第二晶粒132a與第二晶粒132b是用來進行第二功能，第二功能可不同於第一晶粒102之第一功能。另一種方式，在其他實施例中，第二晶粒132a與第二晶粒132b可包含與第一晶粒102類似或相同的功能。在一些實施例中，當第一晶粒102與複數個第二晶粒132a與第二晶粒132b封裝在一起時，第一晶粒102與複數個第二晶粒132a與第二晶粒132b包含使其作為系統單晶片(system-on-a-chip；SOC)的功能。
在一些實施例中，第二晶粒132a與第二晶粒132b包含處理器。在一些實施例中，第二晶粒132a與第二晶粒132b包含先進節點積體電路(advanced node integrated circuits)。在一些實施例中，第二晶粒132a 與第二晶粒132b可包含多閘極場效電晶體(multiple-gate field effect transistors；MUGFETs)，而且可包含例如鰭式場效電晶體(FinFETs)。另一種方式，第二晶粒132a與第二晶粒132b可包含其他型式的元件。
在一些實施例中，可以再設計單一第二晶粒(圖未繪示)以於後續與第一晶粒102封裝，其中單一第二晶粒包含複數個第二晶粒132a與第二晶粒132b，使含有貫穿孔120之第三晶粒122可以設在複數個第二晶粒132a與第二晶粒132b之二者之間，另於後詳述。
依照一些實施例，包含貫穿孔120之第三晶粒122係耦合於複數個第二晶粒132a與第二晶粒132b之二者之間。依照一些實施例，第一晶粒102之複數個部份，例如內連線110，係電性耦合至第三晶粒122中之貫穿孔120。
如圖4所示，第二晶粒132a、第二晶粒132b及第三晶粒122之間設有模塑化合物106b。模塑化合物106b形成於例如第二晶粒132a、第二晶粒132b及第三晶粒122之周圍。模塑化合物106b包含與模塑化合物106a所述類似的材料。在一些申請專利範圍中，此處所指的模塑化合物106a與模塑化合物106b又可稱為例如第一模塑化合物106a與第二模塑化合物106b，端視出現的先後順序而定。在一些實施例中，模塑化合物106b可設於例如第二晶粒132a、第二晶粒132b以及設於第二晶粒132a與第二晶 粒132b之間的前述部份之電性連接(例如第三晶粒122中的貫穿孔120)的周圍。
如圖5所示，複數個第二晶粒132a與第二晶粒132b以及第三晶粒122上形成絕緣材料138、內連線140及內連線140’。絕緣材料138包含一或一以上的絕緣材料層及/或保護(passivation)層。內連線140及內連線140’包含形成於絕緣材料138中的導體襯墊及/或導體介層窗。在一些實施例中，絕緣材料138、內連線140及內連線140’包含後護層內連線(post-passivation interconnect；PPI)結構及/或重分布層(redistribution layer；RDL)。另一種方式，絕緣材料138、內連線140及內連線140’可包含其他型式的連接結構。
在一些實施例中，絕緣材料138、內連線140及內連線140’包含形成在模塑化合物106b、第二晶粒132a、第二晶粒132b以及第三晶粒122上的複數個水平電性連接。依照一些實施例，水平電性連接係設於封裝半導體元件150靠近第二晶粒132a與第二晶粒132b之一側上(請參閱圖7)。內連線140’之複數個部份(例如水平電性連接)係耦合至第三晶粒122之貫穿孔120。在一些實施例中，絕緣材料138、內連線140包括例如扇出區(fan-out regions)，使封裝半導體元件150之電性連接的腳位(footprint)，比第一晶粒102、第二晶粒132a及第二晶粒132b之接觸、接觸墊或銲墊來得更寬。
如圖6所示，在一些實施例中，載板100移除後，複數個導體146隨即耦合至內連線140。導體146係形成在例如水平電性連接之複數個部份上，且耦合至水平電性連接之複數個部份。導體146可包含例如銲料(solder)之共晶材料(eutectic material)，其中銲料係耦合至例如內連線140之接觸墊或銲墊。導體146包含例如銲錫凸塊(solder bump)或銲球(solder ball)。此處所使用之「銲料(solder)」包括鉛基(lead-based)銲料或無鉛(lead-free)銲料，其中鉛基銲料可例如鉛錫(Pb-Sn)組成物；無鉛銲料可包括鍗化銦(InSb)，錫、銀與銅(“SAC”)組成物，以及具有共同熔點且在電性應用中能形成導體銲料連接的其他共晶材料。就無鉛銲料而言，可以使用不同組成物之SAC銲料，例如SAC 105(Sn 98.5%,Ag 1.0%,Cu 0.5%)、SAC 305以及SAC 405。例如銲球之無鉛導體146可由錫銅(SnCu)化合物形成，不需使用銀(Ag)。另一種方式，無鉛銲料連接元件可包括錫銀(Sn-Ag)，不需使用銅。導體146可以是格狀的矩陣或稱球柵陣列(ball grid array；BGA)所形成之其中一者。導體146另可配置成其他形狀。導體146亦可包含例如非球體導體連接元件。在一些實施例中，也可以不包括導體146。
如圖7所示，接下來，倒置封裝半導體元件150。在一些實施例中，可利用晶粒切割(die saw)，延著切割道對複數個封裝半導體元件150進行切單化(singulated)。封裝半導體元件150包括第一晶粒102以及 一起封裝之第二晶粒132a與第二晶粒132b。第三晶粒122中之貫穿孔120為封裝半導體元件150提供垂直電性連接。內連線140與內連線140’則為封裝半導體元件150提供水平電性連接。其優點在於，由於貫穿孔120設於第二晶粒132a與第二晶粒132b之間，可減少佈線(wiring，例如內連線140’)的長度及繞線(routing)，從而改善封裝半導體元件150之效能。
圖8為圖7所示之封裝半導體元件的上視圖。第三晶粒122中之貫穿孔120係設於第二晶粒132a與第二晶粒132b之間。
內連線110、內連線140及內連線140’可包含例如鈦、鋁、鎳、鎳釩(NiV)、銅之金屬或上述之任意組合或複數層。內連線110、內連線140及內連線140’可利用例如電解電鍍、無電鍍、濺鍍、化學氣相沉積等方法及/或微影製程形成。內連線110、內連線140及內連線140’可包括單層，或利用例如鈦、鎢化鈦(TiW)、鉻或其他材料之黏著層形成的複數層。絕緣材料108、絕緣材料124及絕緣材料138可包含例如環氧樹脂、聚亞醯胺、苯並環丁烯(benzocyclobutene；BCB)、聚苯噁唑(polybenzoxazole；PBO)等聚合物，然亦可使用其他較軟、通常是有機介電材料。可利用例如旋塗或其他常用的形成方法塗布絕緣材料108、絕緣材料124及絕緣材料138。另一種方式，內連線110、內連線140、內連線140’、 絕緣材料108、絕緣材料124及絕緣材料138可包含其他材料且可利用其他方式形成。
圖9至圖15係繪示根據本發明一些實施例的一種半導體元件之封裝方法在不同階段的剖面示意圖。如圖9所示，第一晶粒102包括輸入/輸出區104，且第一晶粒102耦合至載板100。如圖10所示，模塑化合物106a形成於第一晶粒102之周圍，且絕緣材料108以及內連線110形成在第一晶粒102與模塑化合物106a上。
如圖11所示，中介層152耦合至第一晶粒102上。在一些實施例中，中介層152包含例如保護中介層(passive interposer)。中介層152包括複數個貫穿孔120，且複數個貫穿孔120形成在中介層152中。中介層152的每一側係暴露出貫穿孔120或與貫穿孔120耦合之接觸墊的複數個端部，以作為中介層152的電性連接。依據一些實施例，貫穿孔120是預先形成在中介層152中。貫穿孔120從中介層152之一側延伸到另一側，並提供垂直電性連接以耦合至第一晶粒102。在一些實施例中，貫穿孔120的一端連接至第一晶粒102上之內連線110並耦合至第一晶粒102。
如圖12所示，接著，複數個第二晶粒132a與第二晶粒132b係耦合至第1晶粒102。包括貫穿孔120之中介層152係耦合至複數個第二晶粒132a與第二晶粒132b之二者之間。模塑化合物106b設於第二晶粒132a、第二晶粒132b及中介層152之間。如圖13所示，絕緣材料138、 內連線140及內連線140’係形成於複數個第二晶粒132a與第二晶粒132b以及中介層152上。如圖14所示，在一些實施例中，複數個導體146隨即耦合至內連線140之複數個部份。
如圖15所示，接著，倒置封裝半導體元件150’。在一些實施例中，可利用晶粒切割，延著切割道對複數個封裝半導體元件150’進行切單化並予以分離。封裝半導體元件150’包括第一晶粒102以及一起封裝之第二晶粒132a與第二晶粒132b。中介層152中之貫穿孔120為封裝半導體元件150’提供垂直電性連接。內連線140與內連線140’則為封裝半導體元件150’提供水平電性連接。其優點在於，由於中介層152中之貫穿孔120設於第二晶粒132a與第二晶粒132b之間，可減少佈線(wiring，例如內連線140’)的長度及繞線(routing)，從而改善封裝半導體元件150’之效能。圖16係圖15所示之封裝半導體元件150’的上視圖。
圖17至圖23係繪示根據本發明一些實施例的一種半導體元件之封裝方法在不同階段的剖面示意圖。貫穿孔120不是如之前實施例所述設在第三晶粒122或中介層152中，而是形成在載板100a上，之後再封裝在模塑化合物106b內。舉例而言，在圖17中，提供第一載板100a，然後形成種晶層154於載板100a上。種晶層154可包含銅或銅合金，利用濺鍍製程、物理氣相沉積、原子層沉積或其他方法形成。光阻(圖未繪示)係形成於種晶層154上，且 利用預設圖案將光阻圖案化，而形成貫穿孔120。光阻可利用微影製程進行圖案化，其係藉由光罩反射或透過的光或能量，對光阻進行曝光。之後，對光阻進行顯影，再將光阻之曝光區域(或未曝光區域，端視光阻所含之正型光阻或負型光阻而異)予以灰化(ashed)或蝕刻去除，留下光阻內的圖案。接著，進行電化學鍍(electro-chemical plating；ECP)或電鍍製程時，以光阻為罩幕，透過種晶層154上的圖案化光阻形成貫穿孔120。然後，如圖17所示，移除光阻，留下設在種晶層154上的貫穿孔120。
如圖18所示，然後，複數個第二晶粒132a及第二晶粒132b耦合至種晶層154上之第一載板100a。複數個第二晶粒132a及第二晶粒132b可利用例如黏著劑或膠水耦合至第一載板100a。接著，在第二晶粒132a及第二晶粒132b之間、在貫穿孔120之間、在第二晶粒132a及第二晶粒132b與貫穿孔120之間，形成模塑化合物106b，亦如圖18所示。之後，貫穿孔120設於模塑化合物106b中，且設於第二晶粒132a及第二晶粒132b之間。如圖19所示，絕緣材料138、內連線140及內連線140’形成於第二晶粒132a、第二晶粒132b及貫穿孔120上，而第二晶粒132a、第二晶粒132b及貫穿孔120則設於模塑化合物106b中。
如圖20所示，隨即移除第一載板100a，並倒置封裝半導體元件。接著，將第二載板100b耦合至絕緣材料138與內連線140(例如包含水平電性連接)，亦如圖20所示。然後，移除種晶層154，將絕緣材料108與內連線110 形成在第二晶粒132a與第二晶粒132b、貫穿孔120以及模塑化合物106b上，亦如圖20所示。內連線110係電性耦合至例如貫穿孔120。
如圖21所示，第一晶粒102耦合至第二晶粒132a、第二晶粒132b以及貫穿孔120。第一晶粒102之複數個部份係電性耦合至貫穿孔120。第一晶粒102之輸入/輸出區104係藉由例如內連線110而電性耦合至貫穿孔120。
如圖22所示，模塑化合物106a形成於第一晶粒102之上方及周圍，然後移除第二載板100b。如圖23所示，在一些實施例中，連接元件146係形成於內連線140之複數個部份上。在一些實施例中，連接元件146係耦合至例如內連線140形成之水平電性連接之複數個部份。在一些實施例中，可利用晶粒切割，延著切割道對複數個封裝半導體元件150"進行切單化並予以分離。圖24係圖23所示之封裝半導體元件150”的上視圖。
圖25係根據本發明一些實施例的一種半導體元件之封裝方法的流程圖160。在步驟162中，提供第一晶粒102(亦如圖1所示)。在步驟164中，將第二晶粒132a與第二晶粒132b耦合至第一晶粒102(圖4)。在步驟166中，在第一晶粒與每一第二晶粒132a及第二晶粒132b之間形成電性連接，其中每一電性連接的一部份設於第二晶粒132a及第二晶粒132b之間(圖4)。
本揭露內容之一些實施例包含封裝半導體元件150、封裝半導體元件150’或封裝半導體元件150”之設計方法。舉例而言，提供第一晶粒設計，以及提供第二晶粒設計。第二晶粒設計之第二晶粒係用於堆疊至第一晶粒設計之第一晶粒102上。第二晶粒設計則劃分成複數個第二晶粒132a及第二晶粒132b。接著，設計封裝半導體元件150、封裝半導體元件150’或封裝半導體元件150”之複數個電性連接。在一些實施例中，前述一電性連接包含貫穿孔120、內連線140及內連線140’。設計電性連接的步驟包含設計水平電性連接，其中水平電性連接包含內連線140及內連線140’，且內連線140及內連線140’可耦合至複數個第二晶粒132a及第二晶粒132b。設計電性連接的步驟更包含設計垂直電性連接，其中垂直電性連接包含貫穿孔120，且貫穿孔120可耦合包含內連線140與內連線140’之水平電性連接以及第一晶粒10。包含貫穿孔120之垂直電性連接可一次性使用於複數個第二晶粒132a及第二晶粒132b之間。設計垂直電性連接之步驟，包含如圖23所示在模塑化合物106b中設計複數個貫穿孔120，如圖7所示設計包含複數個貫穿孔120之第三晶粒122，或者如圖15所示設計包含複數個貫穿孔120之中介層152。
本揭露內容之一些實施例的優點與好處包括提供新穎的封裝半導體元件150、封裝半導體元件150’或封裝半導體元件150”，其包括在第二晶粒132a及第二晶粒132b之間設有貫穿孔120，且第二晶粒132a及第二晶粒 132b係堆疊在具有第一晶粒102之封裝體中。第二晶粒設計則進行劃分，而複數個第二晶粒132a及第二晶粒132b是用於進行原來第二晶粒設計的功能，且製得的第二晶粒132a及第二晶粒132b係與第一晶粒102封裝。接著，將低成本的貫穿孔120插設於複數個第二晶粒132a及第二晶粒132b之間，以提供短距離且高輸入/輸出連接的電性連接。依照一些實施例，貫穿孔120可包含形成於第三晶粒122、中介層152或模塑通孔106b中之基板通孔(through-substrate vias)。低成本之第三晶粒122與低成本之中介層152可用於提供貫穿孔120。
在貫穿孔120預先形成於第三晶粒122或中介層152內之實施例中，貫穿孔120可有利於在組裝前(例如在封裝製程前)進行預測試(pre-tested)，可增加封裝半導體元件150及封裝半導體元件150’之產量。在一些實施例中，貫穿孔120提供比水平電性連接距離更短的電性連接，從而使封裝半導體元件150、封裝半導體元件150’及封裝半導體元件150”的電性連接距離更短。
上述提供的封裝半導體元件具有較低成本解改善電性效能，是因為在第二晶粒132a及第二晶粒132b之間設的貫穿孔120提供較短的電性連接。在一些實施例中，在第一晶粒102及/或第二晶粒132a與第二晶粒132b中避免形成基板通孔，可降低第一晶粒102及/或第二晶粒132a與第二晶粒132b之製造成本。在一些實施例中，在第一晶粒102及/或第二晶粒132a與第二晶粒132b中避免形 成基板通孔，可例如減少第一晶粒102及/或第二晶粒132a與第二晶粒132b使用之晶粒區域。在封裝半導體元件150、封裝半導體元件150’及封裝半導體元件150”的中間區域設置貫穿孔120，結果降低封裝體在整體上的應力。再者，在半導體元件封裝系統與製造流程中，可輕易實施此處所述之新穎的封裝系統與製造流程。
在一些實施例中，一種複數個半導體元件的封裝方法，包括提供第一晶粒，以及將複數個第二晶粒耦合至第一晶粒。在第一晶粒與每一第二晶粒之間形成一電性連接，其中每一電性連接之一部份係設於前述第二晶粒之間。
在一些實施例中，一種封裝半導體元件包括第一晶粒，以及複數個第二晶粒設置於第一晶粒上。在第一晶粒與每一第二晶粒之間設置複數個電性連接。每一電性連接之一部份係設於前述第二晶粒之間。
在一些實施例中，一種封裝半導體元件之設計方法包括提供第一晶粒設計，以及提供第二晶粒設計。第二晶粒設計之第二晶粒係用於堆疊至第一晶粒設計之第一晶粒上。第二晶粒設計則劃分成複數個第二晶粒。此方法包含設計封裝半導體元件之複數個電性連接。設計電性連接的步驟包含設計可耦合至複數個第二晶粒之水平電性連接，以及設計可耦合至水平電性連接與第一晶粒之垂直電性連接。在一些實施例中，垂直電性連接可一次性使用於複數個第二晶粒之間。
上述已概述數個實施例的特徵，使本發明所屬技術領域中具有通常知識者可更了解本揭露內容之觀點。本發明所屬技術領域中具有通常知識者應可理解，以本揭露內容為基礎設計或修飾其它製程與結構可實現與此處採用之實施例相同的目的及/或達到相同的優點。本發明所屬技術領域中具有通常知識者亦應理解，所謂均等的架構並未脫離本揭露內容之精神和範圍，且本發明所屬技術領域中具有通常知識者在不脫離本揭露之精神和範圍下，進行各種之改變、置換及變更。
102‧‧‧第一晶粒
104‧‧‧輸入/輸出區
106a/106b‧‧‧模塑化合物
108/124/138‧‧‧絕緣材料
110/140/140'‧‧‧內連線
120‧‧‧貫穿孔
122‧‧‧(第三)晶粒
132a/132b‧‧‧第二晶粒
146‧‧‧導體
150‧‧‧封裝半導體元件

Claims (20)

  1. 一種複數個半導體元件之封裝方法，包含：提供一第一晶粒；將複數個第二晶粒耦合至第一晶粒；以及在該第一晶粒與每一該些第二晶粒之間形成一電性連接，其中每一該些電性連接之一部份係設於該些第二晶粒之間。
  2. 根據申請專利範圍第1項所述之方法，其中形成每一該些電性連接之該部份之步驟更包含形成複數個貫穿孔。
  3. 根據申請專利範圍第2項所述之方法，其中形成該些貫穿孔之步驟更包含在一第三晶粒或一中介層中形成該些貫穿孔，且其中形成每一該些電性連接之該些部份之步驟更包括在該些第二晶粒的二者之間耦合該第三晶粒或該中介層。
  4. 根據申請專利範圍第3項所述之方法，其中形成該些貫穿孔之步驟更包含形成複數個垂直電性連接，且其中該方法更包含：耦合該第一晶粒至一載板；在該第一晶粒周圍形成一第一模塑化合物； 將該些第二晶粒及該三晶粒或該中介層耦合至乾第一晶粒，其中該第一晶粒之複數個部份係電性耦合至該三晶粒或該中介層之該些貫穿孔；在該些第二晶粒及該三晶粒或該中介層周圍形成一第二模塑化合物；在該第二模塑化合物、該些第二晶粒及該三晶粒或該中介層上形成複數個水平電性連接，其中該些水平電性連接之複數個部份係電性耦合至該三晶粒或該中介層之該些貫穿孔；移除該載板；以及將複數個導體耦合至該些水平電性連接。
  5. 根據申請專利範圍第2項所述之方法，其中形成該些貫穿孔之步驟更包含將該些貫穿孔設置在一模塑化合物中，且該模塑化合物係設置於該些第二晶粒之間。
  6. 根據申請專利範圍第5項所述之方法，其中形成該些貫穿孔之步驟更包含對一第一載板上之該些貫穿孔進行電鍍步驟，其中形成該些貫穿孔之步驟更包含形成複數個垂直電性連接，且其中該方法更包含：將該些第二晶粒耦合至該第一載板上；在該些第二晶粒及該些貫穿孔之間形成該模塑化合物； 在該模塑化合物、該些第二晶粒及該些貫穿孔上形成複數個水平電性連接，其中該些水平電性連接之複數個部份係電性連接至該些貫穿孔；移除該第一載板；將一第二載板耦合至該些水平電性連接；以及將該第一晶粒耦合至該些第二晶粒及該些貫穿孔，其中該第一晶粒之複數個部份係電性連接至該些貫穿孔。
  7. 根據申請專利範圍第6項所述之方法，其中形成該模塑化合物之步驟更包含形成一第一模塑化合物，且其中該方法更包含：在該第一晶粒周圍形成一第二模塑化合物；移除該第二載板；以及將複數導體耦合至該些水平電性連接。
  8. 一種封裝半導體元件，包含：一第一晶粒；複數個第二晶粒設置於該第一晶粒上；以及在該第一晶粒與每一該些第二晶粒之間設置複數個電性連接，其中每一該些電性連接之一部份係設於該些第二晶粒之間。
  9. 根據申請專利範圍第8項所述之封裝半導體元件，其中該些電性連接之該些部份包含該封裝半導體元件之複數個垂直電性連接。
  10. 根據申請專利範圍第9項所述之封裝半導體元件，其中該第一晶粒更包含一輸入/輸出介面，且其中該些垂直電性連接係電性耦合至該第一晶粒之該輸入/輸出介面。
  11. 根據申請專利範圍第9項所述之封裝半導體元件，其中該些垂直電性連接包含複數個貫穿孔，且該些貫穿孔係設置於一模塑化合物中。
  12. 根據申請專利範圍第9項所述之封裝半導體元件，更包含在該些第二晶粒的二者之間設置一第三晶粒或一中介層，且其中該些垂直電性連接包含複數個貫穿孔，且該些貫穿孔係設置於該第三晶粒或該中介層中。
  13. 根據申請專利範圍第9項所述之封裝半導體元件，其中該些電性連接更包含複數個水平電性連接，且其中該些水平電性連接之複數個部份係電性耦合至該些垂直電性連接。
  14. 根據申請專利範圍第13項所述之封裝半導體元件，其中該些水平電性連接係設於該封裝半導體元件靠近該些第二晶粒之一側。
  15. 根據申請專利範圍第13項所述之封裝半導體元件，其中該些水平電性連接包含一重分布層(redistribution layer；RDL)或一後護層內連線(post-passivation interconnect；PPI)結構。
  16. 根據申請專利範圍第13項所述之封裝半導體元件，更包含複數個導體耦合至該些水平電性連接。
  17. 根據申請專利範圍第8項所述之封裝半導體元件，更包含一第一模塑化合物以及一第二模塑化合物，其中該第一模塑化合物設於該第一晶粒之周圍，該第二模塑化合物設於該些第二晶粒之周圍以及該些電性連接位於該些第二晶粒之間的該部份。
  18. 根據申請專利範圍第8項所述之封裝半導體元件，其中該第一晶粒係用於進行一第一功能，該些第二晶粒係用於進行一第二功能，該第二功能不同於第一功能，且該封裝半導體元件包含一系統單晶片(system-on-a-chip；SOC)。
  19. 一種封裝半導體元件之設計方法，包含：提供一第一晶粒設計；提供一第二晶粒設計，該第二晶粒設計之一第二晶粒係用於堆疊至該第一晶粒設計之該第一晶粒上； 將該第二晶粒設計劃分成用於複數個第二晶粒之一設計；以及設計該封裝半導體元件之複數個電性連接，其中設計該些電性連接之步驟包含：設計複數個水平電性連接，其中該些水平電性連接係耦合至與該些第二晶粒；以及設計複數個垂直電性連接，其中該些垂直電性連接係於該些水平電性連接與該第一晶粒之間耦合。
  20. 根據申請專利範圍第19項所述之設計方法，其中設計該些垂直電性連接之步驟包含設計複數個貫穿孔，或設計一第三晶粒或一中介層，其中該第三晶粒或該中介層包含該些貫穿孔。
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US20200020666A1 (en) 2020-01-16
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US11289449B2 (en) 2022-03-29
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