TWI532142B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
TWI532142B
TWI532142B TW103104612A TW103104612A TWI532142B TW I532142 B TWI532142 B TW I532142B TW 103104612 A TW103104612 A TW 103104612A TW 103104612 A TW103104612 A TW 103104612A TW I532142 B TWI532142 B TW I532142B
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Taiwan
Prior art keywords
mold resin
semiconductor
semiconductor device
laser
layer
Prior art date
Application number
TW103104612A
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English (en)
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TW201438181A (zh
Inventor
Taizo Nomura
Original Assignee
Toshiba Kk
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Publication date
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Publication of TW201438181A publication Critical patent/TW201438181A/zh
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Publication of TWI532142B publication Critical patent/TWI532142B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
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Description

半導體裝置之製造方法
[相關申請案]
本申請案享受以日本專利申請案2013-59350號(申請日：2013年3月22日)及日本專利申請案2013-258043號(申請日：2013年12月13日)為基礎申請案之優先權。本申請案藉由參照該等基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置及其製造方法。
近年來，於行動電話等便攜式無線通信機器中，避免由內置之各種電子零件產生之電磁雜訊干擾無線系統成為較大之課題。先前，作為此種雜訊抑制對策，一般有利用金屬板包圍包含產生源之電路(金屬板屏蔽)之方法。然而，該方法存在招致機器之大型化、高背化之問題。
因此，研究對作為雜訊源之電子零件本身實施屏蔽對策，作為其一，開發有於經樹脂密封之半導體封裝之表面藉由鍍敷而設置屏蔽層者(以下，稱為屏蔽半導體封裝)。此種半導體封裝具有如下優點：除屏蔽零件本身以外，還可將屏蔽層形成為非常薄，故可謀求機器之進一步之小型化或薄型化。
然而，另一方面，於藉由雷射而標記製品資訊時，有貫通屏蔽層而損害屏蔽性之虞。又，若為防止此種貫通，而使標記之深度較淺，則產生視認性降低之問題。
本發明所欲解決之課題在於提供一種可小型化、薄型化，且具有良好之屏蔽性能並且具備視認性亦優異之雷射標記之半導體裝置及其製造方法。
實施形態之半導體裝置包括配線基板、搭載於上述配線基板上之半導體元件、密封上述半導體元件之塑模樹脂(mold resin)、及設置於上述塑模樹脂上之屏蔽層，且上述塑模樹脂於表面具有因雷射照射而產生之標記，且於具有該標記之塑模樹脂上設置有上述屏蔽層。
實施形態之半導體裝置之製造方法具備如下步驟：於配線基板上搭載半導體晶片；利用塑模樹脂密封上述半導體元件；於上述塑模樹脂之表面藉由雷射照射而施加標記；及於施加有上述標記之塑模樹脂表面形成屏蔽層。
1a~1i‧‧‧半導體元件(半導體晶片)
2‧‧‧配線基板
2a‧‧‧表面配線層
2b‧‧‧內層配線層
3‧‧‧外部電極
4‧‧‧信號線
5‧‧‧接地線
6‧‧‧塑模樹脂
7‧‧‧標記部
8‧‧‧屏蔽層
10‧‧‧導體裝置(半導體封裝)
圖1係表示一實施形態之半導體裝置之構造之剖面圖。
圖2係表示一實施形態之半導體裝置之製造方法之流程之圖。
以下，參照圖式對實施形態進行說明。
圖1係表示一實施形態之半導體裝置之構造之剖面圖。
圖1所示之半導體裝置(半導體封裝)10係所謂之積層型半導體裝置，且於配線基板2上多段地積層有複數個半導體元件(半導體晶片)1a、1b、1c、…、1h，而且，另外於配線基板2上搭載1個半導體元件1i。於圖式之例中，所積層之半導體元件之個數為8個、即積層有8段，但半導體元件之積層數並未特別限定，例如亦可為1層、2層、5層、16層、32層等。於圖式之例中，積層8段之半導體元件1a~ 1h為NAND閃存，另外搭載於配線基板2上之半導體元件1i為NAND控制器，半導體裝置10具有與記憶裝置、例如記憶卡或SSD(Solid State Disk，固態硬碟)等同等之功能。
複數個半導體元件1a~1i均使用矽基板等半導體基板。另一方面，配線基板2使用例如將樹脂基板、陶瓷基板、玻璃基板等絕緣基板作為基材而使用之多層配線基板。作為應用樹脂基板之配線基板2，可列舉一般之多層銅箔積層板(多層印刷電路板)等。於配線基板2之下表面側，設置有用以與外部連接之電極墊，且於其上固定焊接凸塊等外部電極3。又，於配線基板2之上表面側，設置有包含信號圖案及接地圖案之表面配線層2a，各半導體元件1a~1i分別經由信號線4及接地線5而連接於該等信號圖案及接地圖案。進而，於配線基板2之內部設置有表面配線層2a及連接於外部電極3側之電極墊之內層配線層2b。
於如此般搭載有複數個半導體元件1a~1i之配線基板2之上表面，以包覆半導體元件1a~1i、或設置於配線基板2上表面之表面配線層2a、將半導體元件1a~1i與表面配線層2a連接之信號線4及接地線5之方式塑模塑模樹脂6。該塑模樹脂6係將半導體元件1a~1i或表面配線層2a、信號線4及接地線5等密封而形成絕緣層者，例如使用含有碳黑等填料之環氧樹脂等。
於塑模樹脂6之上表面，藉由雷射之照射而刻印製品編號、製造年月日、製造工場等製品資訊(圖1中，7表示藉由利用雷射照射之刻印而形成之標記部)，進而，於該經刻印之塑模樹脂6之表面整體、即上表面及側面、進而於緊連著塑模樹脂6之側面之配線基板2之側面，使用金屬鍍敷或金屬濺鍍形成屏蔽層8。屏蔽層8係主要用以屏蔽半導體元件1a~1i所產生之電磁雜訊者。因此，電性連接於設置於配線基板2之下表面之接地用外部電極，藉此確保屏蔽性。
形成屏蔽層8之金屬材料並未特別限定，例如使用Cu、Ni、Cr或含有B、Co或W之Ni合金等。又，屏蔽層8既可為單層亦可為包含複數層之積層構造。進而，其厚度並未特別限定，但為了半導體裝置10之小型化、薄型化，而較佳為儘可能地薄。藉由使屏蔽層8之厚度較薄，而可提高標記部7之視認性。即，若使屏蔽層8之厚度較厚，則利用雷射照射之刻印之深度變小而視認性降低。藉由使屏蔽層8之厚度較薄而可防止該視認性之降低。但是，若過薄則有屏蔽層8之機械強度降低，且其一部分視情況剝離等而屏蔽性降低之虞。就此種觀點而言，屏蔽層8較佳為2~4μm之範圍。
於本實施形態中，標記部7之刻印深度為約30μm，屏蔽層8由3μm厚之Ni層及Cu層之2層構造構成。
再者，於因雷射而產生之標記中，YAG(Yttrium Aluminum Garnet，釔鋁石榴石)雷射或YVO4(釔．釩酸鹽)雷射等因點徑較小，且可形成約30μm左右之深度之刻印，故較佳。於本實施形態中，使用點徑0.1mm之YAG雷射。
雖省略圖示，但於本實施形態中，可設為使埋設於塑模樹脂6之接地線5之線圈頂部與屏蔽層8接觸之構成。藉由使接地線5與屏蔽層8接觸，而謀求半導體裝置10之接地強化，且可進一步提高屏蔽性能。再者，為使接地線5之線圈頂部與屏蔽層8接觸，而只要如下所述般於連接接地線5時，使線圈高度高於信號線4之線圈高度，即，使接地線5之線圈頂部之位置高於信號線4之線圈頂部之位置，並且於施加因雷射而產生之標記時使接地線5之線圈頂部露出即可。藉由對使接地線5露出之塑模樹脂6形成屏蔽層8，而可使接地線5與屏蔽層8接觸。再者，於該情形時，塑模樹脂6之材料較佳為使用透明或半透明之可透視內部之材料。藉此，可確認應露出之接地線5、特別是其線圈頂部之位置，從而可於雷射標記時確實且適當地使接地線5露出。
又，於本實施形態之另一例中，可對接地圖案剖面於側面露出之配線基板2形成屏蔽層8。於該情形時，以跨過半導體裝置10之外形線之方式預先形成接地圖案，且以切斷接地圖案之方式進行下述分離，藉此可使接地圖案剖面於形成屏蔽層8之前在配線基板2之側面露出。
於本實施形態之半導體裝置中，因於藉由雷射照射而形成標記部7之塑模樹脂6之表面形成有屏蔽層8，故裝置之大型化、高背化得到抑制，並且可具有標記部7之優異視認性、可靠性較高之屏蔽性能。又，於使接地線5與屏蔽層8接觸之情形時，可謀求接地強化，且可進一步提高屏蔽性能。
其次，使用圖2所示之流程圖對該實施形態之半導體裝置10之製造方法之一例進行說明。
如圖2所示，步驟主要包括以下6步驟：製造集合基板之步驟(101)、搭載半導體元件之步驟(102)、利用塑模樹脂進行密封之步驟(103)、分離成各個半導體裝置之步驟(104)、利用雷射照射施加標記之步驟(105)、形成屏蔽層之步驟(106)。
首先，於集合基板之製造步驟(101)中，製作將複數個配線基板2連續設置為矩陣狀之構造之集合基板。
繼而，於半導體元件搭載步驟(102)中，於上述各配線基板之上表面依序積層半導體元件1a、1b、1c、…、1h，並且搭載半導體元件1i，將設置於配線基板2之信號圖案及接地圖案與各半導體元件1a~1i經由信號線4及接地線5而連接。此時，接地線5與信號線4較佳為接地線5之線圈頂部位於較信號線4之線圈頂部更高位。藉此，可於後續步驟中使接地線5與屏蔽層8容易地接觸，從而可謀求接地之強化、進而屏蔽性能之提高。
繼而，於利用塑模樹脂之密封步驟(103)中，於搭載有半導體元 件1a~1i之集合基板之上表面側，將塑模樹脂6、例如環氧樹脂總括塑模，密封半導體元件1a~1i。塑模樹脂6之塑模可使用轉移塑模法、壓縮塑模法、灌注方法、印刷法等塑模法。
繼而，於分離步驟(104)中，為製作各個半導體裝置10，而將塑模樹脂6與集合基板一併切斷，分離成複數個搭載有半導體元件1a~1i之配線基板2。切斷可使用鑽石刀片等刀片。
繼而，於標記步驟(105)中，藉由具有YAG雷射等之雷射標記裝置而於配線基板2上之塑模樹脂6之上表面，刻印製品名、製品編號、製造年月日、製造工場等製品資訊。就獲得良好之視認性及作業性之觀點而言，刻印之深度較佳為20~40μm左右，更佳為25~35μm左右，進而更佳為大致30μm。
而且，刻印較佳為以使塑模樹脂6內之接地線5之線圈頂部露出之方式進行。為此，較佳為，於半導體元件搭載步驟(102)中，於連接接地線5時調節其線圈高度。又，較佳為，於照射雷射之前，利用安裝於雷射標記裝置之相機等辨識接地線5之線圈頂部之位置，於進行對準修正後，進行雷射照射。藉由進行此種對準修正，而可使接地線5之線圈頂部確實地露出。即，接地線5於利用塑模樹脂之密封步驟(103)中，線圈頂部之位置因樹脂流動而變化。因此，藉由利用相機等辨識該產生變化之位置並進行對準修正，而可使接地線5之線圈頂部確實地露出。再者，於利用相機等辨識接地線5之線圈頂部之位置之情形時，作為塑模樹脂6之材料，必須使用可透視之材料。
繼而，於屏蔽層形成步驟(106)中，對經雷射標記之塑模樹脂6之表面整體、即上表面及側面整體實施金屬鍍敷或金屬濺鍍，形成例如3μm厚之屏蔽層8。藉此，製作如圖1所示之半導體裝置10。
再者，於實施金屬鍍敷或金屬濺鍍時，為提高屏蔽層8對於塑模樹脂6之密接性，而較佳為預先將塑模樹脂6之表面、至少上表面粗 化。於本方法中，為獲得多個半導體裝置，而切斷總括密封之塑模樹脂。因此，塑模樹脂6之側面藉由切斷而已經粗化，故基本上無需進行粗化，但若需要，則亦可進一步追加粗化步驟。作為粗化之方法，亦可使用搪磨等方法，但就可將標記步驟(105)中使用之雷射裝置作為粗化裝置而使用，且無需重新準備用於粗化之裝置，且可謀求步驟之簡化、步驟時間之縮短而言，較佳為利用雷射照射之方法。
該粗化步驟亦可於標記步驟(105)之前及之後中之任一者進行，就標記部7之視認性之方面而言，較佳為於標記步驟(105)之前進行。即，若於標記步驟(105)之後進行，則利用雷射之刻印之深度縮小，視認性降低。
根據以上說明之半導體裝置之製造方法，因藉由金屬鍍敷或金屬濺鍍而形成有屏蔽層，故可形成厚度非常薄之屏蔽層，從而可使半導體裝置小型化．薄型化。
而且，於對塑模樹脂之表面藉由雷射而標記製品資訊等之後，因形成有屏蔽層，故可具有可靠性較高之屏蔽性能，並且可形成具有充分之視認性之標記部。即，當於屏蔽層形成後進行雷射標記之情形時，有產生因雷射所致之屏蔽層之貫通而屏蔽降低之虞。又，於不貫通之情形時，刻印較淺，無法獲得充分之視認性。於上述半導體裝置之製造方法中，因於雷射標記後形成屏蔽層，故無貫通屏蔽層之虞，且可進行具有充分之深度之刻印。因此，可具有可靠性較高之屏蔽性能，且可形成具有充分之視認性之標記部。
進而，當於形成屏蔽層後進行雷射標記之情形時，金屬之雷射反射率通常較大，故不得不增大雷射輸出，雷射材料之消耗劇烈，且必須頻繁之更換，但於上述方法中，因對雷射光之吸收良好之塑模樹脂進行標記，故雷射輸出較低即可，且無需頻繁之更換，因而可謀求製造成本之降低、作業效率之提高。
以上，對本發明之實施形態進行了說明，但該實施形態係作為示例而提出，並未意圖限定發明之範圍。該新穎之實施形態可以其他各種形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該實施形態及其變形包含於發明之範圍或主旨內，並且包含於申請專利範圍中記載之發明及其均等之範圍內。
1a~1i‧‧‧半導體元件(半導體晶片)
2b‧‧‧內層配線層
3‧‧‧外部電極
4‧‧‧信號線
5‧‧‧接地線
6‧‧‧塑模樹脂
7‧‧‧標記部
8‧‧‧屏蔽層
10‧‧‧半導體裝置(半導體封裝)

Claims (2)

  1. 一種半導體裝置之製造方法，其特徵在於具備如下步驟：於配線基板上搭載半導體元件；利用塑模樹脂密封上述半導體元件；將上述塑模樹脂之表面粗化；藉由雷射照射而對上述塑模樹脂之表面被粗化之部分施加標記；及於施加有上述標記之塑模樹脂表面形成屏蔽層。
  2. 如請求項1之半導體裝置之製造方法，其中於上述標記步驟中，透過上述塑模樹脂而確認連接於上述元件之接地線之位置，並基於該確認到之位置而對上述塑模樹脂之表面施加標記。
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