CN107278325A - 集成电路封装 - Google Patents

集成电路封装 Download PDF

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Publication number
CN107278325A
CN107278325A CN201580062500.0A CN201580062500A CN107278325A CN 107278325 A CN107278325 A CN 107278325A CN 201580062500 A CN201580062500 A CN 201580062500A CN 107278325 A CN107278325 A CN 107278325A
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CN
China
Prior art keywords
encapsulation
conductive
lead frame
pillar structure
conductive material
Prior art date
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Pending
Application number
CN201580062500.0A
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English (en)
Inventor
K·坎农
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies International Ltd
Qualcomm Inc
Original Assignee
Cambridge Silicon Radio Ltd
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Filing date
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Application filed by Cambridge Silicon Radio Ltd filed Critical Cambridge Silicon Radio Ltd
Publication of CN107278325A publication Critical patent/CN107278325A/zh
Pending legal-status Critical Current

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Abstract

集成电路封装包括：半导体管芯；引线框架，其位于第一平面中；至少一个导电柱结构，其从所述第一平面向外延伸，其中所述引线框架和所述至少一个导电柱结构由烧结导电材料形成；封装材料，其封装所述半导体管芯、所述引线框架和所述至少一个导电柱结构；导电层，其位于所述封装的上表面上，所述导电层导电连接到所述至少一个导电柱。还公开了制造方法。

Description

集成电路封装
背景技术
对于减小电子电路的尺寸有不断增加的动力。已经发展了具有减小的形状因子的集成电路封装的范围。图1示出四方扁平无引线(QFN)封装8的例子。集成电路设置在管芯2上，管芯2由粘合剂4固定到焊盘3。在该封装中，引线5在封装内部，并且接触焊盘设置在封装的下表面上。引线键合6将管芯连接到接触焊盘5。因为引线5不在封装的占用空间之外延伸，这导致较小的封装。
图2示出引线上倒装芯片(FOL)封装10。集成电路设置在由焊球11固定到引线5的管芯2上，引线5在管芯2的下方延伸，并且因此是引线5而不是管芯附着焊盘3支撑管芯。该封装避免对引线键合的需要并进一步减小了封装的总尺寸。
集成电路易受电磁干扰(EMI)的影响。EMI干扰可以由电路板之外的源引起或来自同一电路板上的其它器件。器件之间的EMI的问题进一步由于器件在电路板上的间距的减小而加重。已知提供对集成电路封装的EMI屏蔽可能将封装的尺寸增加到不合需要的程度或可能在制造期间需要额外的工艺步骤，这可能增加制造封装的复杂度和成本。
以下描述的实施例不限于解决用于屏蔽封装的已知布置的任何或所有缺点的实施方式。
发明内容
提供本发明内容用于以简化的形式介绍所选择的概念，以下在具体实施方式中进一步对其进行描述。本发明内容并不旨在识别所要求保护的主题的关键特征或必要特征，也不旨在用来有助于确定所要求保护的主题的范围。
本公开的一个方面提供集成电路封装，其包括：半导体管芯；引线框架，其位于第一平面中；至少一个导电柱结构，其从所述第一平面向外延伸，其中所述引线框架和所述至少一个导电柱结构由烧结导电材料形成；封装材料，其封装所述半导体管芯、所述引线框架和所述至少一个导电柱结构；导电层，其位于所述封装的上表面上，所述导电层导电连接到所述至少一个导电柱。
所述至少一个导电柱结构可以具有大于所述引线框架的高度的高度。
所述至少一个导电柱结构可以垂直于所述第一平面延伸。
所述封装包括多个所述导电柱。
所述多个导电柱在所述引线框架的周边周围间隔开。
所述至少一个导电柱可以位于所述封装的周边上。或者，所述至少一个导电柱可以从所述封装的周边向内偏移。
所述至少一个导电柱可以包括位于所述引线框架的周边周围的导电材料的连续壁。
所述壁可以位于所述封装的周边上。
所述导电层可以形成所述封装的EMI屏蔽和所述封装的热屏蔽中的至少一种。
所述导电层可以是导电薄板材料。
所述导电层可以是烧结导电材料。
所述烧结导电材料可以是烧结金属。
所述烧结导电材料可以是烧结银。
所述烧结导电材料可以是传导热的。
所述烧结导电材料可以是传导电的。
所述封装还可以包括在所述半导体管芯之下的热焊盘。导电路径可以将所述至少一个导电柱结构连接到所述热焊盘。
本公开的另一方面提供一种封装半导体管芯的方法，其包括：通过在需要引线框架的元件的位置处将导电材料沉积到载体的表面上来形成所述引线框架；通过在需要至少一个导电柱结构的位置处将所述导电材料沉积到所述载体的所述表面上来形成所述至少一个导电柱结构，其中所述导电材料是烧结导电材料；附着半导体管芯；将所述半导体管芯连接到所述引线框架；封装所述半导体管芯、所述引线框架和所述至少一个导电柱结构以形成包覆封装；将导电层加入到所述包覆封装的上表面，所述导电层导电连接到所述至少一个导电柱；以及去除所述载体。
所述至少一个导电柱结构可以形成具有大于引线框架的高度的高度。
所述至少一个导电柱结构可以由多个沉积所述导电材料的阶段形成，在所述阶段之间进行固化。
加入导电层可以包括将一层所述导电材料沉积在所述包覆封装的上表面上。
加入导电层可以包括将导电薄板附着到所述包覆封装的上表面。
沉积所述导电材料可以包括以下其中之一：丝网印刷所述导电材料；印刷所述导电材料。
如对于技术人员将显而易见的，优选的特征可以视情况而组合，并可以与本发明的任何方面组合。
附图说明
将参考附图以举例的方式描述本发明的实施例，其中：
图1示出四方扁平无引线(QFN)封装；
图2示出引线上倒装芯片(FOL)封装；
图3A-3K示出用于形成封装的制造过程；
图4示出可以在图3A-3K的过程中使用的模板；
图5示出安装到电路板的封装；
图6A-6E示出封装中的导电结构的例子；以及
图7示出制造过程的流程图。
在所有附图中共同的参考标记用于表示相似的特征。
具体实施方式
以下仅以举例的方式描述本发明的实施例。这些例子代表申请人当前已知的实施本发明的最佳方式，虽然它们并不是可以实现这一点的唯一方式。本说明书阐述例子的功能和用于构造和操作例子的步骤的顺序。然而，相同或等效的功能和顺序可以由不同的例子来实现。
图3A-3J示出形成示例性封装的一序列阶段。在这些图中示出的示例性封装是四方扁平无引线(QEN)封装，虽然技术可以应用于其它类型的封装，例如引线上倒装芯片(FCQFN)封装。
在图3A，提供载体21。载体21在制造过程的随后阶段期间提供支撑。载体21是可以由任何能够经受住封装过程的最大偏移温度(excursion temperature)的适当材料制造的平面薄板。一般的材料例子包括不锈钢或玻璃。
在图3B，将模板31施加到载体21的表面。模板31用作掩模或样板，并限定其中形成引线框架的元件的区域22。图4在平面图中示出模板31，其具有开孔区域42以限定其中将形成引线框架的元件的区域42。模板31还包括：其中将形成柱23的开口区域43；其中将形成热焊盘24的开口区域44；以及其中将形成将柱23连接到热焊盘24的连接部23A的开口区域41。热焊盘是导热材料在最终封装中位于半导体管芯之下并传导热量远离管芯的区域。模板31可以是印刷到载体21的表面上的材料。模板31是临时层且随后被去除。模板31可以在图3C所示的阶段之后被去除，或保留在适当的位置上直到稍后(例如图3E之后)的阶段。
在图3C，在载体21上形成引线框架。在载体21上在需要引线框架的元件22的位置处沉积导电材料。引线框架的元件22包括封装的接触焊盘。接触焊盘也可以被称为着落盘(land)。在最终封装中，这些提供至封装的下表面的电连接/来自封装的下表面的电连接。导电材料可以沉积在封装的中央区域中以用作管芯26的热焊盘24。引线框架的元件22、24位于与载体21的平面平行的公共平面中。在图3B中施加的模板31用作在图3C沉积的导电材料的样板。导电材料是金属粉末和悬浮组分的混合物。金属粉末可以是银或铜。可以使用模板32作为样板以限定其中将形成引线框架的元件的开口区域通过丝网印刷工艺来施加导电材料。或者，可以通过3D或喷墨印刷工艺来施加导电材料，其中材料选择性地沉积在载体21上的精确位置处。如果3D印刷或喷墨印刷技术用于沉积导电材料，则图3B和3C所示的模板31可以被省略且导电材料可以在需要它的位置处直接沉积到载体21上。
在图3C，也在载体21上在需要至少一个导电柱结构23的一个或多个位置处沉积导电材料。柱由与引线框架的其它元件相同的导电材料形成。在图3B施加的模板31也限定其中将要形成至少一个柱的区域。柱结构23和引线框架的元件22同时形成。通常，柱由与引线框架相同的材料形成。
在未示出的随后阶段中，导电材料经受一组工艺条件，其中在一组推荐的环境条件下在限定的时间段内施加热量，其蒸发糊状物的悬浮组分以形成在图3C的烧结固体。这个阶段可以仅使用热量和时间来形成烧结固体，或可以使用压力、热量和时间。另一种选择是可以使用紫外(UV)辐射来烧结导电材料的颗粒，如果颗粒足够小且如果暴露在UV辐射下而在颗粒中产生足够的能量。一旦烧结工艺完成，就可以去除模板31。图3D示出去除模板31之后的部分制造的封装，留下了引线框架的元件22和部分构造的柱23。
在多个阶段中沉积导电材料以实现至少一个柱23的期望高度。在一个阶段中沉积的材料的示例性厚度是25微米。引线框架的元件22可能只需要沉积和烧结的单个阶段。至少一个柱23可能需要材料沉积的多个阶段。图3E示出制造过程的另一阶段，其中采用另一模板32。可以在引线框架的其它元件22上施加模板32，如图3E所示。如以前一样，导电材料经受限定的工艺条件，并且烧结在图3F施加的材料中的金属粉末。一旦过程完成，就去除模板32。可以通过布设多层模板材料直到实现期望的厚度来形成模板32。或者，可以在单个步骤中形成具有所需最终厚度的模板32。
图3F示出在已经去除模板32之后的部分制造的封装。导电柱结构23具有大于引线框架的其它元件的高度34的高度33。柱的所需高度33由包括管芯厚度26、管芯附着厚度25、引线键合高度27、环高与封装表面之间的最小可接受的距离和材料34的第一烧结底部层的厚度的部分的总和来确定。半导体管芯具有300微米的一般厚度，但可以通过使用常规晶圆研磨工艺而使其有很大程度的减小，这将影响柱23的最终高度的设计。与封装设计的其它元件相比，导电柱23的高度允许柱23导电连接到在最终封装的上表面上的屏蔽层。在所示的例子中，导电柱垂直于引线框架的平面而延伸。在材料沉积的每个阶段之后，通过使用所推荐的工艺条件来固化所沉积的材料。导电材料是烧结材料，例如金属。
在图3G，附着半导体管芯26。粘合剂25将管芯26固定到热焊盘24。
在图3H，管芯26连接到引线框架的元件22。在QFN封装的情况下，如所示出的，引线键合27连接在半导体管芯26和引线框架的接触焊盘22之间。图3A示出已经安装引线键合27之后的封装。
图3H所示的封装然后由封装材料28(例如模塑料)封装。封装材料28具有电绝缘特性。封装材料28封装半导体管芯26、引线框架22和至少一个导电柱结构23。在图3I所示的例子中，封装材料28封装在所有垂直延伸的侧面上的至少一个导电柱结构23。在至少一个导电柱结构23位于封装周边上的另一例子(未示出)中，封装材料28可以只封装在柱结构23的面向内的侧面上的至少一个导电柱结构23。至少一个导电柱结构23的面向外的侧面可以保持暴露。在完成的封装中，模塑料的高度不大于柱23的高度。包覆封装可能需要表面加工(例如，研磨或某些其它工艺)以提供模塑料的水平上表面并确保柱的顶部完全暴露。柱23的上表面需要良好、干净的导电表面以提供用于屏蔽的可靠接触。图3I示出已经施加模塑料并使其变得平坦之后的部分制造的封装。
在图3J，将导电层29施加到包覆封装的上表面。导电层29导电连接到导电柱23。导电层29可以是预先形成的导电材料的薄板，其例如通过粘合剂或焊接到柱23而附着到封装的上表面。或者，可以通过以与前面针对引线框架和柱23所描述的类似方式将导电材料沉积在所述上表面上来形成导电层29。最后，在图3K，从封装的下侧去除载体21。载体21可以被重新使用。
图5示出安装到印刷电路板的封装。封装的引线框架的接触焊盘22经由焊球38连接到在电路板上的焊盘39。封装的导电柱23经由焊球36连接到在电路板上的焊盘37。导电柱23提供穿过模塑料28的通孔。如果用于形成引线框架22的导电材料是银，则可以直接焊接到引线框架。这与常规蚀刻的铜引线框架相比减少了一个阶段，常规蚀刻的铜引线框架在它们可以被焊接之前需要电镀。热焊盘24连接到在热焊盘24之下的PCB上的地平面区45。横截面也示出将柱23连接到热焊盘24的连接部23A。连接部23A提供柱23与热焊盘24之间的热和/或电传导路径。
导电层29提供对半导体管芯26的EMI屏蔽。EMI屏蔽可以保护管芯不受封装之外的EMI源的影响。附加或可选地，EMI屏蔽可以保护封装之外的任何器件不受由管芯26产生的EMI的影响。附加或可选地，导电层29可以传导热，并且可以帮助扩散/消散由管芯26产生的热量。连接部23A将柱23连接到热焊盘24。热焊盘24通常由焊料47连接到PCB 45、46。PCB 46可以包括热通孔以消散热量。
图6A-6E示出可以在如上所述的封装中设置成连接到屏蔽层的导电结构的一些例子。图6A-6C中的每一个在平面图中示出封装，其中屏蔽层被去除。示出引线框架的一组接触焊盘22。在图6A中，提供单个导电柱23。柱23可以具有前面在图3C-3K中所示的类型。柱23可以设置在封装范围内的任何位置，例如在角落处或沿着侧面。虽然图6A所示的柱从封装的周边向内偏移，但是柱可以设置在封装的周边上。连接部23A将柱23连接到热焊盘24。在图6B、6C和6D中，图6A和图3C-3K中所示类型的多个柱23设置在封装周围。在图6B中，柱23位于引线框架的这一组接触焊盘22之外。图6B示出在封装的角附近的一组四个柱23和将柱23连接到热焊盘24的连接部23A。图6C示出具有不同于图6B的位置上的一组四个柱23的另一例子。还示出引线框架的迹线。迹线将焊盘22连接到更接近热焊盘24和管芯26的焊盘的向内位置。图6D示出具有安装在角附近的柱23的另一例子。总保持架是理想的，但通常总保持架不太实际，因为输入和输出需要穿过封装/从封装穿出。柱的间距将被芯片设计限制。在图6E中，连续壁53设置在封装周围。壁53以与在图3C-K中所示的相同方式形成。壁可以被视为彼此邻接的多个柱，或者一对其间连接有额外结构的柱。壁43位于引线框架的这一组接触焊盘22之外。多个连接部23A将壁53连接到热焊盘24。另一种选择(未示出)是提供由两个或更多个壁区段形成的不连续壁。虽然图6E所示的壁53从封装的周边向内偏移，但是壁53可以设置在封装的周边上。使柱23和/或壁53从封装的周边向内偏移可以使从一块封装切割单独的封装变得容易。虽然图6A-6E的例子示出具有圆形或正方形横截面的柱，但是柱可以具有其它形状。例如，柱可以具有矩形横截面。
图7示出封装半导体管芯的示例性方法。在块101，提供载体。如果使用丝网印刷工艺来施加导电材料，则在块102将模板布设在载体上。在块103，通过在需要引线框架的元件的位置处将导电材料沉积到载体的表面上来形成引线框架。在块104，通过将导电材料沉积到载体的表面上来形成至少一个导电柱结构。可以同时执行块103和104。可以在块105固化在块103和104沉积的材料。如果需要的话，至少一次进一步重复执行块106-108。在块109，去除任何模板。在块110，附着半导体管芯。在块111，通过施加封装材料(例如模塑料)以形成包覆封装来封装至少一个导电柱结构。在块111，将导电层加入到包覆封装的上表面。如上所述，在加入导电层之前，可能需要对封装材料和/或至少一个柱结构进行一些表面加工。导电层导电连接到至少一个导电柱。在最后一个块(未示出)中去除载体。
对块106-108的进一步一次或多次的重复为至少一个导电柱结构提供了大于半导体管芯、线环高度、管芯附着、线环高度与封装顶表面之间的最小间隔以及引线框架的组合高度的高度。
当柱结构23和引线框架的元件22同时形成时，这减小提供导电屏蔽层之间的连接所需的制造过程阶段的数量。例如，在导电屏蔽层已经安装到封装之后，上述方法不需要任何另外的阶段。
如对于技术人员显而易见的，在本文中给出的任何范围或器件值可以扩展或改变而不失去所寻求的效果。
将理解的是，以上描述的益处和优点可以涉及一个实施例或可以涉及几个实施例。实施例不限于解决任何或所有所述问题的实施例或具有任何或所有所述益处和优点的实施例。
对“一”项的任何提及是指那些项目中的一个或多个。术语“包括”在本文中用于意指包括所识别的方法块或元件，但这样的块或元件并不包括专用列表，并且方法或装置可以包含额外的块或元件。
可以以任何适当的顺序或在适当情况下同时执行本文中所描述的方法的步骤。此外，可以从任何方法中删除单独的块而不偏离本文中所描述的主题的精神和范围。上述的任何例子的方面可以与所描述的任何其它例子的方面组合以形成另外的例子而不失去所寻求的效果。
将理解的是，以上对优选实施例的描述仅以举例的方式给出，并且本领域技术人员可以做出各种修改。虽然以上已经以某种详细程度或参考一个或多个单独的实施例描述了各种实施例，但本领域技术人员可以对所公开的实施例进行许多改变而不偏离本发明的精神或范围。

Claims (20)

1.一种集成电路封装，包括：
半导体管芯；
引线框架，其位于第一平面中；
至少一个导电柱结构，其从所述第一平面向外延伸，其中所述引线框架和所述至少一个导电柱结构由烧结导电材料形成；
封装材料，其封装所述半导体管芯、所述引线框架和所述至少一个导电柱结构；
导电层，其位于所述封装的上表面上，所述导电层导电连接到所述至少一个导电柱。
2.如权利要求1所述的封装，其中所述至少一个导电柱结构具有大于所述引线框架的高度的高度。
3.如权利要求1所述的封装，其中所述至少一个导电柱结构垂直于所述第一平面延伸。
4.如权利要求1所述的封装，包括多个所述导电柱。
5.如权利要求4所述的封装，其中所述多个导电柱在所述引线框架的周边周围间隔开。
6.如权利要求1所述的封装，其中所述至少一个导电柱位于所述封装的周边上。
7.如权利要求1所述的封装，其中所述至少一个导电柱包括位于所述引线框架的周边周围的导电材料的连续壁。
8.如权利要求7所述的封装，其中所述壁位于所述封装的周边上。
9.如权利要求1所述的封装，其中所述导电层形成所述封装的EMI屏蔽和所述封装的热屏蔽中的至少一种。
10.如权利要求1所述的封装，其中所述导电层是导电薄板材料。
11.如权利要求1所述的封装，其中所述导电层是烧结导电材料。
12.如权利要求1所述的封装，其中所述烧结导电材料是烧结金属。
13.如权利要求1所述的封装，其中所述烧结导电材料是烧结银。
14.如权利要求1所述的封装，还包括在所述半导体管芯之下的热焊盘，并且其中导电路径将所述至少一个导电柱结构连接到所述热焊盘。
15.一种封装半导体管芯的方法，包括：
通过在需要引线框架的元件的位置处将导电材料沉积到载体的表面上来形成所述引线框架；
通过在需要至少一个导电柱结构的位置处将所述导电材料沉积到所述载体的所述表面上来形成所述至少一个导电柱结构，其中所述导电材料是烧结导电材料；
附着半导体管芯；
将所述半导体管芯连接到所述引线框架；
封装所述半导体管芯、所述引线框架和所述至少一个导电柱结构以形成包覆封装；
将导电层加入到所述包覆封装的上表面，所述导电层导电连接到所述至少一个导电柱；以及
去除所述载体。
16.如权利要求15所述的方法，其中所述至少一个导电柱结构具有大于所述引线框架的高度的高度。
17.如权利要求15所述的方法，其中形成至少一个导电柱结构包括多个沉积所述导电材料的阶段，在所述阶段之间进行固化。
18.如权利要求15所述的方法，其中加入导电层包括将一层所述导电材料沉积在所述包覆封装的上表面上。
19.如权利要求15所述的方法，其中加入导电层包括将导电薄板附着到所述包覆封装的上表面。
20.如权利要求15所述的方法，其中通过沉积所述导电材料来形成所述至少一个导电柱结构包括以下其中之一：
丝网印刷所述导电材料；
印刷所述导电材料。
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