CN104465542B - 具有模塑通孔的叠层封装结构 - Google Patents
具有模塑通孔的叠层封装结构 Download PDFInfo
- Publication number
- CN104465542B CN104465542B CN201410341681.8A CN201410341681A CN104465542B CN 104465542 B CN104465542 B CN 104465542B CN 201410341681 A CN201410341681 A CN 201410341681A CN 104465542 B CN104465542 B CN 104465542B
- Authority
- CN
- China
- Prior art keywords
- moulding compound
- connector
- stress relief
- packaging part
- relief structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 74
- 238000000465 moulding Methods 0.000 title claims abstract description 14
- 239000000206 moulding compound Substances 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000000608 laser ablation Methods 0.000 claims description 5
- 230000001788 irregular Effects 0.000 claims description 4
- 230000008030 elimination Effects 0.000 claims 1
- 238000003379 elimination reaction Methods 0.000 claims 1
- 230000035882 stress Effects 0.000 description 17
- 239000010410 layer Substances 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 150000002118 epoxides Chemical class 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Connector Housings Or Holding Contact Members (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本文公开了一种器件,包括:具有第一侧的第一封装件,第一侧具有设置在其上的多个连接件;以及通过连接件安装在第一封装件上的第二封装件。模塑料设置在第一封装件的第一侧上以及第一封装件和第二封装件之间。多个应力消除结构(SRS)设置在模塑料中,多个SRS中的每个均包括位于模塑料中并且与多个连接件中的每个都间隔开的不含金属的腔。本发明涉及一种具有模塑通孔的叠层封装结构。
Description
技术领域
本发明涉及一种具有模塑通孔的叠层封装结构。
背景技术
半导体器件用于各种电子应用中,诸如个人电脑、手机、数码相机和其他电子设备。通常,通过在半导体衬底上方循序地沉积绝缘或介电层、导电层和半导体材料层,然后使用光刻图案化各种材料层以在其上形成电路部件和元件来制造半导体器件。
通过不断地减小最小部件尺寸以允许更多的部件集成到给定区域中,半导体工业不断地改进各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成密度。在一些情况下,这些较小的电子部件也需要比以前的封装件利用更小的面积的更小的封装件。
由于叠层封装(PoP)技术具有允许在较小的整体封装件内更密集的集成集成电路的能力,因此叠层封装技术正变得越来越流行。在诸如智能手机的许多先进的手持设备中采用PoP技术。虽然PoP技术已允许较小的封装件轮廓,但是总厚度的减小当前仍受到接合点高度和邻近的接合点之间的距离(称为间距)的限制。通过在第二封装件上堆叠具有一个或多个管芯的封装件或衬底,并以导电互连件连接封装件来形成PoP器件。
发明内容
针对现有技术中存在的问题,根据本发明的一个方面,提供了一种器件,包括:衬底,具有第一侧,在所述第一侧上设置有多个连接件和管芯;模塑料,设置在所述第一侧上并且围绕所述多个连接件中的每个;以及应力消除结构(SRS),设置在所述模塑料中,所述SRS包括位于所述模塑料中并且与所述多个连接件中的每个分隔开的腔。
在上述器件中,还包括:位于所述模塑料中的多个连接件开口,所述多个连接件中的每个均设置在所述多个连接件开口的相应的一个中,其中,所述SRS与所述多个连接件开口分隔开。
在上述器件中,所述SRS设置在所述多个连接件和所述管芯之间。
在上述器件中,所述SRS具有圆锥形形状。
在上述器件中,所述管芯设置在所述多个连接件的中心区域中,并且所述SRS设置为邻近所述多个连接件的内部拐角区域。
在上述器件中,还包括:安装在所述衬底上方的封装件,所述模塑料设置在所述衬底和所述封装件之间,其中,所述多个连接件中的每个均在所述衬底和所述封装件之间延伸。
根据本发明的另一方面,还提供了一种器件,包括:第一封装件,具有第一侧,在所述第一侧上设置有多个连接件;第二封装件,通过所述连接件安装在所述第一封装件上;模塑料,设置在所述第一封装件的第一侧上和所述第一封装件与所述第二封装件之间;以及多个应力消除结构(SRS),设置在所述模塑料中,所述多个SRS中的每个均包括位于所述模塑料中并且与所述多个连接件中的每个都间隔开的不含金属的腔。
在上述器件中,还包括:安装至所述第一封装件的第一侧的管芯,所述多个连接件设置在所述管芯周围,所述多个SRS中的每个位于所述多个连接件中的一个或多个与所述管芯之间。
在上述器件中,还包括:位于所述模塑料中的多个连接件开口,所述多个连接件中的每个均设置在所述多个连接件开口的相应的一个中,其中,所述多个SRS中的每个均与所述多个连接件开口分隔开。
在上述器件中,其中,所述多个SRS中的每个均具有与所述多个连接件开口中的一个相同的形状。
在上述器件中,其中,所述多个SRS的至少一个具有圆锥形形状。
在上述器件中,所述多个SRS中的每个均与所述多个连接件开口中的每个间隔开至少30μm。
在上述器件中,所述多个SRS的总表面积为所述模塑料的表面积的约0.01%和约15%之间。
根据本发明的又一方面,还提供了一种形成器件的方法,包括:在所述第一封装件的第一侧和所述第一封装件的第一侧上的多个连接件中的每个的周围形成模塑料;以及在所述模塑料中形成多个应力消除结构(SRS),所述多个SRS中的每个均包括位于所述模塑料中并且与所述多个连接件中的每个间隔开的不含金属的腔。
在上述方法中,还包括:将管芯安装至所述第一封装件的第一侧,其中,形成所述模塑料包括在所述管芯周围形成模塑料。
在上述方法中,所述多个连接件设置在所述管芯周围,并且所述多个SRS中的每个均形成为邻近所述多个连接件的内部拐角区域以及形成在所述多个连接件的内部拐角区域与所述管芯之间。
在上述方法中,还包括:在所述模塑料中形成多个连接件开口,所述多个连接件中的每个均设置在所述多个连接件开口的相应的一个中,其中,所述多个SRS中的每个均与所述多个连接件开口分隔开。
在上述方法中,形成所述多个SRS和形成所述多个连接件开口包括去除所述模塑料的一部分。
在上述方法中,去除所述模塑料的一部分包括通过激光烧蚀去除所述模塑料的所述一部分。
在上述方法中,所述多个SRS中的每个均形成为具有包括正方形、圆形、椭圆形、矩形、环形、三角形、菱形或不规则多边形的形状。
附图说明
为了更全面地理解本发明及其优势,现将结合附图所进行的以下描述作为参考,其中:
图1A和图1B是根据实施例示出具有模塑的应力消除结构的封装件的示意图;
图2至图9示出了根据实施例的在形成具有模塑的应力消除结构的叠层封装结构中的中间步骤的截面图;
图10是根据实施例示出模塑的应力消除结构的结构的截面图;
图11A至图11F示出了根据各个实施例的模塑的应力消除结构的布局;以及
图12是根据实施例示出形成具有模塑的应力消除结构的叠层封装结构的方法的流程图。
除非另有说明,否则不同图中的相应标号和字符通常指的是相应的部件。绘制的图只用于说明实施例的相关方面,并且无需按比例绘制。
具体实施方式
下面详细地讨论了本发明的各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅说明了制造和使用本发明的具体方式,而不用于限制本发明的范围。应该注意,为了简化的目的,在每个后续的附图中并不包括全部的元件标号。相反,与每个附图的描述最相关的元件标号包括在每个附图中。
图1A和图1B分别是根据本发明的实施例的具有模塑料106的封装件100的透视图和顶视图,模塑料106具有形成在其中的应力消除结构(SRS)110。封装件100具有衬底112,衬底112的一侧上具有模塑料106。模塑料106具有连接件开口104,连接件102设置在每个连接件开口104中。管芯108安装在衬底112中并且镶嵌或以其他方式设置在模塑料106中。在实施例中,管芯108位于模塑料106的中心区域中。模塑料106也具有靠近连接件102的阵列的内部拐角(interior corner)的一个或多个SRS110。SRS110是模塑料106内的腔。
模塑料106、衬底112和管芯108中的每个可以具有不同的热膨胀系数(CTE)。在应用模塑料106之后的封装件100的热处理可以引起不同的元件在热处理的加热的条件下以不同的速率膨胀(expand),从而可能会引起模塑料106形成裂缝。已经观察到应力引起的破裂在连接件102的阵列的内部拐角区最严重,连接件102的阵列的内部拐角区域在图1B中被识别为应力区域114。热应力趋于在应力区域114中引起破裂,尤其是在邻近的连接件开口104之间。模塑料106中的裂缝可以从模塑料106的顶面延伸至衬底112,从而使衬底112的表面上的迹线暴露并可能破裂。靠近应力区域114生成的SRS110消除模塑料106中的应力,从而减少模塑料106的破裂。
图2是根据实施例示出用于封装件100的衬底112的截面图。衬底112可以包括一个或多个衬底层202,衬底层202具有一个或多个导电元件206和一个或多个焊盘(land)204。虽然附图中示出了单个衬底112,但可以可选择地在包括多个衬底112的工件(未示出)上加工若干个衬底112,并且在随后的工艺步骤中可以分割工件。
导电元件206是连接焊盘204的金属通孔、迹线或其他导电部件。在实施例中,衬底112包括具有一个或多个焊盘204的一个或多个重分布层(RDL)(诸如介电层),焊盘204可以通过导电元件206进行电连接。在其他实施例中,衬底112是PCB、载具或其他结构。
图3是根据一些实施例示出在衬底112上安装管芯108的截面图。一个或多个管芯108可以安装在焊盘204上。虽然为了清楚的目的仅示出了单个管芯108的安装,但可以将任意数量的管芯108安装至焊盘204。在一些实施例中,管芯108通过球栅阵列中的焊球302、通过表面安装技术、引脚网格阵列、引线互连件、导电粘合剂、插座或其他合适的技术安装至焊盘204。
图4是根据实施例示出在衬底112的顶部上形成连接件102的截面图。在这样的实施例中,连接件102是形成在焊盘204上的焊球。在其他实施例中,连接件102是接触柱(studs)、柱形件、凸块或其他导电部件。
图5是在连接件102上方形成的模塑料106的截面图。在实施例中,模塑料106是非导电材料,诸如环氧化物、树脂或可模塑聚合物等。在这样的实施例中,应用的模塑料106基本上是液态的(诸如以环氧化物或树脂的形式),然后通过化学反应进行固化。在其他实施例中,模塑料106是应用为液体、胶体或可延展固体的紫外(UV)固化或热固化的聚合物。在另一个实施例中,模塑料106是无粘性干膜层。
在一个实施例中,提供模具,并且在应用和固化期间,模具保持并使模塑料106成形。例如,模具可以具有当应用时用于保持模塑料106材料的边界或其他部件。模具可以包括离型膜以帮助从模塑料106上分离模具。例如,在模塑料106是环氧化物或树脂的实施例中,离型膜用于防止模塑料106材料粘附至模具表面。
在实施例中,形成覆盖连接件102的模塑料106,并且管芯108具有暴露的顶面。在另一实施例中,模塑料106覆盖管芯108,并且在另一实施例中,在形成模塑料之后,通过模塑料106的表面暴露连接件102。
图6是根据实施例示出模塑料106的图案化的截面图。可以去除模塑料106的一部分以形成SRS110开口,在实施例中,SRS110开口是空的或不包括金属部件或连接件102。此外,从连接件102上方和周围去除模塑料106以形成连接件开口104。在实施例中,SRS110从模塑料106的顶面延伸穿过模塑料106。在这样的实施例中,每个SRS110均延伸至衬底112。在另一实施例中,SRS110部分地延伸穿过模塑料106,其中,部分模塑料106形成SRS110的最低表面或底面,使得部分模塑料106设置在SRS和衬底112之间。
在实施例中,通过激光烧蚀去除模塑料106以形成连接件开口104和SRS110。在这样的实施例中,激光用于通过烧除或烧蚀模塑料106来形成连接件开口104和SRS110。通过激光的功率、激光移动的速度或其他工艺因数来控制开口的深度。例如,激光的切割光束可以具有小于期望的连接件开口尺寸的宽度,并且激光可以通过在模塑料中切割通路来形成开口。由于模塑料比预期的连接件开口104的其他部分薄,因此激光在连接件102的中心部分上方以第一、较快的速度移动。激光可以在连接件102的边缘处以第二、较慢的速度移动,在连接件102的边缘处去除的模塑料的量较大,并且需要通过激光进行更深地切割以实现期望的深度。
在其他实施例中,图案化模塑料106,例如,通过蚀刻模塑料、通过在模塑料106是液态形式时模制模塑料106来成形、通过研磨或钻削或通过其他合适的工艺。
在实施例中,可以使用与形成连接件开口104相同的工艺形成SRS。因此,可以使用激光烧蚀形成SRS110。在另一个实施例中,在形成连接件开口104之前或之后,单独地形成SRS110。在这样的实施例中,可以使用与形成连接件开口104不同的技术形成SRS110。例如,在模制模塑料106期间形成连接件开口104,并且随后使用激光烧蚀形成SRS110。
在实施例中,连接件开口104和SRS110是圆形的并且形成为具有斜边,从而产生圆锥形形状。然而,连接件开口104和SRS110中的每个可以均具有非圆锥形形状。例如,连接件开口104可以形成为与连接件102的形状共形。在这样的实例中,可以在正方形或基本上正方形的连接件开口中设置正方形连接件。在实例中,SRS110可以是椭圆形的、不规则矩形或任何其他形状。此外,虽然单个SRS110示出为靠近连接件102的组设置,但是在实施例中,使用多个SRS110以有效地减小模塑料106中的应变。
图7是示出将封装连接件702应用至衬底112的截面图。在衬底112的底侧的焊盘204上形成一个或多个封装连接件702,从而产生配置为安装至另一个板、封装件、载具或PCB等的器件。在实施例中,封装连接件702是焊球。在其他实施例中,封装连接件702是凸块、接触柱、柱形件、焊盘网格阵列(LGA)元件、引脚或其他导电部件。
图8和图9是根据实施例示出将第二封装件802应用至封装件100的截面图。例如,第二封装件802具有衬底808,诸如中介板、封装衬底、另一个管芯或载具等,衬底808具有通过安装件806(诸如粘合剂、底部填充物、焊球网格等)的方式安装在其上的一个或多个管芯804。一个或多个封装安装件812沿着第二封装件802的底面设置。在实施例中,衬底808具有设置在诸如电介质、氧化物、树脂、PCB或其他电绝缘材料的绝缘层808中的一个或多个导电元件810。导电元件810设置在绝缘层808中并且将封装安装件812电连接至管芯804。
通过将连接件102与封装安装件812接触来使第二封装件802安装在封装件100上。在实施例中,连接件102和封装安装件812是焊球,并且通过回流焊球以形成接合点902来将第二封装件802安装至封装件100。在另一个实施例中,封装安装件802是接触柱、凸块或柱形件等,并且通过将封装连接件812焊接至封装件100,来将第二封装件802接合至封装件100。在又一个实施例中,第二封装件802通过焊盘网格阵列和焊盘、通过引脚和插座或通过其他导电结构连接至封装件100。
图10是根据实施例示出SRS110的结构的截面图。在实施例中,模塑料106位于诸如聚合物、氧化物或氮化物等的饰面层(finishing layer)1004上,并且具有介于约120μm和约140μm之间的厚度。饰面层1004位于诸如钝化层等的保护层1002上。
连接件开口104的底部宽度1008约等于或大于连接件102的宽度1006。在一些实施例中,SRS110具有与连接件开口104大约相同的尺寸或相同的形状。在实施例中,连接件宽度1006介于约170μm和约230μm之间,连接件开口底部宽度1008和SRS底部宽度介于约190μm和约250μm之间,并且连接件开口顶部宽度1010和SRS顶部宽度1016介于约370μm和约430μm之间。
SRS110与连接件开口104间隔开,从而使得在模塑料106表面形成期间的激光的布局中的任何未对准或误差均考虑在内。此外,SRS110与连接件开口104的间隔给连接件开口104周围的模塑料106提供了更高的强度。通过模塑料106的厚度、连接件开口104的间距、形成封装件100的结构的CTE确定SRS110的尺寸和间隔。具体地,SRS110与连接件开口104间隔开至少30μm的分隔距离。
在衬底112上提供模塑料106以部分防止衬底112的翘曲。SRS110的总表面积为模塑料106的表面积的约0.01%和约15%之间。在这样的实施例中,通过节约的用来形成SRS110的模塑料106的面积来确定SRS110的表面积。此外,每个SRS110的体积介于约8×10-6mm3和约5mm3之间。限制SRS110的体积和总表面积以防止模塑料106变弱并保持衬底支撑模塑料106。
图11A、图11B和图11C示出了涉及连接件102的阵列的SRS110布置的实施例的顶视图。如图11A所示,在实施例中,单个SRS110设置在管芯108(例如,参见图1A至图1B、图3至图9)和连接件102之间的连接件102阵列的内部拐角区域中,SRS110的尺寸或宽度小于连接件开口104的尺寸或宽度。在这样的实施例中,SRS110可以具有与连接件开口104相同的形状。
图11B示出了在管芯108(例如,参见图1A至图1B、图3至图9)和连接件102之间的连接件102阵列的内部拐角区域中设置的多个SRS110的实施例。示出的SRS110的尺寸或宽度小于连接件开口104的尺寸或宽度小于,但是可以使用其他尺寸和形状。图11C示出了在连接件102的阵列的内部拐角区域中和连接件102之间均设置的一个或多个SRS110的实施例。
图11D、图11E和图11F示出了根据实施例的SRS110的不同形状的顶视图。如图11D所示,在实施例中,SRS110可以具有设置在其中的两个以上的连接件102,SRS110的壁与连接件102分隔开并且两个连接件102之间的模塑料106中具有间隙或空间。图11E示出了SRS110是设置在管芯108(例如,参见图1A至图1B、图3至图9)和连接件102之间的连接件102的阵列的内部拐角区域中的部分环形的实施例。图11F示出了设置在管芯108(例如,参见图1A至图1B、图3至图9)和连接件102之间的连接件102的阵列的内部拐角区域中的角形的SRS110的实施例。应该注意,尽管本文中示出了具有部分环形或角形的SRS110的实施例,但是SRS110的形状可以是圆形、椭圆形、矩形、环形、三角形、菱形或其他规则或不规则的形状。
图12是根据实施例示出形成具有SRS的叠层封装结构的方法1200的流程图。在框1202中,提供了衬底,并且在框1204中,将一个或多个管芯附接至衬底。在框1206中,在衬底上形成连接件,并且在框1208中,应用模塑料。在框1210中,形成模塑料的表面,暴露出连接件并且形成一个或多个SRS。在框1212中,在管芯的相对侧的衬底上形成一个或多个安装件。在框1214中,将第二封装件应用至封装件并且第二封装件位于模塑料上方。
因此,根据实施例的一种器件包括:具有第一侧的衬底,其中,第一侧具有设置在其上的多个连接件和管芯;以及设置在第一侧上并且围绕多个连接件中的每个的模塑料。应力消除结构(SRS)设置在模塑料中,SRS包括位于模塑料中的与多个连接件中的每个分隔开的腔。
根据另一个实施例的一种器件包括:具有第一侧的第一封装件,其中,第一侧具有设置在其上的多个连接件;以及通过连接件安装在第一封装件上的第二封装件。模塑料设置在第一封装件的第一侧上以及第一封装件和第二封装件之间。多个应力消除结构(SRS)设置在模塑料中,多个SRS中的每个均包括位于模塑料中并且与多个连接件中的每个间隔开的不含金属的腔。
根据实施例的一种方法包括:在第一封装件的第一侧上以及第一封装件的第一侧上的多个连接件中的每个的周围均形成模塑料,以及在模塑料中形成多个应力消除结构(SRS),多个SRS中的每个均包括位于模塑料中并且与多个连接件中的每个间隔开的不含金属的腔。
尽管已经详细地描述了本发明的实施例及其优势,但应该理解,可以在不背离由所附权利要求限定的本发明的精神和范围的情况下,做出各种改变,替换和更改。例如,本领域普通技术人员将容易地理解,本文描述的许多特征、功能、工艺和材料可以在本发明的范围内作出变化。而并且,本申请的范围并不旨在限于说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域普通技术人员将容易从本发明的公开内容理解,根据本发明,可以利用现有的或今后开发的执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、物质组成、工具、方法或步骤。因此,所附权利要求旨在将这样的工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。
Claims (20)
1.一种半导体器件,包括:
衬底,具有第一侧,在所述第一侧上设置有多个连接件和管芯;
模塑料,设置在所述第一侧上并且围绕所述多个连接件中的每个;
多个开口,位于所述模塑料中,所述多个开口中的每一个开口均暴露出所述多个连接件中的相应连接件且均占有所述模塑料的顶面的第一表面积;以及
应力消除结构(SRS),设置在所述模塑料中,所述应力消除结构包括位于所述模塑料中并且与所述多个连接件中的每个分隔开的腔体,所述应力消除结构占有所述模塑料的所述顶面的第二表面积,所述第二表面积小于所述第一表面积。
2.根据权利要求1所述的器件,还包括:位于所述模塑料中的多个连接件开口,所述多个连接件中的每个均设置在所述多个连接件开口的相应的一个中,其中,所述应力消除结构与所述多个连接件开口分隔开。
3.根据权利要求1所述的器件,其中,所述应力消除结构设置在所述多个连接件和所述管芯之间。
4.根据权利要求1所述的器件,其中,所述应力消除结构具有圆锥形形状。
5.根据权利要求1所述的器件,其中,所述管芯设置在所述多个连接件的中心区域中,并且所述应力消除结构设置为邻近所述多个连接件的内部拐角区域。
6.根据权利要求1所述的器件,还包括:安装在所述衬底上方的封装件,所述模塑料设置在所述衬底和所述封装件之间,其中,所述多个连接件中的每个均在所述衬底和所述封装件之间延伸。
7.一种半导体器件,包括:
第一封装件,具有第一侧,在所述第一侧上设置有多个连接件;
第二封装件,通过所述连接件安装在所述第一封装件上;
模塑料,设置在所述第一封装件的第一侧上和所述第一封装件与所述第二封装件之间;以及
多个应力消除结构(SRS),设置在所述模塑料中,所述多个应力消除结构中的每个均包括位于所述模塑料中并且与所述多个连接件中的每个都间隔开的不含金属的腔体。
8.根据权利要求7所述的器件,还包括:安装至所述第一封装件的第一侧的管芯,所述多个连接件设置在所述管芯周围,所述多个应力消除结构中的每个位于所述多个连接件中的一个或多个与所述管芯之间。
9.根据权利要求7所述的器件,还包括:位于所述模塑料中的多个连接件开口,所述多个连接件中的每个均设置在所述多个连接件开口的相应的一个中,其中,所述多个应力消除结构中的每个均与所述多个连接件开口分隔开。
10.根据权利要求9所述的器件,其中,所述多个应力消除结构中的每个均具有与所述多个连接件开口中的一个相同的形状。
11.根据权利要求7所述的器件,其中,所述多个应力消除结构的至少一个具有圆锥形形状。
12.根据权利要求9所述的器件,其中,所述多个应力消除结构中的每个均与所述多个连接件开口中的每个间隔开至少30μm。
13.根据权利要求12所述的器件,其中,所述多个应力消除结构的总表面积为所述模塑料的表面积的0.01%和15%之间。
14.一种形成半导体器件的方法,包括:
在第一封装件的第一侧和所述第一封装件的第一侧上的多个连接件中的每个的周围形成模塑料;
在所述模塑料中形成多个开口,所述多个开口中的每一个开口均暴露出所述多个连接件中的相应连接件且均占有所述模塑料的顶面的第一表面积;以及
在所述模塑料中形成多个应力消除结构(SRS),所述多个应力消除结构中的每个均包括位于所述模塑料中并且与所述多个连接件中的每个间隔开的不含金属的腔体,每个应力消除结构均占有所述模塑料的所述顶面的第二表面积,所述第二表面积小于所述第一表面积。
15.根据权利要求14所述的方法,还包括:将管芯安装至所述第一封装件的第一侧,其中,形成所述模塑料包括在所述管芯周围形成模塑料。
16.根据权利要求15所述的方法,其中,所述多个连接件设置在所述管芯周围,并且所述多个应力消除结构中的每个均形成为邻近所述多个连接件的内部拐角区域以及形成在所述多个连接件的内部拐角区域与所述管芯之间。
17.根据权利要求14所述的方法,还包括:在所述模塑料中形成多个连接件开口,所述多个连接件中的每个均设置在所述多个连接件开口的相应的一个中,其中,所述多个应力消除结构中的每个均与所述多个连接件开口分隔开。
18.根据权利要求17所述的方法,其中,形成所述多个应力消除结构和形成所述多个连接件开口包括去除所述模塑料的一部分。
19.根据权利要求18所述的方法,其中,去除所述模塑料的一部分包括通过激光烧蚀去除所述模塑料的所述一部分。
20.根据权利要求14所述的方法,其中,所述多个应力消除结构中的每个均形成为具有包括正方形、圆形、椭圆形、矩形、环形、三角形、菱形或不规则多边形的形状。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/025,414 | 2013-09-12 | ||
US14/025,414 US9237647B2 (en) | 2013-09-12 | 2013-09-12 | Package-on-package structure with through molding via |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104465542A CN104465542A (zh) | 2015-03-25 |
CN104465542B true CN104465542B (zh) | 2018-02-16 |
Family
ID=52625392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410341681.8A Active CN104465542B (zh) | 2013-09-12 | 2014-07-17 | 具有模塑通孔的叠层封装结构 |
Country Status (3)
Country | Link |
---|---|
US (4) | US9237647B2 (zh) |
KR (1) | KR101640309B1 (zh) |
CN (1) | CN104465542B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9237647B2 (en) | 2013-09-12 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with through molding via |
US9627285B2 (en) | 2014-07-25 | 2017-04-18 | Dyi-chung Hu | Package substrate |
US10231338B2 (en) * | 2015-06-24 | 2019-03-12 | Intel Corporation | Methods of forming trenches in packages structures and structures formed thereby |
CN106910723B (zh) * | 2015-07-29 | 2019-05-24 | 三星半导体(中国)研究开发有限公司 | 半导体封装件和制造该半导体封装件的方法 |
US9871016B2 (en) * | 2015-07-29 | 2018-01-16 | Samsung Electronics Co., Ltd. | Semiconductor package |
KR20170044919A (ko) * | 2015-10-16 | 2017-04-26 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
KR102530537B1 (ko) | 2016-04-11 | 2023-05-10 | 삼성전자주식회사 | 반도체 패키지 |
TWI573232B (zh) * | 2016-05-18 | 2017-03-01 | 矽品精密工業股份有限公司 | 電子封裝件 |
US20180166426A1 (en) * | 2016-12-14 | 2018-06-14 | Nanya Technology Corporation | Semiconductor structure and a manufacturing method thereof |
KR102358323B1 (ko) | 2017-07-17 | 2022-02-04 | 삼성전자주식회사 | 반도체 패키지 |
US10861773B2 (en) * | 2017-08-30 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
KR102448238B1 (ko) * | 2018-07-10 | 2022-09-27 | 삼성전자주식회사 | 반도체 패키지 |
US11139282B2 (en) * | 2018-07-26 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and method for manufacturing the same |
US10825774B2 (en) | 2018-08-01 | 2020-11-03 | Samsung Electronics Co., Ltd. | Semiconductor package |
JP7080852B2 (ja) * | 2019-06-25 | 2022-06-06 | キヤノン株式会社 | 半導体モジュール、電子機器、及びプリント配線板 |
US11557491B2 (en) * | 2019-10-31 | 2023-01-17 | Nxp B.V. | Selective underfill assembly and method therefor |
CN111029304B (zh) * | 2019-11-22 | 2021-09-14 | 中国电子科技集团公司第十三研究所 | 抗振三维堆叠电路结构及其制备方法 |
US11963291B2 (en) | 2022-04-21 | 2024-04-16 | Nxp B.V. | Efficient wave guide transition between package and PCB using solder wall |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101268548A (zh) * | 2004-06-25 | 2008-09-17 | 德塞拉股份有限公司 | 微电子封装及其方法 |
US7633765B1 (en) * | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
TW201201290A (en) * | 2010-03-25 | 2012-01-01 | Stats Chippac Ltd | Integrated circuit packaging system with stacking option and method of manufacture thereof |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6403896B1 (en) * | 2000-09-27 | 2002-06-11 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
JP5501562B2 (ja) * | 2007-12-13 | 2014-05-21 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
US8143530B1 (en) * | 2010-09-17 | 2012-03-27 | Endicott Interconnect Technologies, Inc. | Liquid crystal polymer layer for encapsulation and improved hermiticity of circuitized substrates |
JP2013147979A (ja) | 2012-01-18 | 2013-08-01 | Hitachi Koki Co Ltd | エンジン及びエンジン作業機 |
JP2013149797A (ja) * | 2012-01-19 | 2013-08-01 | Denso Corp | 半導体パッケージ |
US8847369B2 (en) * | 2012-07-20 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging structures and methods for semiconductor devices |
US9237647B2 (en) | 2013-09-12 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with through molding via |
-
2013
- 2013-09-12 US US14/025,414 patent/US9237647B2/en active Active
-
2014
- 2014-07-17 CN CN201410341681.8A patent/CN104465542B/zh active Active
- 2014-09-03 KR KR1020140116880A patent/KR101640309B1/ko active IP Right Grant
-
2016
- 2016-01-07 US US14/990,547 patent/US9502387B2/en active Active
- 2016-11-18 US US15/356,268 patent/US9780076B2/en active Active
-
2017
- 2017-10-02 US US15/722,758 patent/US10008480B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7633765B1 (en) * | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
CN101268548A (zh) * | 2004-06-25 | 2008-09-17 | 德塞拉股份有限公司 | 微电子封装及其方法 |
TW201201290A (en) * | 2010-03-25 | 2012-01-01 | Stats Chippac Ltd | Integrated circuit packaging system with stacking option and method of manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
US20160118369A1 (en) | 2016-04-28 |
CN104465542A (zh) | 2015-03-25 |
US9502387B2 (en) | 2016-11-22 |
US9237647B2 (en) | 2016-01-12 |
US10008480B2 (en) | 2018-06-26 |
KR101640309B1 (ko) | 2016-07-15 |
US20150070865A1 (en) | 2015-03-12 |
US20180026014A1 (en) | 2018-01-25 |
US20170069605A1 (en) | 2017-03-09 |
KR20150030610A (ko) | 2015-03-20 |
US9780076B2 (en) | 2017-10-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104465542B (zh) | 具有模塑通孔的叠层封装结构 | |
CN106356340B (zh) | 半导体器件及其制造方法 | |
TWI500091B (zh) | 封裝一半導體裝置之方法及封裝裝置 | |
US10163711B2 (en) | Methods of packaging semiconductor devices including placing semiconductor devices into die caves | |
US10269619B2 (en) | Wafer level chip scale packaging intermediate structure apparatus and method | |
CN104952828A (zh) | 覆晶堆叠封装结构及其制作方法 | |
US8847369B2 (en) | Packaging structures and methods for semiconductor devices | |
CN107346766A (zh) | 整合扇出型封装及其制造方法 | |
CN105321828B (zh) | 封装方法 | |
TWI594382B (zh) | 電子封裝件及其製法 | |
KR20200106001A (ko) | 양면 볼 그리드 어레이 패키지를 위한 하부-충전의 제어 | |
TW201806090A (zh) | 封裝結構 | |
CN105990268B (zh) | 电子封装结构及其制法 | |
TWI553818B (zh) | 電子封裝模組之製造方法以及電子封裝模組結構 | |
TWI669797B (zh) | 電子裝置及其製法與基板結構 | |
TWI611523B (zh) | 半導體封裝件之製法 | |
CN104051399B (zh) | 晶圆级芯片尺寸封装中间结构装置和方法 | |
TW201405732A (zh) | 半導體封裝件及其製法 | |
CN109712941A (zh) | 衬底结构、包含衬底结构的半导体封装结构,以及制造半导体封装结构的半导体工艺 | |
CN107845610B (zh) | 基板结构及其制作方法 | |
US20170287840A1 (en) | Semiconductor package structure and method of fabricating the same | |
TWI694562B (zh) | 堆疊封裝結構及其製造方法 | |
JP6290987B2 (ja) | 半導体パッケージ基板及びその製造方法 | |
TW201413887A (zh) | 封裝基板與封裝結構之製法 | |
TWI441291B (zh) | 半導體封裝件及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |