TWI655714B - 封裝基板、封裝半導體裝置與其之封裝方法 - Google Patents

封裝基板、封裝半導體裝置與其之封裝方法 Download PDF

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Publication number
TWI655714B
TWI655714B TW103145548A TW103145548A TWI655714B TW I655714 B TWI655714 B TW I655714B TW 103145548 A TW103145548 A TW 103145548A TW 103145548 A TW103145548 A TW 103145548A TW I655714 B TWI655714 B TW I655714B
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Taiwan
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substrate
package substrate
opening
region
substrate core
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TW103145548A
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TW201535599A (zh
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侯皓程
陳玉芬
鄭榮偉
梁裕民
王宗鼎
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台灣積體電路製造股份有限公司
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Abstract

在一些實施方式中，一種半導體裝置之封裝基板包含一基板核心與置於基板核心上方之一材料層。封裝基板包含置於基板核心與材料層中之鍃孔開口。

Description

封裝基板、封裝半導體裝置與其之 封裝方法
本發明是有關於一種封裝基板。
半導體裝置被使用於不同的電子應用中，例如個人電腦、手機、數位相機、以及其他電子儀器，舉例而言。半導體裝置典型地由依序沉積絕緣或介電層、導電層與半導體層之材料於半導體基板上，且藉由顯影法圖案化不同材料層以形成電路構件與元件於其上而製作。
數打或數百個積體電路典型地被製造於在單一半導體晶圓上。藉由沿著切割線切割積體電路，各別晶粒被獨立開來。獨立的晶粒接著分別被以，舉例而言，多晶粒模組或其他類型之封裝體，而封裝。
藉由持續減少最小特徵尺寸，其容許於一給定面積內結合更多構件，半導體產業持續改善不同電子構件(亦即電晶體、二極體、電阻、電容等)之積集密度。這些較 小的電子構件亦需較小的封裝，其於一些應用中比以前之封裝使用更少的面積。
在一些實施方式中，一種半導體裝置之封裝基板包含一基板核心與置於基板核心上方之一材料層。封裝基板包含置於基板核心與材料層中之鍃孔開口。
在一些實施方式中，一種封裝半導體裝置包含封裝基板，包含一基板核心、置於基板核心上方之一材料層以及置於基板核心與材料層中之鍃孔開口。鍃孔開口包含槽區與耦合槽區之針孔區。積體電路耦合至封裝基板。
在一些實施方式中，一種半導體裝置之封裝方法包含提供封裝基板，包含基板核心、置於基板核心上方之材料層、以及置於基板核心與材料層中之鍃孔開口。方法包含耦合積體電路至該封裝基板。藉由鍃孔開口配置底部填材於封裝基板與積體電路之間。
100‧‧‧封裝基板
102‧‧‧基板核心
103‧‧‧基板
104a、104b‧‧‧導電材料、接點
106‧‧‧通孔
108a、108a’、108b、108b’、116a、116b、144‧‧‧絕緣材料
110a、110a’、110b、110b’‧‧‧貫穿結構
112a、112a’、112b、112b’‧‧‧接點
114‧‧‧開口
118‧‧‧導電凸塊、連接元件
120a‧‧‧第一側
120b‧‧‧第二側
122‧‧‧連接元件
130‧‧‧積體電路
140‧‧‧封裝半導體裝置
142‧‧‧底部填材
146‧‧‧填充物
150‧‧‧流程圖
152、154、156‧‧‧步驟
d1、d2、d3‧‧‧尺寸
從以下結合所附圖式所做的詳細描述，可對本揭露之態樣有更佳的了解。需注意的是，根據業界實務的標準做法，各種特徵不是按比例繪製。實際上，為了清楚討論起見，各種特徵的尺寸可任意放大或縮小。
第1圖至第6圖為根據本揭露一些實施方式之封裝基板之製程方法於不同製程階段的剖面圖。
第7圖為根據一些實施方式之封裝基板的剖面圖。
第8圖為根據一些實施方式之第7圖的封裝基板的上視圖。
第9圖至第11圖為根據本揭露一些實施方式之封裝基板之封裝方法於不同製程階段的剖面圖。
第12圖為根據一些實施方式之第11圖之部分封裝半導體裝置的更仔細視角。
第13A圖至第13C圖為根據一些實施方式之封裝基板之鍃孔開口的上視圖。
第14圖為根據一些實施方式之半導體裝置的封裝方法的流程圖。
以下的揭露提供了許多不同實施方式或範例，以實施所提供之標的之不同特徵。以下所描述之構件與安排的特定範例係用以簡化本揭露。當然這些僅為範例，並非用以做為限制。舉例而言，於描述中，第一特徵形成於第二特徵上方或上，可能包含第一特徵與第二特徵以直接接觸的方式形成的實施方式，亦可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施方式，如此第一特徵與第二特徵可能不會直接接觸。此外，本揭露可能會在各範例中重複參考數字及/或文字。這樣的重複係基於簡化與清楚之目的，以其本身而言並非用以指定所討論之各實施方式及/或配置之間的關係。
另外，在此說明中可能會使用空間相對用語，例如「下方(underlying)」、「下方(below)」、「較低(lower)」、「上方(overlying)」、「較高(upper)」等等，以方便說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了在圖中所繪示之方向外，這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上)，因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
本揭露之一些實施方式有關於半導體裝置之封裝基板、封裝半導體裝置之方法與其結構。封裝半導體裝置係利用新穎之封裝基板以封裝，而封裝基板之製作方法亦被揭露。封裝基板包含形成於其中之鍃孔開口，於此處更進一步被描述。
第1圖至第6圖為根據本揭露一些實施方式之封裝基板100之製程方法於不同製程階段的剖面圖。根據一些實施方式，封裝基板100包含一覆晶封裝基板。首先參照第1圖，其為一封裝基板100，其包含基板核心102。舉例而言，在一些實施方式中，基板核心102包含玻璃纖維、樹脂、填充物、其他材料與/或其組合。在一些實施方式中，基板核心102包含一或多個被埋於其中之被動元件(未繪示)。或者，基板核心102可包含其他材料或元件。
在一些實施方式中，封裝基板100包含導電材料104a與104b，置於基板核心102之每一側，如第1圖所繪示。導電材料104a與104b包含銅或銅合金，其例如包含大 約5微米至大約25微米之一厚度。或者，導電材料104a與104b可包含其他材料或尺寸。在一些實施方式中，封裝基板100不包含形成於其中之導電材料104a與104b，且導電材料104a與104b形成於基板核心102上。導電材料104a與104b可利用鍍膜(plating)、物理氣相沉積法(physical vapor deposition,PVD)、濺鍍(sputtering)、化學氣相沉積法(chemical vapor deposition,CVD)或其他方法形成。
導電材料104a與104b利用曝光顯影法(photolithography)製程圖案化，如第2圖所繪示。舉例而言，導電材料104a之圖案化可藉由形成一層光阻(未繪示)於導電材料104a上方，且將光阻層暴露於反射自或穿透一光罩(亦未繪示)之具所需圖案的光或能量下，其將顯影光罩之圖案轉換至光阻層。光阻層接著被顯影，且光阻層之被曝光(或未曝光，取決於光阻層包含正或負光阻)區域被灰化或蝕刻掉，留下殘留於導電材料104a上之圖案化光阻層。光阻層接著作為蝕刻製程之蝕刻遮罩，其將光阻之圖案轉移至導電材料104a，如第2圖所繪示。光阻層接著被移除。導電材料104b可利用相似之曝光顯影法圖案化，例如利用另一光阻層與光罩。
或者，在一些實施方式中，導電材料104a與/或104b可包含種子層。導電材料104a與/或104b被光阻層(未繪示)或其他材料所覆蓋，其利用曝光顯影法以圖案化成所需的圖案。一導電材料，例如銅或銅合金，利用電鍍法或 化學電鍍(electro-chemical plating,ECP)法而被鍍於被圖案化光阻層暴露之導電材料104a與/或104b。光阻層被去除，而包含種子層之導電材料104a與/或104b被區域性移除，其區域為在鍍膜製程中光阻層存在的地方。導電材料104a與104b包含複數個接點(contacts)，形成於基板核心102之每一側上，其例如提供基板核心102之電性連接。
複數個通孔(plated-through holes,PTHs)106形成於基板核心102中，亦繪示於第2圖中。通孔106包含導電材料，例如銅、銅合金或其他導體，且在一些實施方式中可包含屏障層、襯墊、種子層與/或填充材料。通孔106提供自基板核心102之一側至基板核心102之另一側的垂直電性連接。舉例而言，一些通孔106可耦合於基板核心102之一側的接點104a與基板核心102之相對一側之接點104b之間。通孔106之洞可例如由鑽孔(drilling)製程、曝光顯影、雷射製程或其他方法形成，而通孔106之洞可接著填滿導電材料。
在一些實施方式中，通孔106可於形成接點104a與104b之前形成。在其他的實施方式中，通孔106可於形成接點104a與104b之後形成。在這些實施方式中，通孔106可延伸穿過接點104a與104b，未繪示。舉例而言，通孔106之端點可延伸穿過接點104a與104b。在第2至6圖中僅繪示二通孔106；然而，可替代的，根據一些實施方式，幾打或幾百或多個通孔106可形成穿過封裝基板100。
複數個絕緣材料108a與108a’、貫穿結構110a與110a’、以及接點112a與112a’形成於接點104a與基板核心102上方，如第3圖所示。在一些實施方式中，貫穿結構110a與110a’與接點112a與112a’可包含互連層之互連連接。舉例而言，在一些實施方式中，接點104a、絕緣材料108a與108a’、貫穿結構110a與110a’、以及接點112a與112a’包含封裝基板100之增層。在一些實施方式中，貫穿結構110a與110a’以及接點112a與112a’包含銅或銅合金。在一些實施方式中，絕緣材料108a與108a’包含介電材料或絕緣膜，例如為Ajinomoto Fine-Techno公司提供之Ajinomoto增層膜(Ajinomoto build-up film,ABF)或一預浸料(亦即一種被預浸於樹脂或其他材料之塑膠材料)。或者，貫穿結構110a與110a’、接點112a與112a’與絕緣材料108a與108a’可包含由其他供應者提供之其他材料。
在一些實施方式中，可利用一附加製程或半附加製程以形成絕緣材料108a與108a’、貫穿結構110a與110a’、以及接點112a與112a’。舉例而言，首先，絕緣材料108a形成於接點104a與基板核心102上方。絕緣材料108a利用鑽孔製程圖案化以形成用於貫穿結構110a之圖案。一導電材料形成於圖案化絕緣材料108a中以形成貫穿結構110a。一導電材料形成於絕緣材料108a與貫穿結構110a上方，且導電材料利用顯影製程圖案化以形成接點112a。在一些實施方式中，在填滿圖案化絕緣材料108a與形成貫穿結構110a之製程中，導電材料可包含形成於絕緣 材料108a上方之多餘導電材料，使得不需多一附加沉積製程。絕緣材料108a’接著形成於絕緣材料108a與接點112a上方，且絕緣材料108a’被圖案化，其圖案用於貫穿結構110a’。一導電材料被形成於圖案化絕緣材料108a’中，形成貫穿結構110a’。一導電材料被形成於貫穿結構110a’與絕緣材料108a’上方，且導電材料被圖案化以形成接點112a’。在一些實施方式中，在填滿圖案化絕緣材料108a’與形成貫穿結構110a’之製程中，導電材料可包含形成於絕緣材料108a’上方之多餘導電材料，使得不需多一附加沉積製程。或者，絕緣材料108a與108a’、貫穿結構110a與110a’以及接點112a與112a’可利用其他方式形成，且可包含其他材料。舉例而言，在一些實施方式中，可利用一或多個鑽孔方式、消去蝕刻製程與/或鍍膜製程以形成絕緣材料108a與108a’、貫穿結構110a與110a’以及接點112a與112a’。
複數個絕緣材料108b與108b’、貫穿結構110b與110b’、以及接點112b與112b’形成於接點104b與基板核心102上方，且於基板核心102之相對側上，亦如第3圖所示。舉例而言，絕緣材料108b與108b’、貫穿結構110b與110b’、以及接點112b與112b’可與位於基板核心102另一側之絕緣材料108a與108a’、貫穿結構110a與110a’、以及接點112a與112a’包含相似的材料且可利用相似之方法形成。在一些實施方式中，接點104b、絕緣材料108b與108b’、貫穿結構110b與110b’、以及接點112b與112b’包含封裝基板100之互連層或增層。
封裝基板100之增層(即包含接點104a、絕緣材料108a與108a’、貫穿結構110a與110a’、以及接點112a與112a’之增層或包含接點104b、絕緣材料108b與108b’、貫穿結構110b與110b’、以及接點112b與112b’之增層)在此處，即在一些請求項中，亦被稱為置於基板核心102上方之材料層。在一些實施方式中，部分之開口114形成於部分置於基板核心102上方之至少一之材料層中，即置於基板核心102上方之部分至少一之增層中。
二絕緣材料108a、108a’、108b、108b’繪示於圖中之基板核心102的各一側；然而，可替代的，單一絕緣材料、無絕緣材料、或三或多個絕緣材料可形成於基板核心102的各一側上。類似的，其他數量，如零、一或三或多個，之貫穿結構層與/或接點層可包含於封裝基板100上。
舉例而言，根據一些實施方式，接點104a與104b、貫穿結構110a與110a’、接點112a與112a’、貫穿結構110b與110b’、以及接點112b與112b’包含封裝基板100之水平電性連接元件。舉例而言，在一些實施方式中，接點112a、112a’、112b與112b’可包含扇出(fan-out)區域，使得於基板核心102一側上的接點之足跡(footprint)散開或者較基板核心102另一側上的接點之足跡寬。另一例中，在一些實施方式中，接點112b’較接點112a’為寬。
根據本揭露之一些實施方式，至少一開口114形成於基板103中，其包含基板核心102與絕緣材料108a、108a’、108b、與108b’，如第4圖所示。在一些實施方式 中，開口114完全地延伸穿過封裝基板100，如第4圖所示。根據一些實施方式，開口114包含一鍃孔開口(spot-faced aperture)，其包含具有尺寸d1之直徑或寬度之第一區域與具有尺寸d2之直徑或寬度之第二區域。在一些實施方式中，具有尺寸d1之寬度之第一區域大於具有尺寸d2之寬度之第二區域。舉例而言，在一些實施方式中，具有尺寸d1之第一寬度為約二倍或大於具有尺寸d2之第二寬度。
舉例而言，在一些實施方式中，尺寸d1包含大約2毫米(mm)或更大，在一些實施方式中，尺寸d2包含大約1毫米或更小。另一例中，在一些實施方式中，尺寸d1包含大約2.26毫米，而尺寸d2包含大約0.5毫米(mm)。再另一例中，在一些實施方式中，尺寸d1為尺寸d2之4倍或更大。或者，開口114之尺寸d1與d2可包含其他值與其他相對值。
在一些實施方式中，開口114可更包含一第三尺寸，未繪示於第4圖(見第6圖)。在一些實施方式中，第三尺寸可大於尺寸d2且小於尺寸d1，亦未繪示。開口114可包含一互連區域，置於第一區域與第二區域之間，其中互連區域例如包含第三尺寸。
在一些實施方式中，開口114可利用鑽孔製程所形成。鑽孔製程可包含機械製程(即於封裝基板100中鑽孔)、雷射製程、微影製程或其他方式。開口114之第一區域可利用第一鑽頭形成，而開口114之第二區域可利用第二鑽頭形成，其中第二鑽頭例如小於第一鑽頭。在一些實施方式中，直徑或寬度具尺寸d1之開口114之第一區域包含一槽 區。槽區包含一底部填充槽，其適用於在置放底部填材製程時接受與保留底部填材，於此處進一步描述。在一些實施方式中，直徑或寬度具尺寸d2之開口114之第二區域包含一針孔區。舉例而言，針孔區耦合槽區。針孔區包含在置放底部填材製程時一底部填材之注射道，亦於此處進一步描述。在一些實施方式中，開口114之針孔區置於材料層中(即如第4圖之絕緣材料108a與108a’中)其置於基板核心102上方。
絕緣材料116a與116b形成於基板核心102之兩側，即分別於絕緣材料108a’與108b’以及接點112a’與112b’上方，如第5圖所示。舉例而言，在一些實施方式中，絕緣材料116a與116b包含止焊漆(solder resist)。部分之絕緣材料116a與116b自接點112a’與112b’上方移除，亦如第5圖所示。
複數個導電凸塊118形成於封裝基板100之第一側120a上，如第6圖所示。在一些實施方式中，導電凸塊118包含被包含於導電材料之複數個連接元件。根據一些實施方式，導電凸塊118包含複數個控制崩塌晶片連接(controlled collapse chip connection,C4)凸塊。舉例而言，導電凸塊118可包含共熔合金(eutectic)材料如焊錫。舉例而言，導電凸塊118可利用落球(ball drop)製程或焊錫浸泡(solder bath)法形成。或者，導電凸塊118可包含其他材料或可利用其他方法形成。
舉例而言，在一些實施方式中，接點112a’包含接觸墊，置於導電凸塊118耦合至封裝基板100之第一側 120a上，如第6圖所示。接點112b’包含接觸墊，置於導電凸塊(未繪示於第6圖，見第7圖包含導電凸塊之連接元件122)可耦合至相對封裝基板100之第一側120a的第二側120b上，如第6圖所示。舉例而言，接點112a’與112b’置於基板103之相對側。
基板103(亦為封裝基板100)之第一側120a包含用以安裝一積體電路(見第9圖所繪示之積體電路130)於其上之一區域。基板103與封裝基板100之第二側120b包含用以耦合複數個連接元件(見第7圖所繪示之連接元件122)之一區域。舉例而言，在一些實施方式中，基板核心102亦包含第一側120a與相對於第一側120a之第二側120b。鍃孔開口114之包含尺寸d2的針孔區置於靠近封裝基板100、基板103或基板核心102的第一側120a，而舉例而言，在一些實施方式中，鍃孔開口114之包含尺寸d1的槽區置於靠近封裝基板100、基板103或基板核心102的第二側120b。
在一些實施方式中，鍃孔開口114之包含尺寸d1的槽區包含實質筆直之側壁，如第4至6圖所示。或者，鍃孔開口114之包含尺寸d1的槽區可包含具角度之側壁，如在第6圖之114”的幻像(即虛線內)所示。舉例而言，鍃孔開口114之槽區的側壁可向基板核心102之中心或朝基板核心之相對側凹陷。相似的，包含尺寸d2的針孔區之側壁可包含實質筆直之側壁或具角度之側壁(未繪示)。
在一些實施方式中，在形成絕緣材料108a、108a’、108b與108b’於基板核心102上後，基板核心102 與絕緣材料108a、108a’、108b與108b’包含基板103。舉例而言，在一些實施方式中，在形成絕緣材料108a、108a’、108b與108b’於基板核心102上後，基板103包含絕緣材料108a、108a’、108b與108b’。在一些實施方式中，鍃孔開口114之針孔區與/或槽區形成於基板103之絕緣材料108a、108a’、108b與108b’中。舉例而言，在第4至6圖的實施方式中，包含尺寸d2的針孔區形成於絕緣材料108a與108a’中，而包含尺寸d1的槽區形成於基板核心102與絕緣材料108b與108b’中。或者，針孔區亦可形成於部分之基板核心102內，如在第5圖之114’的幻像中。
在其他的實施方式中，鍃孔開口114之槽區形成於絕緣材料108b’內，而鍃孔開口114之針孔區形成於基板核心102與絕緣材料108a’內，如第7圖所示，其為根據一些實施方式之封裝基板100的剖面圖。或者，鍃孔開口114之槽區與針孔區可形成於絕緣材料108a、108a’、108b與108b’之不同組合中，與基板核心102之部分或整體厚度中。於另一例中，在一些實施方式中，包含鍃孔狀之開口114形成於封裝基板100中。
根據一些實施方式，在一底部填材之應用與在底部填材之固化製程中，封裝基板100被顛倒。第7圖繪示已被顛倒之封裝基板100，且鍃孔開口114包含尺寸d1之槽區靠近面朝上之封裝基板100或基板103之第二側120b。在第7、9、10與11圖中，為了簡化起見，包含接點112a’之導電材料未以圖案化繪示；然而舉例而言，在一些實施方式 中，導電材料層包含複數個接點112a’，如第2至6圖所示。接點112a’與112b以及絕緣材料108a與108b未繪示或包含於第7、9、10與11圖中；然而根據一些實施方式，這些元件與材料層可被包含或可不被包含於基板103中。
第8圖為根據一些實施方式之第7圖的顛倒封裝基板100的上視圖。舉例而言，第8圖所繪示之視角為封裝基板100的底視圖(亦即，當封裝基板100未顛倒時，連接元件122為面向下)。連接元件122以陣列排列形成於封裝基板100的下表面。舉例而言，在一些實施方式中，陣列排列包含球柵陣列封裝(ball grid array,BGA)。陣列可如第8圖所示完全佔滿，或者陣列可以不同圖案(未繪示)而部分佔據。
每一圖僅繪示一開口114；或者，複數個開口114可穿越形成於封裝基板100之表面。舉例而言，在第8圖中，單一開口114置於封裝基板100的實質中間區域。或者，開口114可置於封裝基板100的實質非中間區域，未繪示。在其他的實施方式中，一或多個包含鍃孔狀之開口114，其具有不同尺寸或寬度d1與d2，可穿越形成於基板103內之封裝基板100之表面，亦未繪示。於其他例中，三或多個等距或未等距之開口114可穿越形成於基板103之表面。
第9至11圖為根據一些實施方式之封裝一半導體裝置之方法於不同階段的剖面圖。第一，一積體電路130耦合至封裝基板100的第一側120a。積體電路130可耦合至置於封裝基板100之接點112a’(未繪示於第9至11圖；見第 6圖)上的連接元件118。舉例而言，積體電路130可藉由回焊製程耦合至連接元件118。舉例而言，積體電路130可利用覆晶接合製程或其他製程而耦合至封裝基板100。連接元件118提供積體電路130電性與機械性連接至封裝基板100。
封裝半導體裝置140包含封裝基板100、積體電路130與置於封裝基板100與積體電路130之間的連接元件118。積體電路130可包含距離封裝基板100之具有尺寸d3之支架(stand-off)高度。於其他例中，在一些實施方式中，具有尺寸d3之高度可包含大約60微米或更小。或者，尺寸d3可包含其他值。於其他例中，在一些實施方式中，尺寸d3可包含大約15微米至大約150微米。
在一些實施方式中，連接元件118可耦合至封裝基板100，而然後積體電路130耦合至封裝基板100。在其他的實施方式中，連接元件118可耦合至積體電路130，而然後封裝基板100耦合至積體電路130。在其他的實施方式中，連接元件118可皆耦合至積體電路130與封裝基板100，積體電路130可置於封裝基板100上，而連接元件118之一共熔合金(eutectic)材料被回焊以將積體電路130連接至封裝基板100。
在積體電路130接觸至封裝基板100後，一底部填材142置於開口114內，如第10圖所繪示。舉例而言，底部填材142被配置於開口114內之槽區中。在一些實施方式中，底部填材142包含環氧物(epoxy)或樹脂。在一些實施 方式中，底部填材142包含模製化合物。底部填材142可或者包含其他絕緣材料。底部填材142包含使用時為液態之材料，使得它可自開口114之槽區流進開口114之針孔區，如第11圖所繪示。底部填材142被配置入開口114之槽區而通過開口114之針孔區以於積體電路130與封裝基板100之間流動。底部填材142於連接元件118之間流動，實質填滿積體電路130與封裝基板100之間的空間，如第11圖所繪示。底部填材142填滿積體電路130與封裝基板100之間的空間，提供連接元件118之保護層。
底部填材142接著被固化。固化底部填材142可包含將封裝半導體裝置140加熱至一預定溫度，例如大約125度C至大約200度C於大約30分鐘至大約120分鐘。固化製程亦可包含其他溫度與其他持續時間。或者，舉例而言，底部填材142可利用紫外光、紅外能量或其他方法固化。
在底部填材142的固化製程後，在一些實施方式中，底部填材142置於開口114之至少一部分之針孔區。在一些實施方式中，底部填材142置於開口114之完整針孔區內，如第11圖所示。在一些實施方式中，在固化製程後，底部填材142不置於開口114之槽區中。在其他的實施方式中，底部填材142置於開口114之至少一部分之槽區，在一些實施方式中，如第11圖所示。舉例而言，因固化底部填材142時之收縮與/或彎月(meniscus)效應，底部填材142之上表面可包含彎曲形狀。
在一些實施方式中，在底部填材142放置製程與在底部填材142固化製程時，封裝半導體裝置140維持顛倒位置，其開口114之槽區面朝上。
第12圖為根據一些實施方式之第11圖之部分封裝半導體裝置140的更仔細視角。在一些實施方式中，底部填材142包含填充物146。舉例而言，填充物146可包含矽、碳化矽或碳。或者，填充物146可包含其他材料。有利地，在一些實施方式中，因為底部填材142與顛倒之封裝基板100以背朝上位置固化，被置於靠近積體電路130處之底部填材142之填充物146較被置於靠近封裝基板100處之底部填材142之填充物146多。這應用對積體電路130包含置於其上之低介電常數(k)絕緣材料144特別有利，其材料在一些實施方式中可包含有孔與/或易碎材料，舉例而言。
第13A、13B與13C圖為根據一些實施方式之封裝基板100(見第1至7、9至12圖之封裝基板100)之鍃孔開口114的上視圖，繪示不同之鍃孔開口114的結構與形狀。在一些實施方式中，包含尺寸d2之針孔區偏離包含尺寸d1之槽區的中心，如第13A圖所繪示。在一些實施方式中，包含尺寸d2之針孔區實質於包含尺寸d1之槽區的中心上，如第13B圖所繪示。在其他的實施方式中，開口114包含複數個包含尺寸d2之針孔區其可或不偏離包含尺寸d1之槽區的中心，如第13C圖所繪示。
第14圖為根據一些實施方式之半導體裝置的封裝方法的流程圖150。在步驟152中，一封裝基板100(亦 見第7圖)被提供，其包含基板核心102、置於基板核心102上方之材料層108a’與/或108b’、以及置於基板核心102與材料層108a’與/或108b’中的鍃孔開口114。在步驟154中，一積體電路130耦合至封裝基板100(見第9圖)。在步驟156中，一底部填材142藉由鍃孔開口114置於封裝基板100與積體電路130之間(見第10與11圖)。
在一些實施方式中，在配置底部填材142後，底部填材142被固化。在一些實施方式中，放置底部填材142更包含藉由鍃孔開口114之針孔區注射底部填材142。於其他例中，在一些實施方式中，提供封裝基板100包含提供一覆晶封裝。
本揭露之一些實施方法包含利用此處描述之新穎封裝基板100的半導體裝置之封裝方法。其他實施方式包含半導體裝置之封裝基板100。其他實施方式包含使用此處描述之封裝基板100以封裝之封裝半導體裝置。其他實施方式包含封裝基板100之製作方法。
本揭露之一些實施方式的好處包含提供新穎封裝基板100其包含此處描述之鍃孔開口114。藉由鍃孔開口114配置底部填材142防止沿著積體電路之一或二邊緣放置底部填材142，其防止放置不足之底部填材142於積體電路下、或防止過度填滿空間其造成底部填材142之龜裂(亦即溢出)。進一步地，底部填材142之重覆應用的需求可被避免。底部填材142的單通(one-pass)放置是可達成的，其結果為節省時間、節省成本以及改善或增加封裝製程流程與底 部填材142應用製程的每小時單位量(units per hour,UPH)。舉例而言，在一些實施方式中，製程產出量(process through-put)可增加，結果可改善製作與封裝效率。
因開口114之鍃孔狀，基板103對於開口114所需之凸塊面積與接線面積係最小化。較強之毛細效應可被達成，其更加改善產出量，造成開口114之極細針孔區。封裝基板100中之新穎之開口114包含較寬的槽區與較窄的針孔區。因開口114之針孔區的較強之毛細效應，快速底部填材注射可被達成。藉由鍃孔開口而放置底部填材亦導致底部填材之較快的擴散速度。
實施方式提供了積體電路的改善保護，其中因底部填材之填充物導致毗鄰至積體電路，封裝係以背向上位置被固化。靠近積體電路之被積累之填充物提供積體電路之材料層，以及積體電路與封裝基板之強化接點、接觸墊與凸塊底層金屬(under-ball metallization)較多的保護。
本揭露之實施方式於覆晶球柵陣列封裝(flip-chip ball grid array,FCBGA)封裝具有特別的好處，其舉例而言可具有超細積體電路尺寸與大約或小於60微米(即此處描述的包含尺寸d3)之低凸塊高度。
在一些實施方式中，一種半導體裝置之封裝基板包含一基板核心與置於基板核心上方之一材料層。封裝基板包含置於基板核心與材料層中之鍃孔開口。
在一些實施方式中，一種封裝半導體裝置包含封裝基板，包含一基板核心、置於基板核心上方之一材料層 以及置於基板核心與材料層中之鍃孔開口。鍃孔開口包含槽區與耦合槽區之針孔區。積體電路耦合至封裝基板。
在一些實施方式中，一種半導體裝置之封裝方法包含提供封裝基板，包含基板核心、置於基板核心上方之材料層、以及置於基板核心與材料層中之鍃孔開口。方法包含耦合積體電路至該封裝基板。藉由鍃孔開口配置底部填材於封裝基板與積體電路之間。
上述已概述數個實施方式的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到，其可輕易地利用本揭露做為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施方式相同之目的及/或達到相同的優點。熟悉此技藝者也應了解到，這類均等架構並未脫離本揭露之精神和範圍，且熟悉此技藝者可在不脫離本揭露之精神和範圍下，進行各種之更動、取代與潤飾。

Claims (9)

  1. 一種半導體裝置之封裝基板，包含：一基板核心；一材料層，置於該基板核心上方；以及一鍃孔(spot-faced)開口，置於該基板核心與該材料層中，其中該鍃孔開口延伸穿過該基板核心與該材料層，於該基板核心具有一第一直徑，且於該材料層具有一第二直徑，該第一直徑大於該第二直徑。
  2. 如請求項1所述之封裝基板，其中該鍃孔開口於該基板核心中包含一槽區，該鍃孔開口於該材料層中包含與該槽區相連通之一針孔區。
  3. 一種封裝半導體裝置，包含：一封裝基板，包含一基板核心，置於該基板核心上方之一材料層，以及置於該基板核心與該材料層中之一鍃孔開口，該鍃孔開口包含一槽區與耦合該槽區之一針孔區，該槽區延伸穿過該基板核心，且該針孔區延伸穿過該材料層，其中該針孔區之一直徑小於該槽區之一直徑；以及一積體電路，耦合至該封裝基板。
  4. 如請求項3所述之封裝半導體裝置，更包含一底部填材，置於該封裝基板與該積體電路之間。
  5. 如請求項4所述之封裝半導體裝置，其中該槽區包含比該針孔區之一寬度大之一較大寬度，且其中該底部填材更置於該鍃孔開口之該針孔區中。
  6. 如請求項4所述之封裝半導體裝置，其中該底部填材包含一填充物，且其中該底部填材於靠近該積體電路包含比靠近該封裝基板還多之該填充物。
  7. 如請求項3所述之封裝半導體裝置，更包含複數個連接元件，置於該積體電路與該封裝基板之間。
  8. 一種半導體裝置之封裝方法，該方法包含：提供一封裝基板，包含一基板核心，置於該基板核心上方之一材料層，以及置於該基板核心與該材料層中之一鍃孔開口，其中該鍃孔開口延伸穿過該基板核心與該材料層，於該基板核心具有一第一直徑，且於該材料層具有一第二直徑，該第一直徑大於該第二直徑；耦合一積體電路至該封裝基板；以及藉由該鍃孔開口配置一底部填材於該封裝基板與該積體電路之間。
  9. 如請求項8所述之方法，其中該鍃孔開口於該基板核心中包含一槽區，該鍃孔開口於該材料層中包含與該槽區相連通之一針孔區，其中耦合該積體電路至該封裝基板包含耦合該積體電路至該封裝基板靠近該鍃孔開口之該針孔區的一側，且其中配置該底部填材包含將該封裝基板靠近該鍃孔開口之該槽區的一側朝上放置，且經由該鍃孔開口之該槽區配置該底部填材，其中配置該底部填材更包含經由該鍃孔開口之該針孔區注射該底部填材。
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