TWI266403B - Method for fabricating semiconductor package substrate with opening penetrating therethrough - Google Patents

Method for fabricating semiconductor package substrate with opening penetrating therethrough

Info

Publication number
TWI266403B
TWI266403B TW092137578A TW92137578A TWI266403B TW I266403 B TWI266403 B TW I266403B TW 092137578 A TW092137578 A TW 092137578A TW 92137578 A TW92137578 A TW 92137578A TW I266403 B TWI266403 B TW I266403B
Authority
TW
Taiwan
Prior art keywords
penetrating
semiconductor package
package substrate
penetrating therethrough
circuit layer
Prior art date
Application number
TW092137578A
Other languages
Chinese (zh)
Other versions
TW200522326A (en
Inventor
Bin-Yang Chen
Hsin-Ku Huang
Xian-Zhang Wang
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW092137578A priority Critical patent/TWI266403B/en
Publication of TW200522326A publication Critical patent/TW200522326A/en
Application granted granted Critical
Publication of TWI266403B publication Critical patent/TWI266403B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor package substrate with an opening penetrating therethrough is proposed, wherein an inner substrate formed with a plurality of penetrating holes is provided, and at least a penetrating opening is formed therein by a drill pin. After a plating through hole is formed in the penetrating hole and a patterned circuit layer is formed on a prescribed surface of the inner substrate by a patterned process, a solder mask is formed on the patterned circuit layer. By the arrangement, it can prevent alignment errors of the drill pin and a shaping machine in the process of fabricating a substrate via forming the penetrating opening before the patterned circuit layer.
TW092137578A 2003-12-31 2003-12-31 Method for fabricating semiconductor package substrate with opening penetrating therethrough TWI266403B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092137578A TWI266403B (en) 2003-12-31 2003-12-31 Method for fabricating semiconductor package substrate with opening penetrating therethrough

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092137578A TWI266403B (en) 2003-12-31 2003-12-31 Method for fabricating semiconductor package substrate with opening penetrating therethrough

Publications (2)

Publication Number Publication Date
TW200522326A TW200522326A (en) 2005-07-01
TWI266403B true TWI266403B (en) 2006-11-11

Family

ID=38191569

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092137578A TWI266403B (en) 2003-12-31 2003-12-31 Method for fabricating semiconductor package substrate with opening penetrating therethrough

Country Status (1)

Country Link
TW (1) TWI266403B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413459B (en) * 2011-01-10 2013-10-21 Unimicron Technology Corp Circuit board and manufacturing method thereof and sensor
TWI465171B (en) * 2012-12-21 2014-12-11 Zhen Ding Technology Co Ltd Package circuit board, method for manufacturing asme, and package structure
CN104916595A (en) * 2014-03-14 2015-09-16 台湾积体电路制造股份有限公司 Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI413459B (en) * 2011-01-10 2013-10-21 Unimicron Technology Corp Circuit board and manufacturing method thereof and sensor
TWI465171B (en) * 2012-12-21 2014-12-11 Zhen Ding Technology Co Ltd Package circuit board, method for manufacturing asme, and package structure
CN104916595A (en) * 2014-03-14 2015-09-16 台湾积体电路制造股份有限公司 Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

Also Published As

Publication number Publication date
TW200522326A (en) 2005-07-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees