JP5237607B2 - 基板の製造方法 - Google Patents
基板の製造方法 Download PDFInfo
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- JP5237607B2 JP5237607B2 JP2007277438A JP2007277438A JP5237607B2 JP 5237607 B2 JP5237607 B2 JP 5237607B2 JP 2007277438 A JP2007277438 A JP 2007277438A JP 2007277438 A JP2007277438 A JP 2007277438A JP 5237607 B2 JP5237607 B2 JP 5237607B2
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Description
図9は、本発明の第1の実施の形態に係る基板の断面図である。
外部接続端子18は、貫通電極17の下端に設けられている。外部接続端子18は、基板10に設けられた貫通電極17と実装基板12に設けられたパッド13とを電気的に接続するための端子である。外部接続端子18としては、例えば、バンプ(例えば、はんだバンプ)を用いることができる。
パッド32,33及び配線34を備えた配線パターン21が形成される。なお、この段階では、隣接する基板形成領域Bに形成された配線パターン21は一体的に構成されているため、隣接する基板形成領域Bに形成されたパッド32は電気的に接続されている。
図27は、本発明の第2の実施の形態に係る基板の断面図である。図27において、第1の実施の形態の基板10と同一構成部分には同一符号を付す。
図30は、本発明の第3の実施の形態に係る基板の断面図である。
貫通電極92の上端面は、半導体基板91の表面91Aと略面一となるように構成されている。貫通電極92の上端は、後述するパッド115(配線パターン96の構成要素の1つ)と接続されている。貫通電極92の下端は、半導体基板91の裏面91Bから突出している。貫通電極92の下端面は、絶縁材93の下面93Bと略面一となるように構成されている。貫通電極92の下端は、外部接続用パッド101と接続されている。
12 実装基板
13,32,33,83,115,116 パッド
15,61 半導体デバイス
16,22,62,71,93 絶縁部材
16A,32A,93A 上面
16B,93B 下面
17,92 貫通電極
18,84 外部接続端子
19 透光性部材
21,96 配線パターン
25,41,91,121 半導体基板
25A,41A,91A,121A 表面
25B,41B,91B,121B 裏面
25C 側面
27,65 デバイス本体
27A 受光部
28,66 電極パッド
31,126 貫通孔
34,117 配線
36,45A,47A,68,97A,113,124A,127A 開口部
43 金属膜
45,47,124,127 レジスト膜
49,111 貫通部
75 基板積層体
76 導電部材
81 電子部品
82 実装基板
95 絶縁膜
97 ソルダーレジスト
99,103 拡散防止膜
101 外部接続用パッド
116A 接続面
A 隙間
B,G 基板形成領域
C,H 切断位置
E 突出量
F 幅
Claims (7)
- 半導体基板と、前記半導体基板の一方の面に設けられ、前記半導体基板と絶縁されたパッドと、前記パッドと対向する部分の前記半導体基板を貫通するように配置され、一方の端部が前記パッドと接続されると共に、前記半導体基板と絶縁された貫通電極と、を備えた基板の製造方法であって、
前記半導体基板に前記パッドの母材となる金属膜を形成する金属膜形成工程と、
前記パッドの形成領域に対応する部分の前記金属膜と対向する部分の前記半導体基板に貫通孔を形成する貫通孔形成工程と、
前記貫通孔に前記貫通電極を形成する貫通電極形成工程と、
前記半導体基板に前記貫通電極の側面を露出する貫通部を形成する貫通部形成工程と、
少なくとも前記貫通部を充填するように絶縁材を形成する絶縁材形成工程と、
前記絶縁材形成工程後に、前記金属膜をパターニングして前記パッドを形成するパッド形成工程と、を含み、
前記貫通電極は、複数設けられており、
前記貫通部形成工程では、少なくとも2つ以上の前記貫通電極の側面を露出するように前記貫通部を形成することを特徴とする基板の製造方法。 - 前記貫通電極形成工程では、前記金属膜を給電層とする電解めっき法により、前記貫通電極を形成することを特徴とする請求項1記載の基板の製造方法。
- 前記絶縁材形成工程では、前記貫通部を充填すると共に、前記一方の面とは反対側に位置する前記半導体基板の他方の面を覆うように前記絶縁材を形成することを特徴とする請求項1又は2記載の基板の製造方法。
- 前記絶縁材形成工程では、前記絶縁材を印刷法により形成することを特徴とする請求項1ないし3のうち、いずれか一項記載の基板の製造方法。
- 前記貫通電極形成工程では、前記パッドと接続されていない側の前記貫通電極の端部が前記半導体基板の他方の面から突出するように前記貫通電極を形成することを特徴とする請求項1ないし4のうち、いずれか一項記載の基板の製造方法。
- 前記金属膜形成工程の前に、前記半導体基板の一方の面に、前記パッドと電気的に接続される半導体デバイスを形成する半導体デバイス形成工程を設けたことを特徴とする請求項1ないし5のうち、いずれか一項記載の基板の製造方法。
- 前記パッド形成工程の後に、拡散防止膜が形成される接続面を除いてソルダーレジストを形成するソルダーレジスト形成工程を有することを特徴とする、請求項1ないし5のうち、いずれか一項記載の基板の製造方法。
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TW097140818A TW200926381A (en) | 2007-10-25 | 2008-10-24 | Method for producing substrate |
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JP5578808B2 (ja) * | 2009-05-15 | 2014-08-27 | 新光電気工業株式会社 | 半導体パッケージ |
JP5644242B2 (ja) | 2009-09-09 | 2014-12-24 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
JP2011187771A (ja) * | 2010-03-10 | 2011-09-22 | Omron Corp | 電極部の構造 |
EP2482310B1 (en) * | 2011-01-27 | 2020-09-23 | Sensirion AG | Through vias in a sensor chip |
JP5821284B2 (ja) * | 2011-05-30 | 2015-11-24 | セイコーエプソン株式会社 | 配線基板、赤外線センサー及び貫通電極形成方法 |
JP6031746B2 (ja) * | 2011-11-01 | 2016-11-24 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置及び電子機器 |
US9653401B2 (en) * | 2012-04-11 | 2017-05-16 | Nanya Technology Corporation | Method for forming buried conductive line and structure of buried conductive line |
EP2871152B1 (en) | 2013-11-06 | 2017-05-24 | Sensirion AG | Sensor device |
EP3001186B1 (en) | 2014-09-26 | 2018-06-06 | Sensirion AG | Sensor chip |
EP3032227B1 (en) | 2014-12-08 | 2020-10-21 | Sensirion AG | Flow sensor package |
JP2016029731A (ja) * | 2015-10-02 | 2016-03-03 | セイコーエプソン株式会社 | 回路基板及びセンサー |
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US6943056B2 (en) * | 2002-04-16 | 2005-09-13 | Renesas Technology Corp. | Semiconductor device manufacturing method and electronic equipment using same |
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US7307348B2 (en) * | 2005-12-07 | 2007-12-11 | Micron Technology, Inc. | Semiconductor components having through wire interconnects (TWI) |
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