TWI550729B - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
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- TWI550729B TWI550729B TW103123509A TW103123509A TWI550729B TW I550729 B TWI550729 B TW I550729B TW 103123509 A TW103123509 A TW 103123509A TW 103123509 A TW103123509 A TW 103123509A TW I550729 B TWI550729 B TW I550729B
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- semiconductor
- semiconductor substrate
- substrate
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 238
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 239000000758 substrate Substances 0.000 claims description 133
- 235000012431 wafers Nutrition 0.000 claims description 88
- 238000007789 sealing Methods 0.000 claims description 77
- 229920005989 resin Polymers 0.000 claims description 63
- 239000011347 resin Substances 0.000 claims description 63
- 238000010030 laminating Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 60
- 238000000227 grinding Methods 0.000 description 26
- 238000000926 separation method Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 10
- 238000002360 preparation method Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 239000011256 inorganic filler Substances 0.000 description 3
- 229910003475 inorganic filler Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Dicing (AREA)
Description
本申請案享有以日本專利申請案2014-52716號(申請日:2014年3月14日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
實施形態之發明係關於一種半導體裝置之製造方法及半導體裝置。
近年來,伴隨著通信技術或資訊處理技術之發展,要求半導體裝置之小型化及高速化。為應對此,於半導體裝置中推進以如下為目的之半導體封裝之開發,即,藉由積層有複數個半導體晶片之三維安裝而縮短零件間之配線之長度來應對動作頻率之增大,且提高安裝面積效率。
例如,於NAND(與非)型快閃記憶體等半導體裝置中,自小型化及高速化之觀點考慮,提出有於同一配線基板積層記憶體控制器與記憶體晶片之三維安裝構造。作為三維安裝構造,例如有利用TSV(Through Silicon Via,矽通孔)方式之積層構造。
於製造利用TSV方式之積層構造之半導體裝置時,藉由在導線架等金屬板上積層複數個半導體晶片,且使用貫通半導體晶片之貫通電極進行半導體晶片間之電性連接而形成積層體,並藉由底部填充樹脂密封半導體晶片間。其後,使積層體與配線基板貼合。進而,藉由填
充密封樹脂而密封積層體,於配線基板形成外部連接端子之後,進行切割而對應積層體來分離配線基板。
於利用底部填充樹脂之密封步驟中,為了不使用以密封某一積層體之底部填充樹脂擴散至鄰接之其他積層體之形成區域而於金屬板上設置有密封材料流出防止體,但如此會使金屬板之尺寸不得不相應地變大有設置該防止體之程度。進而,於三維安裝構造中,半導體裝置易於變厚。由此,為了縮小半導體裝置之尺寸,例如需要縮小設置積層體之基板之面積,並且使半導體裝置變薄。
實施形態之發明所欲解決之課題在於縮小半導體裝置之尺寸。
實施形態之半導體裝置之製造方法係如下方法,即,對半導體基板之表面格子狀地形成槽,於半導體基板上之由槽包圍之區域藉由積層複數個半導體晶片而形成積層體,且於由槽包圍之區域形成覆蓋複數個半導體晶片間及複數個半導體晶片之側面之第1密封樹脂層,對應積層體而分離半導體基板,以半導體晶片位於配線基板側之方式將積層體搭載於配線基板上,且於配線基板上形成密封積層體之第2密封樹脂層,對應積層體而分離配線基板,於形成第1密封樹脂層之後且分離配線基板之前,自半導體基板之形成有積層體之面之相反側之面沿厚度方向磨削半導體基板之一部分。
1‧‧‧半導體基板
10‧‧‧配線基板
11‧‧‧積層體
14‧‧‧密封樹脂層
15‧‧‧焊錫材料
16‧‧‧密封樹脂層
17‧‧‧密封樹脂層
18‧‧‧外部連接端子
21‧‧‧接著層
22a‧‧‧半導體晶片
22b‧‧‧半導體晶片
22c‧‧‧半導體晶片
23‧‧‧凸塊電極
24‧‧‧接著層
25‧‧‧貫通電極
26‧‧‧配線層
27‧‧‧連接配線
28‧‧‧電極墊
31‧‧‧固定帶
A-B‧‧‧線段
C1‧‧‧槽
X-Y‧‧‧線段
S1-1~S1-9、S2-1~S2-10‧‧‧步驟
圖1係表示半導體裝置之製造方法例之流程圖。
圖2A及B係用以說明半導體裝置之製造方法例之圖。
圖3A及B係用以說明半導體裝置之製造方法例之剖面圖。
圖4A及B係用以說明半導體裝置之製造方法例之剖面圖。
圖5A及B係用以說明半導體裝置之製造方法例之剖面圖。
圖6A及B係表示半導體裝置之構造例之圖。
圖7係表示半導體裝置之製造方法例之流程圖。
圖8A及B係用以說明半導體裝置之製造方法例之剖面圖。
圖9A及B係用以說明半導體裝置之製造方法例之剖面圖。
以下,參照圖式對實施形態進行說明。再者,圖式係模式性之圖,例如存在厚度與平面尺寸之關係、各層之厚度之比率等與實際情況不同之情形。又,實施形態中,對實質上相同之構成要素附上相同符號並省略說明。
圖1係表示半導體裝置之製造方法例之流程圖。圖1所示之半導體裝置之製造方法例至少包括:準備步驟(S1-1),準備半導體基板;積層步驟(S1-2),於半導體基板上藉由積層複數個半導體晶片而形成積層體;第1密封步驟(S1-3),於半導體基板上形成覆蓋複數個半導體晶片間及複數個半導體晶片之側面之密封樹脂層;第1分離步驟(S1-4),對應積層體而分離半導體基板;搭載步驟(S1-5),將積層體搭載於配線基板上;第2密封步驟(S1-6),形成密封積層體之密封樹脂層;磨削步驟(S1-7),磨削半導體基板之一部分;端子形成步驟(S1-8),形成外部連接端子;及第2分離步驟(S1-9),對應積層體而分離配線基板。參照圖式對上述步驟進一步進行說明。
參照圖2對準備步驟(S1-1)及積層步驟(S1-2)進行說明。圖2係用以說明半導體裝置之製造方法例之圖,圖2之(A)係俯視圖,圖2之(B)係沿圖2之(A)之線段X-Y之剖面圖。再者,方便起見,圖2之(A)中省略圖2之(B)之一部分構成要素而圖示。於此,作為一例,對在1片半導體基板1形成複數個積層體11之例進行說明。
準備步驟(S1-1)中,準備半導體基板1。半導體基板1於表面具有設置為格子狀之槽C1。槽C1具有防止底部填充樹脂之過度擴散之功
能、及用於形成積層體時之位置對準之作為對準標記之功能。槽C1例如針對每一積層體11而設置為格子狀,對應於鄰接之積層體11而設置之格子狀之槽C1如圖2之(B)所示般排列設置。槽C1之深度例如為大於等於50μm且小於等於100μm。槽C1較佳為如圖2之(A)所示般,設置於較半導體基板1之緣更靠內側。槽C1係例如藉由使用鑽石刀片等對半導體基板1進行磨削而形成。再者,槽C1之剖面形狀並未特別限定。再者,準備步驟(S1-1)中,亦可對於半導體基板1之表面形成槽C1。
作為半導體基板1,可使用例如矽基板。矽基板因槽C1之形成及使基板變薄等之加工較為容易,故而較佳。再者,半導體基板1亦可為再生基板。又,圖2之(A)中,半導體基板1之形狀為圓形,但並不限定於此,例如亦可為矩形狀。
積層步驟(S1-2)中,如圖2之(A)及圖2之(B)所示般,於半導體基板1上之由槽C1包圍之區域藉由積層複數個半導體晶片而形成積層體11。
於積層體11之形成中,首先,隔著接著層21而於半導體基板1貼合半導體晶片22a。作為接著層21,可使用例如聚醯亞胺等樹脂膜。接著層21於接著半導體晶片22a之後藉由熟化而硬化。
其次,積層複數個半導體晶片22b。於此,作為一例,形成7段半導體晶片22b之積層。半導體晶片22b具有貫通電極25。複數個半導體晶片22b隔著接著層24而貼合,且藉由設置於半導體晶片22b之表面之凸塊電極23及貫通半導體晶片22b之貫通電極25而相互電性連接。再者,亦可於半導體晶片22b之凸塊電極23之形成面之相反面設置電極墊,並經由電極墊及凸塊電極23而與其他半導體晶片22b電性連接。進而,最下層之半導體晶片22b隔著接著層24而貼合於半導體晶片22a,且藉由凸塊電極23及貫通電極25而電性連接於半導體晶片
22a。
作為半導體晶片22a及半導體晶片22b,可使用例如記憶體晶片等。作為記憶體晶片,可使用例如NAND型快閃記憶體等記憶元件。再者,亦可於記憶體晶片設置解碼器等電路。再者,亦可於半導體晶片22a設置貫通電極,並藉由貫通電極而使半導體晶片22a與半導體晶片22b電性連接。
作為凸塊電極23,可使用例如金凸塊、銅凸塊、或焊錫凸塊,作為焊錫凸塊,可使用錫-銀系、錫-銀-銅系之無鉛焊錫。
接著層24具有用以維持半導體晶片22b間隔之間隔件之功能。作為接著層24,可使用例如熱硬化性樹脂等。
進而,於最上層之半導體晶片22b上形成配線層26。進而於配線層26上形成電極墊28。
作為配線層26之具體例,列舉再配置半導體晶片22b之電極等之再配線層。配線層26為設置於半導體晶片22b上之再配線層,且具有連接配線27。連接配線27電性連接於最上層之半導體晶片22b之貫通電極25。
作為連接配線27及電極墊28,可使用例如銅、鈦、氮化鈦、鉻、鎳、金、或鈀等之單層或積層。
其次,於配線層26上配置半導體晶片22c。作為半導體晶片22c可使用例如覆晶型半導體晶片,該半導體晶片22c經由焊錫球等連接端子而電性連接於連接配線27。例如,可藉由熱壓接或還原氣體環境下之回流焊而將半導體晶片22c電性連接於連接配線27。作為半導體晶片22c,可使用例如介面晶片或控制器晶片。於例如半導體晶片22b為記憶體晶片之情形時,可對半導體晶片22c使用控制器晶片,藉由控制器晶片而控制對記憶體晶片之寫入及讀出。再者,半導體晶片22c較佳為小於半導體晶片22b。即,半導體晶片22c較佳為設置於半導體
晶片22b之一部分上。
藉由上述步驟而形成積層體11。如此,積層體11包括半導體基板1、設置於半導體基板1上之半導體晶片22a、積層於半導體晶片22a上之複數個半導體晶片22b、設置於半導體晶片22b上且具有連接配線27之配線層26、及設置於配線層26上之半導體晶片22c。半導體晶片22a藉由凸塊電極23而電性連接於半導體晶片22b,半導體晶片22b具有貫通晶片之貫通電極25,且藉由凸塊電極23及貫通電極25而相互電性連接,半導體晶片22c經由連接配線27而電性連接於半導體晶片22b。如此,可藉由使用TSV方式之積層構造之積層體11而縮小晶片面積,使連接端子數增多,因此可抑制連接不良等。
其次,參照圖3至圖5對第1密封步驟(S1-3)、第1分離步驟(S1-4)、搭載步驟(S1-5)、第2密封步驟(S1-6)、磨削步驟(S1-7)、端子形成步驟(S1-8)、及第2分離步驟(S1-9)進行說明。圖3至圖5係用以說明半導體裝置之製造方法例之剖面圖。
第1密封步驟(S1-3)中,如圖3(A)所示般,於半導體基板1上形成覆蓋積層體11之複數個半導體晶片間及複數個半導體晶片之側面之密封樹脂層14。例如,藉由使用探針等之分配器填充底部填充樹脂,藉此形成密封樹脂層14。此時,於密封樹脂層14之側面形成有凹面。
本實施形態之半導體裝置之製造方法例中,於半導體基板1之表面設置格子狀之槽C1,且於半導體基板1上之由槽C1包圍之區域形成積層體11,因此底部填充樹脂難以越過槽C1而擴散。藉此,例如可抑制底部填充樹脂甚至流出至鄰接之其他積層體11之形成區域。由此,於例如使用1片半導體基板1形成複數個積層體11之情形時,可縮短積層體11之形成區域之間隔,因此可增大積層體11之製取數。
第1分離步驟(S1-4)中,如圖3(B)所示般,對應積層體11而分離半導體基板1。例如,可藉由利用鑽石刀片等刀片切斷半導體基板1而分
離半導體基板1。再者,第1分離步驟(S1-4)中,較佳為一面將形成於半導體晶片之側面之密封樹脂層14(凹面部分)切斷,一面將半導體基板1切斷。又,此時較佳為亦將槽C1除去。藉此,較例如於設置有密封材料流出防止體之金屬板上形成積層體之情形而可縮小半導體裝置之寬度。
搭載步驟(S1-5)中,如圖4(A)所示般,於具有第1面及第2面之配線基板10上搭載積層體11。此時,以半導體晶片位於配線基板10之第1面之方式於配線基板10之第1面上搭載積層體11。例如亦可使用安裝機搭載積層體11。進而,積層體11藉由設置於電極墊上之焊錫材料15而與配線基板10電性連接。例如,可使用脈衝加熱法等接合配線基板10與積層體11。並不限定於此,亦可於將積層體11與配線基板10暫時接著之後,藉由利用回流焊並使用焊錫材料15進行正式接著而搭載積層體11。又,形成密封配線基板10與積層體11之間之密封樹脂層16。例如,可藉由填充底部填充樹脂而形成密封樹脂層16。再者,亦可不必設置密封樹脂層16。
作為配線基板10,可使用例如具有設置於表面之配線層之玻璃環氧化物等樹脂基板等。配線層具有連接墊,例如經由連接墊而與積層體11之電極墊電性連接。再者,配線基板10之第1面相當於圖4(A)之配線基板10之上表面,第2面相當於圖4(A)之配線基板10之下表面,配線基板10之第1面及第2面相互對向。
第2密封步驟(S1-6)中,如圖4(B)所示般,形成密封積層體11之密封樹脂層17。例如,可藉由填充密封樹脂而形成密封樹脂層17。圖4(B)中,以覆蓋半導體基板1之方式圖示密封樹脂層17,但並非限定於此,亦能以使半導體基板1之一部分露出之方式形成密封樹脂層17。作為密封樹脂,可使用含有SiO2等無機填充材料,例如將無機填充材料與絕緣性之有機樹脂材料等混合而成者,例如可使用與環氧樹
脂混合而成者。無機填充材料之含量占整體之80%~95%,具有調整密封樹脂層之黏度或硬度等之功能。使用上述密封樹脂之密封樹脂層17與半導體基板1之密接性較高,故而較佳。
磨削步驟(S1-7)中,如圖5(A)所示般,沿厚度方向至少磨削半導體基板1之一部分。例如,一面將配線基板10之第2面貼附並保持於固定用帶,一面進行噴砂處理或化學機械研磨(Chemical Mechanical Polishing:CMP)處理,藉此可磨削半導體基板1之一部分。於此,圖示自半導體基板1之形成有積層體11之面之相反側之面磨削密封樹脂層17之一部分及半導體基板1之一部分之例,但並不限定於此,亦可使用較例如半導體晶片22b厚之半導體晶片22a,並磨削至半導體晶片22a之一部分為止。
藉由磨削步驟(S1-7)磨削半導體基板1之一部分,藉此可使半導體基板1變薄。磨削步驟(S1-7)後之半導體基板1之厚度較佳為例如大於等於50μm且小於等於100μm。再者,進行磨削步驟(S1-7)之時序並未限定於此,至少於第1密封步驟(S1-3)之後且第2分離步驟(S1-9)之前進行即可。
端子形成步驟(S1-8)中,如圖5(B)所示般,於配線基板10之第2面形成外部連接端子18。例如,於配線基板10之第2面上塗佈助焊劑之後,於該面上搭載焊錫球,並放入至回流焊爐中使焊錫球熔融,而與配線基板10所具有之連接墊接合。其後,可藉由溶劑或純水清洗將助焊劑除去而形成外部連接端子18。
第2分離步驟(S1-9)中,如圖5(B)所示般,對應積層體11而分離配線基板10。例如,將配線基板10之第2面貼附於切割帶並利用切割環等保持配線基板10之後,藉由使用鑽石刀片等之切割而分離配線基板10。以上為半導體裝置之製造方法例之說明。
再者,本實施形態之半導體裝置之製造方法例之步驟內容及步
驟順序未必限定於上述步驟。又,除上述步驟以外,亦可設置例如刻印產品資訊之打印記步驟、或熱處理步驟、形成覆蓋密封體之遮蔽層之遮蔽層形成步驟等。
圖6表示經過上述製造步驟而製作之半導體裝置之構造例。圖6(A)係俯視圖,圖6(B)係沿圖6(A)之線段A-B之剖面圖。再者,圖6(A)中,方便起見而未圖示一部分構成要素。
圖6(A)及圖6(B)所示之半導體裝置包括:配線基板10,其具有相互對向之第1面及第2面;積層體11,其具備半導體基板1、及積層於半導體基板1上之複數個半導體晶片,以半導體晶片位於配線基板10之第1面側之方式搭載於配線基板10之第1面上;密封樹脂層14,其密封複數個半導體晶片間;密封樹脂層16,其密封配線基板10與積層體11之間;密封樹脂層17,其以使半導體基板1之至少一部分露出於配線基板10之第1面上且密封積層體11之方式設置;及外部連接端子18,其設置於配線基板10之第2面。
藉由使半導體基板1露出而可提高半導體裝置之散熱性,例如亦可經由半導體基板1而使半導體裝置冷卻。又,半導體基板1較薄而為例如大於等於50μm且小於等於100μm,密封樹脂層14具有與半導體基板1之側面連續地連接之側面。如此,本實施形態之半導體裝置之製造方法中,可使半導體基板變薄,並且可縮小半導體裝置之寬度,因此可縮小半導體裝置之尺寸。
本實施形態中,對一部分步驟與第1實施形態不同之半導體裝置之製造方法例進行說明。
圖7係表示半導體裝置之製造方法例之流程圖。圖7所示之半導體裝置之製造方法例包括:準備步驟(S2-1),準備半導體基板;積層步驟(S2-2),於半導體基板上藉由積層複數個半導體晶片而形成積層
體;第1密封步驟(S2-3),於半導體基板上以覆蓋複數個半導體晶片間及複數個半導體晶片之側面之方式形成密封樹脂層;第1磨削步驟(S2-4),磨削半導體基板之一部分;第1分離步驟(S2-5),對應積層體而分離半導體基板;搭載步驟(S2-6),將積層體搭載於配線基板;第2密封步驟(S2-7),形成密封積層體之密封樹脂層;第2磨削步驟(S2-8),藉由對密封積層體之密封樹脂層進行磨削而使半導體基板之一部分露出;端子形成步驟(S2-9),形成外部連接端子;及第2分離步驟(S2-10),對應積層體而分離配線基板。再者,本實施形態之半導體裝置之製造方法例之步驟內容及步驟順序未必限定於上述步驟
準備步驟(S2-1)相當於第1實施形態之準備步驟(S1-1)。積層步驟(S2-2)相當於積層步驟(S1-2)。第1密封步驟(S2-3)相當於第1密封步驟(S1-3)。第1分離步驟(S2-5)相當於第1分離步驟(S1-4)。搭載步驟(S2-6)相當於搭載步驟(S1-5)。第2密封步驟(S2-7)相當於第2密封步驟(S1-6)。端子形成步驟(S2-9)相當於端子形成步驟(S1-8)。第2分離步驟(S2-10)相當於第2分離步驟(S1-9)。再者,對於相當於第1實施形態之製造步驟之步驟,可適當引用對應之製造步驟之說明。參照圖式對與第1實施形態不同之內容之步驟進一步進行說明。
本實施形態之半導體裝置之製造方法例中,首先,與第1實施形態之半導體裝置之製造方法例同樣地,自準備步驟(S2-1)進行至第1密封步驟(S2-3)。
其次,參照圖8對第1磨削步驟(S2-4)進行說明。圖8係用以說明本實施形態之半導體裝置之製造方法例之剖面圖。
經過自準備步驟(S2-1)至密封步驟(S2-3)而形成之半導體裝置之一例如圖8之(A)所示般,包括半導體基板1、設置於半導體基板1上之積層體11、及覆蓋積層體11之複數個半導體晶片間及複數個半導體晶片之側面之密封樹脂層14。再者,對於與第1實施形態之半導體裝置
之構造相同之部分,可適當引用該半導體裝置之說明。
第1磨削步驟(S2-4)中,如圖8之(A)所示般將半導體基板1固定於固定帶31。此時,以積層體11位於固定帶31上之方式固定半導體基板1。作為固定帶31,可使用例如光硬化性之固定帶。光硬化性之固定帶因接著力較高,故而較佳。
其後,如圖之8(B)所示般,自半導體基板1之形成積層體11之面之相反側之面沿厚度方向磨削半導體基板1之一部分。例如藉由進行噴砂處理或CMP處理而磨削半導體基板1。
藉由第1磨削步驟(S2-4)而磨削半導體基板1之一部分,藉此可使半導體基板1變薄。第1磨削步驟(S2-4)後之半導體基板1之厚度例如較佳為大於等於50μm且小於等於100μm。
其後,自固定帶31剝離積層體11,與第1實施形態同樣地進行第1分離步驟(S2-5)與搭載步驟(S2-6)。
其次,參照圖9對第2密封步驟(S2-7)及第2磨削步驟(S2-8)進行說明。圖9係用以說明本實施形態之半導體裝置之製造方法例之剖面圖。
第2密封步驟(S2-7)中,如圖9(A)所示般形成密封積層體11之密封樹脂層17。例如,可藉由填充密封樹脂而形成密封樹脂層17。圖9(A)中,以覆蓋半導體基板1之方式圖示密封樹脂層17,但並不限定於此,亦能以使半導體基板1之一部分露出之方式形成密封樹脂層17。此外,適當引用第1實施形態之第2密封步驟(S1-6)之說明。
第2磨削步驟(S2-8)中,如圖9(B)所示般以使半導體基板1露出之方式磨削密封樹脂層17。於此,自半導體基板1之形成積層體11之面之相反側之面沿厚度方向磨削密封樹脂層17之一部分。再者,於第2磨削步驟(S2-8)中,亦可磨削半導體基板1之一部分。至於磨削方法等,可使用與第1實施形態之磨削步驟(S1-7)相同之方法,因此可適當
引用第1實施形態之磨削步驟(S1-7)之說明。
藉由使半導體基板1露出,而可提高半導體裝置之散熱性,例如亦可經由半導體基板1而使半導體裝置冷卻。再者,於本實施形態之半導體裝置之製造方法例中,亦可省略第2磨削步驟(S2-8)。
其後,與第1實施形態同樣地進行端子形成步驟(S2-9)及第2分離步驟(S2-10)。藉由以上步驟而可製造半導體裝置。對於第2實施形態之半導體裝置之構造,可適當引用圖6所示之半導體裝置之說明。
本實施形態之半導體裝置之製造方法中,藉由第1磨削步驟(S2-4)而於分離半導體基板1之前磨削半導體基板1之一部分,藉此可使半導體基板1變薄,並且可削減第2密封步驟(S2-7)中之密封樹脂之量,因此可較第1實施形態使半導體裝置更薄。如此,本實施形態之半導體裝置之製造方法中,可使半導體基板變薄,並且可縮小半導體裝置之寬度,因此可縮小半導體裝置之尺寸。
再者,各實施形態係作為例示而提出者,並未意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施,且可於不脫離發明之要旨之範圍進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或要旨中,並且包含於申請專利範圍所記載之發明及其均等之範圍內。
S1-1~S1-9‧‧‧步驟
Claims (5)
- 一種半導體裝置之製造方法,其係:對半導體基板之表面格子狀地形成槽;於上述半導體基板上之由上述槽包圍之區域藉由積層複數個半導體晶片而形成積層體;於由上述槽包圍之區域,形成覆蓋上述複數個半導體晶片間及上述複數個半導體晶片之側面之第1密封樹脂層;對應上述積層體而分離上述半導體基板;以上述半導體晶片位於配線基板側之方式於上述配線基板上搭載上述積層體;於上述配線基板上形成密封上述積層體之第2密封樹脂層;對應上述積層體而分離上述配線基板;及於形成上述第1密封樹脂層之後且分離上述配線基板之前,自上述半導體基板之形成有上述積層體之面之相反側之面沿厚度方向磨削上述半導體基板之一部分。
- 如請求項1之半導體裝置之製造方法,其中於形成上述第2密封樹脂層之後磨削上述半導體基板之一部分。
- 如請求項1之半導體裝置之製造方法,其中於分離上述半導體基板之前磨削上述半導體基板之一部分。
- 如請求項1至3中任一項之半導體裝置之製造方法,其中於分離上述半導體基板時,將上述第1密封樹脂層切斷,並且將上述半導體基板切斷。
- 一種半導體裝置,其包含:配線基板;積層體,其包括半導體基板、及積層於上述半導體基板上之 複數個半導體晶片,且以上述半導體晶片位於上述配線基板上之方式搭載於上述配線基板上;第1密封樹脂層,其包括自上述半導體基板之側面連續地連接之側面,且密封上述複數個半導體晶片間;及第2密封樹脂層,其使上述半導體基板之至少一部分露出並且密封上述積層體。
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