CN110299364A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110299364A
CN110299364A CN201810847601.4A CN201810847601A CN110299364A CN 110299364 A CN110299364 A CN 110299364A CN 201810847601 A CN201810847601 A CN 201810847601A CN 110299364 A CN110299364 A CN 110299364A
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China
Prior art keywords
chip
laminate
semiconductor
functional layer
semiconductor chip
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CN201810847601.4A
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English (en)
Inventor
河崎一茂
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Kioxia Corp
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Toshiba Memory Corp
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Publication of CN110299364A publication Critical patent/CN110299364A/zh
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Abstract

本发明的实施方式提供能够小型化及低成本化的半导体装置及其制造方法。本发明的实施方式的半导体装置具备：基础部件；第1积层体，包含交替积层在与所述基础部件的表面交叉的第1方向的第1半导体芯片与第2半导体芯片；及第2积层体，在沿所述基础部件的所述表面的第2方向与所述第1积层体排列配置，且包含交替积层在所述第1方向的其他第1半导体芯片与其他第2半导体芯片。所述第1积层体包含与所述基础部件连接的最下层的第1半导体芯片，所述第2积层体包含与所述基础部件连接的最下层的第2半导体芯片。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2018-55029号(申请日：2018年3月22日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
实施方式涉及半导体装置及其制造方法。
背景技术
例如存在如下半导体存储器件，其具有将积层在基板上的多个半导体存储器芯片树脂铸模的构造。此种半导体装置中，随着存储容量的大容量化，芯片的积层数增大，从而器件的尺寸变大，并且制造成本上升。
发明内容
本发明的实施方式提供能够小型化及低成本化的半导体装置及其制造方法。
本发明的实施方式的半导体装置具备：基础部件；第1积层体，包含交替积层在与所述基础部件的表面交叉的第1方向的第1半导体芯片与第2半导体芯片；及第2积层体，在沿所述基础部件的所述表面的第2方向与所述第1积层体排列配置，且包含交替积层在所述第1方向的其他第1半导体芯片与其他第2半导体芯片。所述第1积层体包含与所述基础部件连接的最下层的第1半导体芯片，所述第2积层体包含与所述基础部件连接的最下层的第2半导体芯片。
附图说明
图1及图2是表示实施方式的半导体装置的示意图。
图3及图4是表示实施方式的半导体装置的构成的示意图。
图5～图8是表示实施方式的半导体装置中所包含的半导体芯片的示意剖视图。
图9～图13是表示实施方式的半导体装置的制造方法的示意剖视图。
图14及图15是表示比较例的半导体装置的构成的示意图。
具体实施方式
以下，参照图式对实施方式进行说明。对图式中的相同部分附上相同编号并适当省略其详细说明，且对不同部分进行说明。另外，图式为示意性或概念性的图，各部分的厚度与宽度的关系、部分间的大小比率等未必与现实情况相同。此外，即便在表示相同部分的情况下，也存在根据图式的不同而不同地表示相互的尺寸或比率的情况。
进而，使用各图中所示的X轴、Y轴及Z轴对各部分的配置及构成进行说明。X轴、Y轴、Z轴相互正交，分别表示X方向、Y方向、Z方向。此外，存在将Z方向设为上方，且将其相反方向设为下方进行说明的情况。
图1及图2是表示实施方式的半导体装置1的示意图。图1是表示半导体装置1的构造的剖视图，图2是表示半导体装置1的上表面的示意俯视图。
半导体装置1为例如大容量的非易失性存储装置，包含基础部件10、积层体20A、及积层体20B。积层体20A及20B配置在基础部件10之上。
积层体20A及20B在沿基础部件10的上表面的X方向上排列配置。积层体20A及20B分别包含有在与基础部件10的上表面交叉的方向上，例如在Z方向上交替积层的多个半导体芯片CA与多个半导体芯片CB。积层体20A及20B例如树脂铸模在基础部件10之上。
积层体20A包含位于与基础部件10连接的最下层的半导体芯片CA。此外，积层体20B包含位于与基础部件10连接的最下层的半导体芯片CB。
如图1所示，半导体装置1进而包含逻辑芯片30。逻辑芯片30例如经由倒装芯片凸块(以下，FC凸块33)连接于基础部件10的下表面。
基础部件10为例如安装基板，包含连接焊垫13、配线15、通孔触点17。配线15设置在基础部件10的上表面侧，连接焊垫13设置在基础部件10的下表面侧。通孔触点17从基础部件10的下表面向上表面贯通，将连接焊垫13与配线15电性连接。
半导体芯片CA及CB分别包含通孔触点21及23。通孔触点21及23例如以将半导体芯片CA及CB各自的基板从背面向正面贯通的方式设置。通孔触点21及23分别与半导体芯片CA及CB的功能层(参照图3)连接。积层体20A及20B分别包含的半导体芯片CA及CB经由通孔触点21及23相互电性连接。
如图1所示，最下层的半导体芯片CA及CB例如分别经由连接凸块43而与配线15电性连接。即，连接凸块43将最下层的半导体芯片CA及CB的通孔触点21及23分别连接于配线15。
逻辑芯片30经由连接有FC凸块33的连接焊垫13及通孔触点17而与配线15电性连接。由此，积层体20A与逻辑芯片30之间、及积层体20B与逻辑芯片30之间电性连接。
半导体装置1进而包含配置在基础部件10的下表面的连接部件，例如焊料凸块50。焊料凸块50设置在连接焊垫13上，经由通孔触点17与配线15电性连接。焊料凸块50电性连接于例如与连接于积层体20A及20B的配线15不同的配线15。焊料凸块50例如与外部电路连接，将逻辑芯片30与外部电路电性连接。
如图2所示，积层体20A以在Z方向观察与逻辑芯片30的一部分重叠的方式配置。此外，积层体20B以在Z方向观察与逻辑芯片30的另一部分重叠的方式配置。
例如，积层体20A及20B的通孔触点21及23配置在逻辑芯片30的上方。由此，能够将积层体20A及20B与逻辑芯片30之间以最短距离连接。
图3及图4是表示实施方式的半导体装置1的构成的示意图。图3是表示半导体装置1的部分剖面的示意图。图4是表示半导体芯片CA及CB的端子配置的示意图。
如图3所示，半导体芯片CA包含半导体基板SS、功能层FLA、及接合层WBL。此外，半导体芯片CB包含半导体基板SS、功能层FLB、及接合层WBL。此外，在半导体芯片CA及CB的背面(与功能层FL为相反侧的面)分别设置有连接焊垫45或者连接焊垫47。
如图3所示，半导体芯片CA及CB以各自的接合层WBL对向的方式接合。积层体20A具有将贴合半导体芯片CA及CB而成的积层芯片SC1在Z方向积层的构造。积层体20B具有将贴合半导体芯片CA及CB而成的积层芯片SC2在Z方向积层的构造。
积层芯片SC1以具有隔着连接焊垫47设置在半导体芯片CA的背面上的连接凸块43的方式构成。而且，积层体20A以半导体芯片CB的背面(与功能层FLB为相反侧的面)与半导体芯片CA的背面经由连接凸块43、连接焊垫45及47连接的方式构成。
积层芯片SC2以具有隔着连接焊垫47设置在半导体芯片CB的背面的连接凸块43的方式构成。而且，积层体20B以半导体芯片CB的背面与半导体芯片CA的背面经由连接凸块43、连接焊垫45及47连接的方式构成。
如此，通过将半导体芯片CA与半导体芯片CB隔着接合层WBL贴合，与将所有芯片隔着连接凸块积层的情况相比，可缩小积层体20A及20B的尺寸(高度)。由此，可使半导体装置1小型化。
另外，图3中，省略贯通半导体芯片CA及CB的通孔触点21及23。此外，积层体20A及20B分别经由基础部件10的连接焊垫13、配线15及通孔触点17而与逻辑芯片30及焊料凸块50连接。
如图4所示，半导体芯片CA及CB分别具有数据端子0～7、及指令端子0～3。半导体芯片CA的数据端子及指令端子为例如通孔触点21，半导体芯片CB的数据端子及指令端子为例如通孔触点23。半导体芯片CA及CB的数据端子及指令端子与逻辑芯片30的数据端子及指令端子连接。
例如，数据端子及指令端子沿半导体芯片CA及CB各自的外缘排列配置为一列。此外，半导体芯片CA及CB以各自的数据端子及指令端子以最短距离对向的方式配置。在X方向上邻接的半导体芯片CA及CB具有沿相互对向的侧面配置的数据端子及指令端子，以在X方向上排列两者的数据端子，且排列两者的指令端子的方式配置。
进而，在贴合在半导体芯片CA之上的半导体芯片CB中，数据端子配置在与下层的数据端子连接的位置，指令端子配置在与下层的指令端子连接的位置。在贴合在半导体芯片CB之上的半导体芯片CA中也相同。
如此，在积层体20A及20B中，通过将数据端子及指令端子分别配置在特定区域，而积层体20A及20B与逻辑芯片30之间的连接变得容易。
例如，图14及图15所示的半导体装置2具有如下构造，即，在基础部件10之上配置积层体20A及20B，且在基础部件10的背面侧配置逻辑芯片30。积层体20A及20B均具有将积层芯片SC1在Z方向上积层的构造。此外，积层体20A及20B经由基础部件10的连接焊垫13、配线15及通孔触点17与逻辑芯片30连接。
如图15所示，在半导体装置2中，沿邻接的半导体芯片CA的相互对向的侧面配置的数据端子及指令端子的配列在Y方向上反转。因此，产生数据端子及指令端子在X方向上邻接配置的部分。因此，将积层体20A及20B的端子与逻辑芯片30的端子连接的配线较图4所示的半导体装置1变得更复杂。
即，无法使积层体20A及20B的端子配列与逻辑芯片30的端子配列一致，例如，必须将基础部件10的配线15变更为能够相互连接的图案。此外，作为逻辑芯片30，必须使用根据积层体20A及20B的端子配列而对端子配列进行了变更的专用芯片。因此，制造成本上升。
本实施方式的半导体装置1中，能够根据逻辑芯片30的端子配列而配列积层体20A及20B的数据端子及指令端子，从而可降低制造成本。
图5～图8是表示实施方式的半导体装置1中所包含的半导体芯片CA及CB的示意剖视图。例如，如果区分有无包含连接凸块43的构成，则半导体装置1包含4种半导体芯片CA1、CA2、CB1及CB2。
如图5～图8所示，接合层WBL包含接合焊垫51与绝缘膜53。接合焊垫51例如与功能层FLA或者FLB电性连接。绝缘膜53为例如氧化硅膜，保护功能层FLA或者FLB。功能层FLA及FLB包含例如NAND型存储器元件的存储单元阵列及周边电路。
如图5及图7所示，半导体芯片CA1及CB1在背面侧具有连接凸块43。另一方面，图6及图8所示的半导体芯片CA2及CB2在背面侧不具有连接凸块43。
积层体20A包含将半导体芯片CA1与半导体芯片CB2贴合而成的积层芯片SC1。积层体20B包含将半导体芯片CA2与半导体芯片CB1贴合而成的积层芯片SC2。
其次，参照图9～图13对实施方式的半导体装置1的制造方法进行说明。
图9～图13是依序表示半导体装置1的制造过程的示意剖视图。另外，图9～图13中也省略通孔触点21及23。
如图9所示，形成包含功能层FLA与功能层FLB的晶片100。功能层FLA及功能层FLB为例如形成在半导体基板SS之上的存储器元件。功能层FLA及功能层FLB沿半导体基板SS的表面交替配置。
进而，形成覆盖功能层FLA及FLB的接合层WBL。接合层WBL包含例如接合焊垫51及绝缘膜53。接合焊垫51为包含例如铜的金属层。绝缘膜53为例如氧化硅膜。
如图10所示，形成在半导体基板SS的背面具有连接凸块43的晶片110。晶片110为在晶片100的背面形成有连接凸块43者。连接凸块43例如经由连接焊垫47与半导体基板SS的背面连接。连接凸块43例如使用焊料材等连接部件形成。连接焊垫47为包含例如铜等的金属层。连接凸块43并不限定于焊料材，例如，也可使用较连接焊垫47为低熔点的金属材料。
此外，在半导体基板SS的背面上形成有间隔件SA。间隔件SA为例如树脂部件。通过配置间隔件SA，可将使用连接凸块43连接的积层芯片SC1或者SC2的相互的间隔保持于固定(参照图1)。
如图11所示，形成在半导体基板SS的背面具有连接焊垫45的晶片120。连接焊垫45为包含例如铜等的金属层。晶片120为在晶片100的背面形成有连接焊垫45者。
如图12所示，将晶片110与晶片120贴合。例如，以晶片110的接合层WBL与晶片120的接合层WBL对向的方式配置之后，使晶片110与晶片120接触，并通过例如在高温下加压而将两者贴合。
此时，通过晶片110的接合焊垫51与晶片120的接合焊垫51接触，此外两者的绝缘膜53接触而进行贴合。此外，晶片110与晶片120以功能层FLA与功能层FLB对向的方式接合。
如图13所示，将贴合的晶片110与晶片120通过例如切片机切断而切出积层芯片SC1及SC2。其后，通过在基础部件10之上隔着连接凸块43积层多个积层芯片SC1而形成积层体20A。同样，通过将多个积层芯片SC2隔着连接凸块43积层而形成积层体20B(参照图1)。
所述制造方法中，可通过将例如在X方向及Y方向中的至少1个方向交替配置功能层FLA与功能层FLB的2片晶片100贴合而形成积层芯片SC1及SC2。由此，能以低成本制造半导体装置1。例如，为了制作包含功能层FLA的晶片、及包含功能层FLB的晶片的2种晶片，必须使用2个掩膜组，但在本实施方式的制造方法中，可使用1个掩膜组制作积层芯片SC1及SC2。
对本发明的几个实施方式进行了说明，但这些实施方式是作为示例提出者，并未意图限定发明的范围。这些新颖的实施方式能够以其他各种形态实施，且可在不脱离发明要旨的范围进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或要旨中，并且包含在权利要求书中所记载的发明及其均等的范围。
[符号说明]
1、2：半导体装置
10：基础部件
13、45、47：连接焊垫
15：配线
17、21、23：通孔触点
20A、20B：积层体
30：逻辑芯片
33：FC凸块
43：连接凸块
50：焊料凸块
51：接合焊垫
53：绝缘膜
100、110、120：晶片
CA、CA1、CA2、CB、CB1、CB2：半导体芯片
FLA、FLB：功能层
WBL：接合层
SS：半导体基板
SA：间隔件
SC1：积层芯片
SC2：积层芯片

Claims (7)

1.一种半导体装置，具备：
基础部件；
第1积层体，包含交替积层在与所述基础部件的表面交叉的第1方向的第1半导体芯片与第2半导体芯片；及
第2积层体，在沿所述基础部件的所述表面的第2方向与所述第1积层体排列配置，且包含交替积层在所述第1方向的其他第1半导体芯片与其他第2半导体芯片；且
所述第1积层体包含与所述基础部件连接的最下层的第1半导体芯片，
所述第2积层体包含与所述基础部件连接的最下层的第2半导体芯片。
2.根据权利要求1所述的半导体装置，其中所述第1半导体芯片及所述第2半导体芯片分别具有半导体基板、及设置在所述半导体基板上的功能层，
所述第1积层体及所述第2积层体包含：第1接合部，使所述第1半导体芯片的功能层与所述第2半导体芯片的功能层对向接合；及第2接合部，使所述第1半导体芯片的半导体基板与所述第2半导体芯片的半导体基板对向接合。
3.根据权利要求2所述的半导体装置，其中所述第1半导体芯片及所述第2半导体芯片分别具有：接合焊垫，设置在所述功能层上；及连接焊垫，设置在所述半导体基板的与所述功能层为相反侧的背面侧；且
所述第1接合部包含将所述第1半导体芯片的接合焊垫与所述第2半导体芯片的接合焊垫直接连接的部分，
所述第2接合部包含将所述第1半导体芯片的连接焊垫与所述第2半导体芯片的连接焊垫经由连接部件连接的部分。
4.根据权利要求1至3中任一项所述的半导体装置，其进而具备与所述第1积层体及所述第2积层体电性连接的第3半导体芯片，
所述第3半导体芯片具有指令端子与数据端子，
所述第1积层体及所述第2积层体分别具有与所述指令端子连接的第1端子、及与所述数据端子连接的第2端子，
所述第1积层体的第1端子与所述第2积层体的第1端子在所述第2方向上排列配置，
所述第1积层体的第2端子与所述第2积层体的第2端子在所述第2方向上排列配置。
5.一种半导体装置的制造方法，其形成具有第1面及与所述第1面为相反侧的第2面的第1晶片，该第1面包含第1功能层、及与所述第1功能层交替排列配置的第2功能层，
形成具有第1面、及与所述第1面为相反侧的第2面，且具有配置在所述第2面上的多个连接部件的第2晶片，该第1面包含第1功能层、及与所述第1功能层交替排列配置的第2功能层，
形成晶片接合体，该晶片接合体是以将所述第1晶片的第1功能层与所述第2晶片的第2功能层接合，且将所述第1晶片的第2功能层与所述第1晶片的第1功能层接合的方式，贴合所述第1晶片的第1面与所述第2晶片的第1面而成，
将所述晶片接合体分割为多个第1积层芯片与多个第2积层芯片，这些第1积层芯片分别包含所述第1晶片的第1功能层、及与所述第1晶片的第1功能层接合的所述第2晶片的第2功能层，这些第2积层芯片分别包含所述第2晶片的第1功能层、及与所述第2晶片的第1功能层接合的所述第1晶片的第2功能层。
6.根据权利要求5所述的半导体装置的制造方法，其中所述第1积层芯片及所述第2积层芯片具有作为所述第1晶片的一部分的第1基板、及作为所述第2晶片的一部分的第2基板，
所述多个连接部件以所述第1积层芯片及所述第2积层芯片的各者在与所述第1功能层或者所述第2功能层为相反侧的所述第2基板的背面侧具有所述多个连接导体的一部分的方式配置。
7.根据权利要求5或6所述的半导体装置的制造方法，其中将包含多个所述第1积层芯片的第1积层体、及包含多个所述第2积层芯片的第2积层体形成在基础部件上。
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