TWI792193B - 半導體裝置之製造方法及半導體裝置 - Google Patents

半導體裝置之製造方法及半導體裝置 Download PDF

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TWI792193B
TWI792193B TW110106305A TW110106305A TWI792193B TW I792193 B TWI792193 B TW I792193B TW 110106305 A TW110106305 A TW 110106305A TW 110106305 A TW110106305 A TW 110106305A TW I792193 B TWI792193 B TW I792193B
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semiconductor wafer
semiconductor
mentioned
adhesive film
notch
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TW110106305A
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TW202224004A (zh
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大野天頌
徳渕圭介
友野章
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日商鎧俠股份有限公司
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Abstract

本發明提供一種可將設置於半導體晶圓之接著膜更恰當地分割之半導體裝置之製造方法及半導體裝置。本實施方式之半導體裝置之製造方法具備：於半導體晶圓之第1面設置接著膜之步驟，上述半導體晶圓具有第1面及位於該第1面之相反側之第2面，且於第1面具有半導體元件及與該半導體元件電性連接之凸塊。又，本製造方法具備：沿著半導體晶圓之分割區域，自接著膜側形成切口部之步驟。又，本製造方法具備：沿著切口部，將半導體晶圓單片化成半導體晶片之步驟。又，本製造方法具備：使半導體晶片之第1面與配線基板對向，使凸塊於接著膜內連接於配線基板之步驟。

Description

半導體裝置之製造方法及半導體裝置
本實施方式係關於一種半導體裝置之製造方法及半導體裝置。
作為將半導體晶片安裝至配線基板之方法，已知有覆晶連接。於覆晶連接中，為了連接部分之可靠性，於半導體晶片與配線基板之間填充樹脂。作為填充樹脂，例如，有時使用NCF(Non Conductive Film，非導電膜)等接著膜。例如，藉由將貼附有NCF之半導體晶圓切割，可獲得帶NCF之單片化之半導體晶片。又，藉由在切割後之半導體晶圓上貼附NCF並將NCF切斷，亦可獲得帶NCF之單片化之半導體晶片。
但，有時於半導體晶圓上之一部分會產生例如NCF未完全被分割或NCF蜿蜒地被分割等NCF之分割不良。
提供一種可將設置於半導體晶圓之接著膜更恰當地分割之半導體裝置之製造方法及半導體裝置。
本實施方式之半導體裝置之製造方法具備：於半導體晶圓之第1面設置接著膜之步驟，上述半導體晶圓具有第1面及位於該第1面之相反側之第2面，且於第1面具有半導體元件及與該半導體元件電性連接之凸塊。又，本製造方法具備：沿著半導體晶圓之分割區域，自接著膜側形成切口部之步驟。又，本製造方法具備：沿著切口部，將半導體晶圓單片化成半導體晶片之步驟。又，本製造方法具備：使半導體晶片之第1面與配線基板對向，使凸塊於接著膜內連接於配線基板之步驟。
根據上述構成，能夠提供一種可將設置於半導體晶圓之接著膜更恰當地分割之半導體裝置之製造方法及半導體裝置。
以下，參照圖式對本發明之實施方式進行說明。本實施方式並不限定本發明。於以下之實施方式中，配線基板之上下方向表示使設置半導體晶片之面朝上時之相對方向，有時與遵循重力加速度之上下方向不同。圖式係模式圖或概念圖，各部分之比率等未必與實物相同。於說明書與圖式中，對與上文關於已出現之圖式所敍述之要素相同之要素標註相同符號並適當省略詳細說明。
(第1實施方式) 圖1係表示第1實施方式之半導體裝置1之構成例之剖視圖。半導體裝置1具備配線基板10、半導體晶片20、30、31、接著層40、41、間隔晶片50、接著層60、金屬材料70、接著膜(接著層)80、接合線90及密封樹脂91。半導體裝置1例如係NAND(Not AND，反及)型快閃記憶體之封裝。
配線基板10可為包含配線層11與絕緣層15之印刷基板或插入式基板。配線層11例如可使用銅、鎳或其等之合金等低電阻金屬。絕緣層15例如可使用玻璃環氧樹脂等絕緣性材料。圖中，僅於絕緣層15之正面與背面設置有配線層11。但，配線基板10亦可具有將複數個配線層11及複數個絕緣層15積層而構成之多層配線構造。配線基板10例如亦可如插入式基板般具有貫通其正面與背面之貫通電極12。
於配線基板10之正面設置有阻焊層14，該阻焊層14設置於配線層11上。阻焊層14係用以保護配線層11免受金屬材料70之影響，從而抑制短路不良之絕緣層。於阻焊層14設置有開口部(未圖示)，配線層11之一部分及絕緣層15自開口部露出。
於配線基板10之背面亦設置有阻焊層14，該阻焊層14設置於配線層11上。於自阻焊層14露出之配線層11設置有金屬凸塊13。金屬凸塊13係為了將未圖示之其他零件與配線基板10電性連接而設置。
半導體晶片20例如係控制記憶體晶片之控制器晶片。於半導體晶片20之背面設置有半導體元件20a。半導體元件20a例如可為構成控制器之CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)電路。於半導體晶片20之背面設置有與半導體元件20a電性連接之電極柱21。電極柱21例如使用銅、鎳或其等之合金等低電阻金屬材料。
更詳細而言，半導體晶片20具有面F1及位於該面F1之相反側之面F2，於面F1具有半導體元件20a及與該半導體元件20a電性連接之電極柱21。又，半導體晶片20於面F1側經由電極柱21而與配線基板10連接。半導體晶片20包含半導體元件20a與半導體基板20b。半導體基板20b例如係矽基板。再者，並不限於矽，亦可使用矽以外之半導體。
於作為凸塊之電極柱21之周圍設置有金屬材料70。電極柱21經由金屬材料70而與配線層11電性連接。金屬材料70例如使用焊料、銀、銅等低電阻金屬材料。
於半導體晶片20之周圍、及半導體晶片20與配線基板10之間設置有作為樹脂層(底部填充膠)之接著膜80。接著膜80例如係使NCF(Non Conductive Film)等接著膜硬化而成，被覆並保護半導體晶片20之周圍。再者，接著膜80並不限於NCF，只要為包含熱固性樹脂之接著膜即可。
更詳細而言，接著膜80於半導體晶片20與配線基板10之間被覆電極柱21及金屬材料70。
於半導體晶片20之上，經由接著層40接著有半導體晶片30。半導體晶片30例如係包含NAND型快閃記憶體之記憶體晶片。於半導體晶片30之正面具有半導體元件30a。半導體元件30a例如可為記憶胞陣列及其周邊電路(CMOS電路)。記憶胞陣列亦可為將複數個記憶胞三維配置而成之立體型記憶胞陣列。又，於半導體晶片30上，經由接著層41接著有半導體晶片31。半導體晶片31例如與半導體晶片30同樣地，例如係包含NAND型快閃記憶體之記憶體晶片。半導體晶片30、31亦可為同一個記憶體晶片。圖中，除了作為控制器晶片之半導體晶片20以外，還積層有2個作為記憶體晶片之半導體晶片30、31。但，半導體晶片之積層數可為1層，亦可為3層以上。
更詳細而言，半導體晶片30、31包含半導體元件30a、31a與半導體基板30b、31b。半導體基板30b、31b例如係矽基板。再者，並不限於矽，亦可使用矽以外之半導體。
於半導體晶片20之周圍，於半導體晶片30與配線基板10之阻焊層14之間設置有間隔晶片50。間隔晶片50經由接著層60而接著於阻焊層14上。又，於間隔晶片50之上表面接著有接著層40，半導體晶片30經由接著層40而接著於間隔晶片50之上表面。
接合線90連接於配線基板10、半導體晶片30、31之任意焊墊。為了利用接合線90連接，半導體晶片30、31錯開相當於焊墊之量而積層。再者，半導體晶片20藉由電極柱21而覆晶連接，因此，未進行打線接合。但，半導體晶片20除了利用電極柱21連接以外，亦可進行打線接合。
進而，密封樹脂91將半導體晶片20、30、31、間隔晶片50、接著膜80、接合線90等密封。藉此，半導體裝置1將複數個半導體晶片20、30、31於配線基板10上構成為1個半導體封裝。
接下來，對半導體裝置1之製造方法進行說明。
圖2係表示第1實施方式之半導體晶圓W之一例之概略俯視圖。半導體晶圓W具備複數個晶片區域Rchip與複數個切割區域Rd。晶片區域Rchip及切割區域Rd係半導體晶圓W之正面上之區域。
於作為半導體晶片區域之晶片區域Rchip設置有電晶體、記憶胞陣列等半導體元件(例如，圖1所示之20a、30a、31a)。
作為分割區域之切割區域Rd係鄰接之晶片區域Rchip間之線狀區域，係藉由切割而被切斷之區域。切割區域Rd亦稱為切割線。藉由沿著切割區域Rd將半導體晶圓W切斷，半導體晶圓W以晶片區域Rchip為單位單片化，成為半導體晶片。
圖3A～圖3G係表示第1實施方式之半導體裝置1之製造方法之一例之剖視圖。圖3A～圖3G亦係表示圖2所示之半導體晶圓W之剖面之圖。Wa表示單片化前之半導體晶圓W中之半導體元件，Wb表示單片化前之半導體晶圓W內之半導體基板。
首先，如圖3A所示，於半導體晶圓W之面F1形成半導體元件Wa及電極柱21。即，半導體晶圓W具有面F1及位於該面F1之相反側之面F2，且於面F1具有半導體元件Wa及與該半導體元件Wa電性連接之電極柱21。半導體晶圓W之厚度例如約為30 μm。電極柱21之高度例如約為60 μm。金屬材料70之高度例如約為60 μm。
繼而，如圖3B所示，於半導體晶圓W之面F1貼附保護膠帶PT。
繼而，如圖3C所示，進行隱形切割(註冊商標)。即，於半導體晶圓W設置接著膜80之前，自半導體晶圓W之面F2側照射雷射光L，藉此，沿著切割區域Rd於半導體晶圓W內形成改質部(改質層)LM。改質部LM例如形成於半導體基板Wb內。又，龜裂Wc自改質部LM沿與面F1、F2垂直之方向伸展。再者，龜裂Wc亦可於之後進行之背面研削中伸展。
繼而，如圖3D所示，進行半導體晶圓W之背面研削，並將半導體晶圓W貼裝至切割膠帶DT。背面研削例如藉由CMP(Chemical Mechanical Polishing，化學機械拋光)法進行。半導體晶圓W之面F2例如被研磨至改質部LM被去除為止。
繼而，如圖3E所示，於半導體晶圓W之面F1貼附接著膜80。即，於半導體晶圓W之面F1設置接著膜80。接著膜80之厚度例如為約30 μm～約60 μm。
繼而，如圖3F所示，沿著半導體晶圓W之切割區域Rd，自接著膜80側形成切口部(槽)C。更詳細而言，沿著半導體晶圓W之切割區域Rd，自接著膜80側形成較半導體晶圓W之面F1(接著膜80之厚度)淺之切口部C。即，切口部C未到達半導體晶圓W。藉由將切割區域Rd上之接著膜80之一部分切斷，可輔助之後之步驟中之接著膜80之分割。其結果，可將設置於半導體晶片20之接著膜80更恰當地分割。又，切口部C之深度例如只要為接著膜80之厚度之約三分之一以上即可。又，藉由刀片B，形成切口部C。
繼而，如圖3G所示，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。更詳細而言，藉由以改質部LM為起點將半導體晶圓W劈開，而沿著切口部C將半導體晶圓W單片化成半導體晶片20。更詳細而言，藉由利用按壓構件(未圖示)自圖3G之下方將具有與半導體晶圓W之面F2接著之接著層之切割膠帶DT往上頂，而使切割膠帶DT拉伸(延展)。各半導體晶片20以沿著切割區域Rd內之龜裂Wc劈開之方式分離，因此，半導體晶圓W單片化成半導體晶片20。
又，更詳細而言，沿著切口部C將半導體晶圓W單片化成半導體晶片20，並且將接著膜80分割。即，藉由將切割膠帶DT延展，可與半導體晶片20之單片化大致同時地使接著膜80分割。如上所述，因利用切口部C將一部分接著膜80切斷，故可更容易地將接著膜80分割。
然後，將半導體晶片20安裝至配線基板10。即，使半導體晶片20之面F1與配線基板10對向，使電極柱21於接著膜80內連接於配線基板10。再者，對接著膜80進行硬化處理。又，將間隔晶片50貼裝於配線基板10，將半導體晶片30、31貼裝於間隔晶片50及半導體晶片20。進而，將接合線90與半導體晶片30、31接合。藉此，圖1所示之半導體裝置1完成。
如上所述，根據第1實施方式，沿著半導體晶圓W之切割區域Rd，自接著膜80側形成切口部C。又，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。因此，於半導體晶片20之單片化前，於接著膜80形成切口部C，用以輔助接著膜80之分割。又，切口部C自半導體晶圓W之面F1之上方觀察時，對應於晶片區域Rchip之外形而形成。藉此，於半導體晶片20之單片化時，可將貼附於半導體晶圓W之接著膜80更恰當地分割。
若不於接著膜80設置切口部C，則於圖3G之步驟中，接著膜80有可能未被分割。於該情形時，有可能視為接著膜80之不良而將半導體晶片20廢棄。
對此，於第1實施方式中，藉由在接著膜80設置切口部C，可抑制接著膜80未被分割，從而可抑制不良之產生。
又，於第1實施方式中，半導體晶片20之單片化乃藉由隱形切割進行。於該情形時，亦可於形成改質部LM之後且設置接著膜80之前，對自改質部LM向半導體晶圓W之面F1或面F2延伸之裂紋(龜裂Wc)之狀態進行檢查。因此，亦可於圖3C之步驟之後至圖3E之步驟之前之間，進行切割檢查。切割檢查係對切割後之半導體晶圓W之切斷狀態進行檢查。當進行隱形切割時，在切割檢查中，例如進行有無龜裂Wc存在、龜裂Wc之出現位置、是否筆直及有無微小缺損等之確認。
於貼附接著膜80之後單片化成半導體晶片20時，若為刀片切割、雷射剝蝕及電漿切割等其他切割，則通常於貼附接著膜80之後進行切割。例如，若為刀片切割，則有可能會於半導體晶片20中機械地出現損傷，從而產生碎屑。但，於已經貼附有接著膜80之情形時，難以進行切割檢查。
對此，於第1實施方式中，於貼附接著膜80之前進行隱形切割，因此，可於貼附接著膜80之前藉由確認龜裂Wc而進行切割檢查。因此，可容易保持半導體晶片20之品質。
又，於第1實施方式中，由於使用隱形切割，故藉由劈開將半導體晶圓W切斷。因此，切割部分(切割寬度)較刀片切割、雷射剝蝕及電漿切割等其他切割小，大致為零。
為了切割檢查，於半導體晶片20之單片化後將貼附於半導體晶圓W之接著膜80分割時，利用其他切割，例如如隱形切割般藉由使切割膠帶DT延展而將接著膜80分割即可。但，切割部分較大時，有可能於切割部分內，接著膜80蜿蜒地被分割(分割蜿蜒)。於該情形時，半導體晶片20之外周部之接著膜80之形狀等會不穩定，從而導致接著膜80之分割不良。
對此，於第1實施方式中，藉由隱形切割，可減小切割部分。藉此，可抑制接著膜80之分割蜿蜒。因此，可抑制接著膜80產生分割不良。
又，於第1實施方式中，藉由刀片B形成之切口部C未到達半導體晶圓W。因此，切割時會對半導體晶片20造成損傷之因素只有隱形切割。隱形切割對半導體晶片20造成之損傷較其他切割少，且不易產生碎屑。又，隱形切割由於不易產生碎屑，故可使抗折強度提高。如此，可使對半導體晶片20造成之損傷不變大，並且可將接著膜80更恰當地分割。
(第2實施方式) 圖4係表示第2實施方式之半導體裝置1之製造方法之一例之剖視圖。第2實施方式與第1實施方式之不同點在於，代替刀片B，藉由雷射剝蝕而形成切口部C。再者，於第2實施方式中，藉由隱形切割進行半導體晶片20之單片化。因此，圖4之步驟於與第1實施方式中之圖3A～圖3E相同之步驟之後進行。
將NCF貼附於半導體晶圓W之後(參照圖3E)，如圖4所示，藉由雷射剝蝕，形成切口部C。雷射剝蝕係藉由對材料表面照射光子密度較高之雷射光而使材料表面熔融及蒸發之方法。即，切口部C之形成方法可為任意方法。圖4之後之步驟可與第1實施方式中之圖3G之步驟相同。
第2實施方式之半導體裝置1之其他構成與第1實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第2實施方式之半導體裝置1可獲得與第1實施方式相同之效果。
(第3實施方式) 圖5A～圖5D係表示第3實施方式之半導體裝置1之製造方法之一例之剖視圖。第3實施方式與第1實施方式之不同點在於，代替隱形切割，藉由其他方法進行半導體晶片20之單片化。再者，圖5A～圖5D之步驟於與第1實施方式中之圖3A及圖3B相同之步驟之後進行。
將保護膠帶PT貼附於半導體晶圓W之面F1之後(參照圖3B)，如圖5A所示，進行半導體晶圓W之背面研削，並將半導體晶圓W貼裝至切割膠帶DT。
繼而，如圖5B所示，將接著膜80貼附於半導體晶圓W之面F1。
繼而，如圖5C所示，沿著半導體晶圓W之切割區域Rd，自接著膜80側形成切口部C。更詳細而言，藉由刀片B，形成切口部C。
再者，圖5A～圖5C之步驟可與第1實施方式中之圖3D～圖3F相同。
繼而，如圖5D所示，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。單片化例如藉由利用刀片切割、雷射剝蝕、電漿切割等切割將半導體晶圓W切斷而進行。即，單片化之方法可為任意方法。
第3實施方式之半導體裝置1之其他構成與第1實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第3實施方式之半導體裝置1可獲得與第1實施方式相同之效果。
(第4實施方式) 圖6係表示第4實施方式之半導體裝置1之製造方法之一例之剖視圖。第4實施方式與第3實施方式之不同點在於，代替刀片B，藉由雷射剝蝕而形成切口部C。再者，於第4實施方式中，藉由隱形切割以外之方法進行半導體晶片20之單片化。因此，圖6之步驟於與第1實施方式中之圖3A及圖3B相同之步驟、以及與第3實施方式中之圖5A及圖5B相同之步驟之後進行。又，第4實施方式亦係第2實施方式與第3實施方式之組合。
將接著膜80貼附於半導體晶圓W之面F1之後(參照圖5B)，如圖6所示，沿著半導體晶圓W之切割區域Rd，自接著膜80側形成切口部C。更詳細而言，藉由雷射剝蝕，形成切口部C。即，切口部C之形成方法可為任意方法。圖6之後之步驟可與第3實施方式中之圖5D之步驟相同。
第4實施方式之半導體裝置1之其他構成與第3實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第4實施方式之半導體裝置1可獲得與第1實施方式相同之效果。
(第5實施方式) 圖7係表示第5實施方式之半導體裝置1之構成例之剖視圖。第5實施方式與第1實施方式之不同點在於，於半導體晶片20之面F1之外周部設置缺口部Ca。
又，半導體晶片20具有缺口部Ca，該缺口部Ca設置於位於面F1與面F2之間之半導體晶片20之側面Fs與面F1交叉之角部(面F1之外周部)。即，設置於面F1側之半導體元件20a被削掉一部分，因此，面F1之面積小於面F2之面積。
又，藉由缺口部Ca，可抑制安裝後之應力(封裝應力)之影響。
如圖1所示，未設置缺口部Ca時，半導體元件20a之外周端部位於半導體晶片20之端面。半導體元件20a一般為多層膜。因此，例如，於切割等時會於半導體元件20a之外周端面(外周部)產生膜剝落及裂紋等損傷。此種損傷例如會因安裝後之封裝應力而延展至內部(中心部)。又，一般地，半導體晶片20之外周端面附近係半導體晶片20中封裝應力較大之區域。因此，位於半導體元件20a之外周端面之損傷容易延展至內部。
對此，於第5實施方式中，半導體元件20a之外周部處於自半導體晶片20之外周端面朝半導體晶片20之中心側分離之位置。藉此，即便於切割等單片化時於半導體元件20a中產生損傷，由於安裝後之封裝應力較低，故亦可抑制損傷之內部延展。
又，接著膜80與缺口部Ca之缺口面CF接觸。即，如圖7所示，接著膜80填充於缺口部Ca中。藉此，可於覆晶連接時使接著膜80之一部分分散至缺口部Ca，從而可抑制接著膜80於配線基板10上過度擴散。其原因在於，例如，若接著膜80與配線基板10上之接合墊接觸，則難以使接合線90與接合墊連接。
更詳細而言，缺口部Ca之缺口面CF具有與側面Fs不同之形狀或表面狀態。表面狀態例如包括表面粗糙度等。即，缺口面CF及側面Fs之切斷面互不相同。其原因在於，如下文中所說明般，缺口面CF及側面Fs利用不同之切斷方法切斷。
接下來，對半導體裝置1之製造方法進行說明。
圖8A及圖8B係表示第5實施方式之半導體裝置1之製造方法之一例之剖視圖。再者，於第5實施方式中，藉由隱形切割進行半導體晶片20之單片化。因此，圖8A及圖8B之步驟於與第1實施方式中之圖3A～圖3E相同之步驟之後進行。
將接著膜80貼附於半導體晶圓W之面F1之後(參照圖3E)，如圖8A所示，形成將接著膜80及半導體元件20a切斷之切口部C。更詳細而言，沿著切割區域Rd，自接著膜80側形成較半導體元件Wa深且較半導體晶圓W之面F2淺之切口部C。即，切口部C到達半導體晶圓W而將接著膜80及半導體元件Wa切斷，但未將半導體晶圓W(半導體基板Wb)完全切斷。因此，相對於第1實施方式而言，可將接著膜80更確實地切斷。又，於圖7所示之半導體晶片20形成寬度約為圖8A所示之刀片B之寬度(切割寬度)之一半之缺口部Ca。
繼而，如圖8B所示，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。再者，由於接著膜80及半導體元件Wa於圖8A之步驟中已經被切斷，故於圖8G之步驟中，半導體基板Wb被切斷。
又，更詳細而言，以切斷面具有與切口部C之剖面不同之形狀或表面狀態之方式將半導體晶圓W切斷，藉此，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。切口部C之剖面藉由利用刀片B進行之機械式切削而具有粗糙面。另一方面，半導體基板Wb之切斷面由於係半導體基板Wb(例如矽基板)之解理面，故而係單晶矽之晶面。因此，半導體基板Wb之切斷面係晶體缺陷相對較少且幾乎不存在凹凸之鏡面狀態之光滑面。又，半導體基板Wb之剖面相對於面F1、F2大致垂直。
再者，由於形成圖7所示之缺口部Ca，故較佳為半導體晶片20之單片化時之切割寬度較切口部C窄。
如上所述，根據第5實施方式，自接著膜80側形成較半導體元件Wa深之切口部C。藉此，可藉由切口部C將接著膜80更確實地切斷。其結果，可抑制接著膜80之分割不良及分割蜿蜒，從而可將接著膜80更恰當地分割。
又，於第5實施方式中，半導體元件20a藉由切口部C而切斷。
藉由隱形切割，使半導體晶圓W內部之晶體改質，藉由自改質部位延伸之龜裂將半導體晶圓W劈開。此處，於切割區域Rd中之半導體元件Wa中，例如設置有包含TEG(Test Element Group，測試元件組)焊墊等之器件圖案及配線圖案，因此，龜裂Wc難以延展至面F1之表面。於該情形時，面F1之表面中出現之龜裂Wc有可能於上述圖案區域蜿蜒。於龜裂Wc蜿蜒之狀態下，有可能於切割膠帶DT延展時，無法將半導體晶片20恰當地分割。進而，若蜿蜒之龜裂Wc延展至圖2所示之晶片區域Rchip，則有可能會導致半導體晶片20被破壞。如該等般，若面F1之龜裂Wc蜿蜒，則有可能會產生切割不良。
對此，於第5實施方式中，藉由切口部C，免除了龜裂Wc會蜿蜒之半導體元件20a。藉此，可抑制龜裂Wc蜿蜒，從而抑制產生切割不良。
第5實施方式之半導體裝置1之其他構成與第1實施方式之半導體裝置1之對應構成相同，因此省略其詳細說明。第5實施方式之半導體裝置1可獲得與第1實施方式相同之效果。
(第6實施方式) 圖9係表示第6實施方式之半導體裝置1之製造方法之一例之剖視圖。第6實施方式與第5實施方式之不同點在於，取代刀片B，而藉由雷射剝蝕形成切口部C。再者，於第6實施方式中，藉由隱形切割進行半導體晶片20之單片化。因此，再者，圖9之步驟於與第1實施方式中之圖3A～圖3E相同之步驟之後進行。
將接著膜80貼附於半導體晶圓W之面F1之後(參照圖3E)，如圖9所示，形成將接著膜80及半導體元件20a切斷之切口部C。更詳細而言，藉由雷射剝蝕，形成切口部C。即，切口部C之形成方法可為任意方法。圖9之後之步驟可與第5實施方式中之圖8B之步驟相同。
又，切口部C之剖面因雷射剝蝕而具有包含受熱而形成之熔解痕之面。另一方面，半導體基板Wb之切斷面由於為解理面，故為光滑面。
第6實施方式之半導體裝置1之其他構成與第5實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第6實施方式之半導體裝置1可獲得與第5實施方式相同之效果。
(第7實施方式) 圖10A及圖10B係表示第7實施方式之半導體裝置1之製造方法之一例之剖視圖。第7實施方式與第5實施方式之不同點在於，取代隱形切割，而藉由其他方法進行半導體晶片20之單片化。再者，圖10A及圖10B之步驟於與第1實施方式中之圖3A及圖3B相同之步驟、以及與第3實施方式中之圖5A及圖5B相同之步驟之後進行。
將接著膜80貼附於半導體晶圓W之面F1之後(參照圖5B)，如圖10A所示，形成將接著膜80及半導體元件20a切斷之切口部C。更詳細而言，藉由刀片B，形成切口部C。
繼而，如圖10B所示，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。單片化例如藉由利用刀片切割、雷射剝蝕、電漿切割等切割將半導體晶圓W切斷而進行。即，單片化之方法可為任意方法。再者，當藉由刀片切割進行半導體晶片20之單片化時，較佳為使用寬度較用於形成切口部C之刀片B窄之刀片。
又，切口部C之剖面藉由利用刀片B進行之機械式切削而具有粗糙面。另一方面，半導體基板Wb之切斷面根據上述切割方法而變化。再者，電漿切割係以非接觸之方式藉由化學蝕刻進行切斷。因此，半導體基板Wb之切斷面較刀片切割時之切斷面更光滑，但較隱形切割之切斷面更粗糙。
第7實施方式之半導體裝置1之其他構成與第5實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第7實施方式之半導體裝置1可獲得與第5實施方式相同之效果。
(第8實施方式) 圖11係表示第8實施方式之半導體裝置1之製造方法之一例之剖視圖。第8實施方式與第7實施方式之不同點在於，代替刀片B，藉由雷射剝蝕而形成切口部C。再者，於第8實施方式中，藉由隱形切割以外之方法進行半導體晶片20之單片化。因此，圖11之步驟於與第1實施方式中之圖3A及圖3B相同之步驟、以及與第3實施方式中之圖5A及圖5B相同之步驟之後進行。又，第8實施方式亦係第6實施方式與第7實施方式之組合。
將接著膜80貼附於半導體晶圓W之面F1之後(參照圖5B)，如圖11所示，形成將接著膜80及半導體元件20a切斷之切口部C。更詳細而言，藉由雷射剝蝕，形成切口部C。即，切口部C之形成方法可為任意方法。圖11之後之步驟可與第7實施方式中之圖10B之步驟相同。
第8實施方式之半導體裝置1之其他構成與第7實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第8實施方式之半導體裝置1可獲得與第7實施方式相同之效果。
(第9實施方式) 圖12A及圖12B係表示第9實施方式之半導體裝置1之製造方法之一例之剖視圖。第9實施方式與第5實施方式之不同點在於，形成切口部C之刀片B之前端形狀呈V字狀。再者，於第9實施方式中，藉由隱形切割進行半導體晶片20之單片化。因此，圖12A及圖12B之步驟於與第1實施方式中之圖3A～圖3E相同之步驟之後進行。
將接著膜80貼附於半導體晶圓W之面F1之後(參照圖3E)，如圖12A所示，形成將接著膜80及半導體元件20a切斷之切口部C。更詳細而言，藉由前端呈V字狀之刀片Ba，形成切口部C。於該情形時，圖7所示之缺口面CF之形狀成為相對於側面Fs傾斜之形狀。
繼而，如圖12B所示，沿著切口部C，將半導體晶圓W單片化成半導體晶片20。再者，於圖12B之步驟中，進行與第5實施方式中之圖8B大致相同之步驟。
如此，刀片B之前端形狀並不限於大致圓狀，亦可不同。再者，於圖12B所示之半導體晶片20之單片化時，亦可進行刀片切割。於該情形時，如圖7及圖12B所示，缺口面CF具有與側面Fs相同之表面粗糙度，但具有與側面Fs不同之形狀。
第9實施方式之半導體裝置1之其他構成與第5實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。第9實施方式之半導體裝置1可獲得與第5實施方式相同之效果。
(變化例) 圖13A～圖13G係表示變化例之半導體裝置1之製造方法之一例之剖視圖。變化例與第5實施方式之不同點在於，藉由雷射刻槽，形成圖7所示之缺口部Ca。
又，於變化例中，由於缺口部Ca藉由雷射刻槽形成，故切口部C既可如第5實施方式般到達半導體晶圓W，亦可如第1實施方式般不到達半導體晶圓W。以下，就對第1實施方式之步驟添加雷射刻槽之步驟之例進行說明。因此，圖13A～圖13G之步驟於與第1實施方式中之圖3A相同之步驟之後進行。
於半導體晶圓W之面F1形成半導體元件Wa及電極柱21之後(參照圖3A)，如圖13A所示，藉由雷射光L，形成使半導體基板Wb自半導體元件Wa露出之槽G。即，於半導體晶圓W設置接著膜80之前，沿著切割區域Rd，自半導體晶圓W之面F1側形成較半導體元件20a深且較半導體晶圓W之面F2淺之槽G。
槽G可於形成切口部C之前將難以切斷之半導體元件Wa切斷。因此，槽G發揮與第5實施方式中之圖8A所示之將半導體元件Wa切斷之切口部C大致相同之功能。因此，該槽G之一部分對應於圖7所示之缺口部Ca。
於圖13B～圖13G之步驟中，進行與第1實施方式中之圖3B～圖3G大致相同之步驟。於圖13F所示之例中，切口部C未到達半導體晶圓W，但以將半導體元件Wa拆除之方式形成有槽G。
再者，並不限於雷射刻槽，亦可藉由其他方法形成槽G。
變化例之半導體裝置1之其他構成與第5實施方式之半導體裝置1之對應構成相同，因此，省略其詳細說明。變化例之半導體裝置1可獲得與第5實施方式相同之效果。又，亦可將第1實施方式～第4實施方式及第6實施方式～第9實施方式與變化例之半導體裝置1組合。即，切口部C既可不到達半導體晶圓W，亦可到達半導體晶圓W。進而，切口部C之形成及半導體晶片20之單片化之方法可為任意方法。
對本發明之若干實施方式進行了說明，但該等實施方式係作為示例而提出，並不意圖限定發明之範圍。該等實施方式能夠以其他多種形態實施，可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施方式或其變化包含於發明之範圍或主旨中，且同樣包含於申請專利範圍所記載之發明及其均等之範圍內。 相關申請案之引用
本申請案基於2020年08月19日提出申請之先前之日本專利申請第2020-138825號之優先權而主張優先權利益，其全部內容藉由引用而包含於本文中。
1:半導體裝置 10:配線基板 11:配線層 12:貫通電極 13:金屬凸塊 14:阻焊層 15:絕緣層 20:半導體晶片 20a:半導體元件 20b:半導體基板 21:電極柱 30:半導體晶片 30a:半導體元件 30b:半導體基板 31:半導體晶片 31a:半導體元件 31b:半導體基板 40:接著層 41:接著層 50:間隔晶片 60:接著層 70:金屬材料 80:接著膜 90:接合線 91:密封樹脂 B:刀片 Ba:刀片 C:切口部 Ca:缺口部 CF:缺口面 DT:切割膠帶 F1:面 F2:面 Fs:側面 G:槽 L:雷射光 LM:改質部 PT:保護膠帶 Rchip:晶片區域 Rd:切割區域 W:半導體晶圓 Wa:半導體元件 Wb:半導體基板 Wc:龜裂
圖1係表示第1實施方式之半導體裝置之構成例之剖視圖。  圖2係表示第1實施方式之半導體晶圓之一例之概略俯視圖。  圖3A係表示第1實施方式之半導體裝置之製造方法之一例之剖視圖。  圖3B係表示繼圖3A後之半導體裝置之製造方法之一例之剖視圖。  圖3C係表示繼圖3B後之半導體裝置之製造方法之一例之剖視圖。  圖3D係表示繼圖3C後之半導體裝置之製造方法之一例之剖視圖。  圖3E係表示繼圖3D後之半導體裝置之製造方法之一例之剖視圖。  圖3F係表示繼圖3E後之半導體裝置之製造方法之一例之剖視圖。  圖3G係表示繼圖3F後之半導體裝置之製造方法之一例之剖視圖。  圖4係表示第2實施方式之半導體裝置之製造方法之一例之剖視圖。  圖5A係表示第3實施方式之半導體裝置之製造方法之一例之剖視圖。  圖5B係表示繼圖5A後之半導體裝置之製造方法之一例之剖視圖。  圖5C係表示繼圖5B後之半導體裝置之製造方法之一例之剖視圖。  圖5D係表示繼圖5C後之半導體裝置之製造方法之一例之剖視圖。  圖6係表示第4實施方式之半導體裝置之製造方法之一例之剖視圖。  圖7係表示第5實施方式之半導體裝置之構成例之剖視圖。  圖8A係表示第5實施方式之半導體裝置之製造方法之一例之剖視圖。  圖8B係表示繼圖8A後之半導體裝置之製造方法之一例之剖視圖。  圖9係表示第6實施方式之半導體裝置之製造方法之一例之剖視圖。  圖10A係表示第7實施方式之半導體裝置之製造方法之一例之剖視圖。  圖10B係表示繼圖10A後之半導體裝置之製造方法之一例之剖視圖。  圖11係表示第8實施方式之半導體裝置之製造方法之一例之剖視圖。  圖12A係表示第9實施方式之半導體裝置之製造方法之一例之剖視圖。  圖12B係表示繼圖12A後之半導體裝置之製造方法之一例之剖視圖。  圖13A係表示變化例之半導體裝置之製造方法之一例之剖視圖。  圖13B係表示繼圖13A後之半導體裝置之製造方法之一例之剖視圖。  圖13C係表示繼圖13B後之半導體裝置之製造方法之一例之剖視圖。  圖13D係表示繼圖13C後之半導體裝置之製造方法之一例之剖視圖。  圖13E係表示繼圖13D後之半導體裝置之製造方法之一例之剖視圖。  圖13F係表示繼圖13E後之半導體裝置之製造方法之一例之剖視圖。  圖13G係表示繼圖13F後之半導體裝置之製造方法之一例之剖視圖。
20:半導體晶片
20a:半導體元件
20b:半導體基板
21:電極柱
70:金屬材料
80:接著膜
B:刀片
C:切口部
DT:切割膠帶
F1:面
F2:面
L:雷射光
LM:改質部
PT:保護膠帶
Rd:切割區域
W:半導體晶圓
Wa:半導體元件
Wb:半導體基板
Wc:龜裂

Claims (7)

  1. 一種半導體裝置之製造方法，其具備如下步驟：於半導體晶圓之第1面設置接著膜，上述半導體晶圓具有上述第1面及位於該第1面之相反側之第2面，且於上述第1面具有半導體元件及與該半導體元件電性連接之凸塊，沿著上述半導體晶圓之分割區域，自上述接著膜側形成切口部，沿著上述切口部，將上述半導體晶圓單片化成半導體晶片，使上述半導體晶片之上述第1面與配線基板對向，使上述凸塊於上述接著膜內連接於上述配線基板，沿著上述分割區域，自上述接著膜側形成較上述半導體元件深且較上述半導體晶圓之上述第2面淺之上述切口部，以切斷面具有與上述切口部之剖面不同之形狀或表面狀態之方式將上述半導體晶圓切斷，藉此，沿著上述切口部，將上述半導體晶圓單片化成上述半導體晶片。
  2. 一種半導體裝置之製造方法，其具備如下步驟：於半導體晶圓之第1面設置接著膜，上述半導體晶圓具有上述第1面及位於該第1面之相反側之第2面，且於上述第1面具有半導體元件及與該半導體元件電性連接之凸塊，沿著上述半導體晶圓之分割區域，自上述接著膜側形成切口部，沿著上述切口部，將上述半導體晶圓單片化成半導體晶片，使上述半導體晶片之上述第1面與配線基板對向，使上述凸塊於上述 接著膜內連接於上述配線基板，於上述半導體晶圓設置上述接著膜之前，沿著上述分割區域，自上述半導體晶圓之上述第1面側，形成較上述半導體元件深且較上述半導體晶圓之上述第2面淺之槽。
  3. 一種半導體裝置之製造方法，其具備如下步驟：於半導體晶圓之第1面設置接著膜，上述半導體晶圓具有上述第1面及位於該第1面之相反側之第2面，且於上述第1面具有半導體元件及與該半導體元件電性連接之凸塊，沿著上述半導體晶圓之分割區域，自上述接著膜側形成切口部，沿著上述切口部，將上述半導體晶圓單片化成半導體晶片，使上述半導體晶片之上述第1面與配線基板對向，使上述凸塊於上述接著膜內連接於上述配線基板，於上述半導體晶圓設置上述接著膜之前，自上述半導體晶圓之上述第2面側照射雷射光，藉此，沿著上述分割區域於上述半導體晶圓內形成改質部，以上述改質部為起點將上述半導體晶圓劈開，藉而沿著上述切口部將上述半導體晶圓單片化成上述半導體晶片。
  4. 如請求項2或3之半導體裝置之製造方法，其進而具備如下步驟：沿著上述半導體晶圓之分割區域，自上述接著膜側形成較上述半導體晶圓之上述第1面淺之上述切口部，沿著上述切口部，將上述半導體晶圓單片化成上述半導體晶片，並 且將上述接著膜分割。
  5. 如請求項3之半導體裝置之製造方法，其進而具備如下步驟，即，於形成上述改質部之後且設置上述接著膜之前，對自上述改質部向上述半導體晶圓之上述第1面或上述第2面延伸之裂紋之狀態進行檢查。
  6. 一種半導體裝置，其包括：配線基板；半導體晶片，其具有第1面及位於該第1面之相反側之第2面，於上述第1面具有半導體元件及與該半導體元件電性連接之凸塊，且於上述第1面側經由上述凸塊而與上述配線基板連接；及接著膜，其於上述半導體晶片與上述配線基板之間被覆上述凸塊；且上述半導體晶片具有缺口部，該缺口部設置於位於上述第1面與上述第2面之間之上述半導體晶片之側面、與上述第1面所交叉之角部，上述缺口部之缺口面具有與上述側面不同之形狀或表面狀態。
  7. 一種半導體裝置，其包括：配線基板；半導體晶片，其具有第1面及位於該第1面之相反側之第2面，於上述第1面具有半導體元件及與該半導體元件電性連接之凸塊，且於上述第1面側經由上述凸塊而與上述配線基板連接；及接著膜，其於上述半導體晶片與上述配線基板之間被覆上述凸塊；且上述半導體晶片具有缺口部，該缺口部設置於位於上述第1面與上述 第2面之間之上述半導體晶片之側面、與上述第1面所交叉之角部，上述接著膜與上述缺口部之缺口面接觸。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7301222B1 (en) * 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
US20140242756A1 (en) * 2013-02-24 2014-08-28 Alpha And Omega Semiconductor Incorporated Method for preparing semiconductor devices applied in flip chip technology

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010239005A (ja) 2009-03-31 2010-10-21 Kinki Univ 裏面照射型撮像素子の製造方法、その製造方法により製造された裏面照射型撮像素子及びそれを備えた撮像装置
JP2012069747A (ja) 2010-09-24 2012-04-05 Teramikros Inc 半導体装置およびその製造方法
JP6727948B2 (ja) 2015-07-24 2020-07-22 ソニーセミコンダクタソリューションズ株式会社 撮像素子、製造方法
WO2017077958A1 (ja) 2015-11-04 2017-05-11 リンテック株式会社 半導体装置の製造方法
JP6950907B2 (ja) 2015-11-04 2021-10-13 リンテック株式会社 半導体装置の製造方法
JP6976111B2 (ja) 2017-09-11 2021-12-08 エイブリック株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7301222B1 (en) * 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
US20140242756A1 (en) * 2013-02-24 2014-08-28 Alpha And Omega Semiconductor Incorporated Method for preparing semiconductor devices applied in flip chip technology

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