TWI730117B - 製造半導體封裝的方法 - Google Patents

製造半導體封裝的方法 Download PDF

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TWI730117B
TWI730117B TW106119155A TW106119155A TWI730117B TW I730117 B TWI730117 B TW I730117B TW 106119155 A TW106119155 A TW 106119155A TW 106119155 A TW106119155 A TW 106119155A TW I730117 B TWI730117 B TW I730117B
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pattern
substrate
carrier substrate
package
buffer
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TW201822285A (zh
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金慶煥
姜泰寓
朴炳律
全炯俊
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南韓商三星電子股份有限公司
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Abstract

一種製造半導體封裝的方法包括：在支撐基底上形成初步封裝，所述初步封裝包括連接基底、半導體晶片、以及位於所述連接基底及所述半導體晶片上的模製圖案；在所述模製圖案上形成緩衝圖案；以及在所述緩衝圖案上形成載體基底，所述載體基底包括與所述緩衝圖案接觸的第一部分及與所述模製圖案接觸的第二部分。

Description

製造半導體封裝的方法
本發明的示例性實施例涉及製造半導體封裝的方法，更具體來說，涉及形成及移除載體基底的方法。
半導體封裝可通過將半導體晶片安裝在印刷電路板基底上以及通過例如打線結合或凸塊將半導體晶片電連接到印刷電路板基底來製造。由於隨著電子產業的發展，對功能強、速度較快、且較小的電子元件的需求增大，因而已出現其中將多個半導體晶片堆疊在單個封裝基底上的安裝方法或將封裝彼此堆疊的方法。
根據本發明概念的示例性實施例，一種製造半導體封裝的方法可包括：在支撐基底上形成初步封裝，所述初步封裝包括連接基底、半導體晶片、以及位於所述連接基底及所述半導體晶片上的模製圖案；在所述模製圖案上形成緩衝圖案；以及在所述緩衝圖案及所述模製圖案上形成載體基底，所述載體基底包括與所述緩衝圖案接觸的第一部分及與所述模製圖案接觸的第二部分。
根據本發明概念的示例性實施例，一種製造半導體封裝的方法可包括：提供初步封裝，所述初步封裝包括連接基底、半導體晶片及模製圖案；在所述模製圖案的第一部分上提供緩衝圖案，所述緩衝圖案暴露出所述模製圖案的第二部分的上表面；在所述緩衝圖案及所述模製圖案上提供載體基底，所述載體基底接觸所述模製圖案的所述第二部分的所述上表面；以及移除所述模製圖案的所述第二部分，以將所述載體基底自所述模製圖案分開。
根據本發明概念的示例性實施例，一種製造半導體封裝的方法可包括：在支撐基底上形成封裝，所述封裝包括：連接基底，所述連接基底包括暴露出所述支撐基底的多個開口；分別位於所述多個開口中的各個開口中的多個半導體晶片；以及模製圖案，覆蓋所述支撐基底及所述多個半導體晶片；在所述封裝上形成緩衝圖案，所述緩衝圖案暴露出所述模製圖案；以及在所述緩衝圖案及所述模製圖案上形成載體基底，所述載體基底與所述緩衝圖案的上表面及所述暴露出的模製圖案的上表面接觸。
根據本發明概念的示例性實施例，一種製造半導體封裝的方法可包括：在支撐基底上提供連接基底，其中所述連接基底具有多個開口。可在所述支撐基底上以及所述連接基底的所述多個開口中的每一個開口中配置半導體晶片。可將模製圖案形成為覆蓋每一所述半導體晶片的上表面及所述連接基底的上表面。可在所述模製圖案上將載體基底配置成使得在每一所述半導體晶片的所述上表面及所述連接基底的所述上表面之上延伸。所述載體基底可在每一所述半導體晶片的所述上表面之上的區處與所述模製圖案間隔開，且可在所述連接基底的所述上表面之上的區處黏合到所述模製圖案。在如上所述配置所述載體基底之後，可移除所述支撐基底。
現將參照附圖來更充分地闡述各種示例性實施例，在附圖中示出一些示例性實施例。然而，本文所述的概念可實施為許多替代形式且不應被視為僅限於本文所述示例性實施例。
圖1A、圖2A及圖3A是說明根據示例性實施例的製造半導體封裝的方法的俯視圖。圖1B至圖1E、圖2B至圖2E、圖3B及圖4是說明根據示例性實施例的製造半導體封裝的方法的剖視圖。圖1B至圖1E是沿圖1A中的線I-I'截取的剖視圖。圖2B至圖2E是沿圖2A中的線I-I'截取的剖視圖。圖3B是沿圖3A中的線I-I'截取的剖視圖。
參照圖1A及圖1B，可在支撐基底100上形成初步封裝P。初步封裝P可以面板級別形成。初步封裝P可包括連接基底200、第一半導體晶片300及模製圖案400。當在俯視圖中觀察時，初步封裝P可包括多個第一區R1及第二區R2。初步封裝P的第一區R1可設置在初步封裝P的中心區中。初步封裝P的第二區R2可設置在初步封裝P的邊緣區中且可環繞第一區R1。
連接基底200可設置在支撐基底100上。連接基底200可通過黏合層110貼合在支撐基底100上。作為實例，連接基底200可包括印刷電路板（printed circuit board，PCB）基底。連接基底200可包括基底層210及導電構件220。基底層210可包含非導電材料。在實施例中，基底層210可包含矽酮系材料、聚合物等或其任意組合。可在基底層210中設置導電構件220。導電構件220可包括第一墊221、配線圖案222、通路223及第二墊224。第一墊221可設置在連接基底200的下表面200b上。通路223可穿透基底層210。配線圖案222可設置在基底層210之間且可直接連接至通路223。第二墊224可設置在連接基底200的上表面200a上且可連接至通路223中的至少一個。第二墊224可不在第三方向D3上與第一墊221對準。第三方向D3可為與連接基底200的下表面200b垂直的方向。第一方向D1及第二方向D2可平行於連接基底200的下表面200b。第一方向D1可正交於第二方向D2。
導電構件220可包含例如銅、鋁、鎳等金屬、或其合金。可在連接基底200中形成開口250。開口250可暴露出支撐基底100。
第一半導體晶片300可設置在支撐基底100上。第一半導體晶片300可分別設置在初步封裝P的第一區R1中。第一半導體晶片300可分別設置在連接基底200的開口250中。連接基底200可環繞各自的第一半導體晶片300。可在半導體晶片300中的每一個的下表面300b上設置晶片墊350。
模製圖案400可形成在連接基底200的上表面200a上及第一半導體晶片300的上表面300a上。模製圖案400可在連接基底200與第一半導體晶片300之間的空隙中延伸或填充連接基底200與第一半導體晶片300之間的空隙。模製圖案400可包含軟材料，例如絕緣聚合物。模製圖案400可利用例如聚合物片材形成。在一些實施例中，模製圖案400可包括增層膜或層疊的多個層（laminated multiple layer）。
模製圖案400可包括第一部分410及第二部分420。當在俯視圖中觀察時，模製圖案400的第一部分410可設置在初步封裝P的中心區上且可與所述多個第一區R1重疊。當在俯視圖中觀察時，模製圖案400的第二部分420可與第二區R2重疊。模製圖案400的第二部分420可連接到模製圖案400的第一部分410。
參照圖1A及圖1C，可在初步封裝P的第一區R1上設置緩衝圖案500。緩衝圖案500可覆蓋模製圖案400的第一部分410且可暴露出模製圖案400的第二部分420。緩衝圖案500可包含非黏性材料（即，以下論述的不黏合至（或不顯著地黏合至）模製圖案400的材料（或載體基底600的材料）的材料）。緩衝圖案500可在不貼合至模製圖案400的條件下設置在模製圖案400上。緩衝圖案500的下表面可不結合至模製圖案400的上表面。緩衝圖案500可不通過沉積製程形成。作為實例，緩衝圖案500可包含特氟龍（Teflon）片材。
參照圖1A及圖1D，可在緩衝圖案500上設置載體基底600。在形成載體基底600的過程中，可對緩衝圖案500及模製圖案400的第一部分410施加壓力。由於模製圖案400是軟的，因此模製圖案400的第一部分410可通過所施加的壓力被壓縮。模製圖案400的第二部分420的上表面420a可與緩衝圖案500的上表面500a至少實質上共面。載體基底600可與緩衝圖案500的上表面500a以及模製圖案400的第二部分420的上表面420a接觸。載體基底600可包括第一部分及第二部分。載體基底600的第一部分可與緩衝圖案500實體接觸，但緩衝圖案500可不貼合至載體基底600。而是，載體基底600的第二部分可與模製圖案400的第二部分420接觸並貼合至模製圖案400的第二部分420。因此，載體基底600可通過模製圖案400的第二部分420貼合至初步封裝P。由於模製圖案400的第二部分420設置在初步封裝P的邊緣區內，載體基底600可穩定地固定至初步封裝P。在一些實施例中，在設置載體基底600之前，可不將模製圖案400固化，且可在設置載體基底600之後將模製圖案400固化。
可移除支撐基底100及黏合層110（例如，由虛線所表示）以暴露出初步封裝P的下表面（例如，第一半導體晶片300的下表面300b及連接基底200的下表面200b）。
參照圖1A及圖1E，可在初步封裝P的下表面上（例如，在第一半導體晶片300的下表面300b及連接基底200的下表面200b上）形成絕緣圖案710、重佈線圖案720、及保護層715，以由此形成第一基底700（在本文中也被稱為“重佈線基底”）。重佈線圖案720可包括位於各絕緣圖案710之間的導電圖案721以及穿透絕緣圖案710的導電通路722。重佈線圖案720可包含銅、鋁、等或其任意組合。重佈線圖案720可連接至第一半導體晶片300的晶片墊350及連接基底200的第一墊221。保護層715可形成在絕緣圖案710的下表面上。保護層715可包含絕緣材料。舉例來說，保護層715可包含與模製圖案400相同的材料。然而，應認識到，保護層715是可選的且可被省略。由於第一基底700被用作重佈線基底，因此與連接基底200相比，第一基底700可具有薄的厚度。
可在第一基底700的下表面上形成外部端子730。外部端子730可連接到重佈線圖案720。外部端子730可包含金屬。外部端子730可包含焊料球。外部端子730可通過重佈線圖案720及導電構件220電連接到第二墊224。外部端子730可不在第三方向D3上與第二墊224對準。外部端子730的數目可不同於第二墊224的數目。第二墊224的配置自由度可通過導電構件220及重佈線圖案720而得到提高。
參照圖2A及圖2B，可執行載體基底600的第一移除製程。載體基底600的第一移除製程可包括對初步封裝P及載體基底600執行鋸切製程（例如，將初步封裝P的第二區R2從初步封裝P的第一區R1分離）。舉例來說，可在初步封裝P的第二區R2處（在模製圖案400的第二部分420處）執行鋸切製程以將第二區R2從初步封裝P的第一區R1分離，從而將第二區R2從初步封裝P移除。此時，位於模製圖案400的第二部分420上的載體基底600也可從初步封裝P的第一區R1分離。在下文中，在示例性實施例中，在載體基底600的第一移除製程之後剩餘的模製圖案400的部分可包括模製圖案400的第一部分410。在鋸切製程之後，載體基底600可從模製圖案400分離。由於載體基底600不黏合到緩衝圖案500，因此可容易地將載體基底600從初步封裝P分開。
參照圖2A及圖2C，可執行載體基底600的第二移除製程以將載體基底600從緩衝圖案500分開。作為實例，載體基底600可被固定到移除設備1000的真空抽吸頭1100，且因此可將載體基底600從緩衝圖案500分開。根據示例性實施例，由於緩衝圖案500包含非黏性材料，因此,可在無需施加過大壓力（緩衝圖案500由黏性材料形成時所需要的壓力）便可將載體基底600從緩衝圖案500分離。由於在載體基底600的移除製程中未對初步封裝P施加過大壓力，因此可減少或完全防止對初步封裝P及第一基底700造成的損壞。
參照圖2A及圖2D，可將緩衝圖案500從模製圖案400分開。作為實例，緩衝圖案500可被固定到移除設備1000的真空抽吸頭1100，且因此可容易地將緩衝圖案500從模製圖案400分開。可使用與在圖2C中的載體基底600的第二移除製程中使用的移除設備1000不同或相同的移除設備來執行緩衝圖案500的移除。如果緩衝圖案500黏合到模製圖案400，則模製圖案400的上表面可在緩衝圖案500的移除製程中被損壞。舉例來說，在模製圖案400的上表面上可能會產生裂紋。在這種情形中，模製圖案400的上表面可具有例如大於5 μm的高的中心線平均表面粗糙度（central-line average surface roughness）Ra。可進一步執行緩衝圖案500的額外的移除製程（例如，蝕刻製程）。然而，根據示例性實施例，緩衝圖案500未黏合到模製圖案400，且因此模製圖案400可不在緩衝圖案500的移除製程中被損壞。因此，在載體基底600的第二移除製程之後，模製圖案400的上表面可具有0.1 μm至3 μm的中心線平均表面粗糙度Ra。在緩衝圖案500的移除製程中，第一基底700、連接基底200、第一半導體晶片300及模製圖案400可不受到損壞。因此，所製造的半導體封裝可具有提高的可靠性。可省略緩衝圖案500的額外的移除製程，且因此可簡化緩衝圖案500的移除製程。
參照圖2A及圖2E，在移除緩衝圖案500之後，可在模製圖案400中形成凹槽401以暴露出第二墊224。
參照圖3A及圖3B，可將圖2A及圖2B的初步封裝P單體化，且因此，初步封裝P的第一區R1可彼此分離。初步封裝P的單體化可通過對第一基底700、連接基底200及模製圖案400進行鋸切來執行。初步封裝P的經分離的第一區R1可分別形成第一封裝P1。第一封裝P1可分別包括第一基底700、第一半導體晶片300中的每一個及模製圖案400。在一些實施例中，初步封裝P的單體化可通過單個製程來執行（例如，與圖2B所闡述的載體基底600的第一移除製程一起）。在這種情形中，載體基底600及緩衝圖案500可餘留在第一封裝P1中的每一個上，且可對每一個第一封裝P1執行載體基底600的第二移除製程及緩衝圖案500的移除製程。
參照圖4，可在圖3B所示的第一封裝P1上安裝第二封裝P2以製造半導體封裝。第二封裝P2可包括第二基底800、第二半導體晶片810、及第二模製圖案820。第二半導體晶片810可通過倒裝晶片方法（flip chip method）安裝在第二基底800上。在一些實施例中，第二半導體晶片810可通過打線接合來電連接到第二基底800。模製圖案820可形成在第二基底800上以覆蓋第二半導體晶片810。
可在第一封裝P1與第二封裝P2之間形成連接端子900（例如，焊料凸塊）。連接端子900可連接到第二基底800及第二墊224。第二封裝P2可通過連接端子900電連接到第一封裝P1。圖5A及圖5B是說明根據示例性實施例的載體基底的移除製程的剖視圖。在下文中，可不再對與上述重複的說明予以贅述。
參照圖5A，可提供初步封裝P。初步封裝P可包括連接基底200、多個第一半導體晶片300、模製圖案400、緩衝圖案500及載體基底600。連接基底200、所述多個第一半導體晶片300、模製圖案400、緩衝圖案500及載體基底600的形成可與在圖1B至圖1E所闡述的相同。
之後，可執行載體基底600的第一移除製程。舉例來說，載體基底600的第一移除製程可通過將化學物質塗在模製圖案400的側壁上來執行。所述化學物質可與模製圖案400反應，且因此可移除模製圖案400的第二部分420（由虛線所包圍的區表示）。之後，載體基底600可從模製圖案400分離且可從初步封裝P分開。
參照圖5B，可執行載體基底600的第二移除製程。載體基底600的第二移除製程可通過與圖2C所述的製程相同的製程來執行。舉例來說，可使用移除設備1000來將載體基底600從模製圖案400分開。在載體基底600的第二移除製程之後，可通過與圖2D至圖3B所闡述的製程實質上相同的製程來製造第一封裝P1。然而，在圖3A及圖3B所述的單體化製程期間可移除初步封裝P的第二區R2。
圖5C是說明根據示例性實施例的載體基底的第一移除製程的剖視圖。在下文中，不再對與上述重複的說明予以贅述。
參照圖5C，可如以上針對圖5A所述來對初步封裝P進行處理。也就是說，可執行載體基底600的第一移除製程。載體基底600的第一移除製程可通過將化學物質塗在模製圖案400的側壁上來執行。之後，可對初步封裝P及載體基底600執行鋸切製程。初步封裝P的第二區R2可通過鋸切製程來與初步封裝P的第一區R1分離。此時，可如上所論述移除載體基底600的一部分及緩衝圖案500。
圖6A、圖7A及圖8A是說明根據示例性實施例的製造半導體封裝的方法的俯視圖。圖6B、圖7B及圖8B分別是沿圖6A、圖7A及圖8A中的線I-I'截取的剖視圖。在下文中，不再對與上述重複的說明予以贅述。圖6C是說明根據示例性實施例的初步封裝的剖視圖。在下文中，不再對與上述重複的說明予以贅述。
參照圖6A及圖6B，可製備初步封裝P。初步封裝P可通過與圖1A及圖1B所述製程實質上相同的製程來形成。然而，如示例性地所示，初步封裝P可包括第一區R1、第二區R2及虛設區DR。虛設區DR可設置在各第一區R1之間。作為實例，當在俯視圖中觀察時，初步封裝P的虛設區DR可在第二方向D2上延伸。在其他實施例中，初步封裝P的虛設區DR可包括在第一方向D1上延伸的第一部分及在第二方向D2上延伸的第二部分，如圖6C所示。然而，應認識到，虛設區DR的佈局（當在俯視圖中觀察時）可根據需要或以其他適合的方式加以改變。
可在初步封裝P上設置緩衝圖案500及載體基底600。可在第一半導體晶片300的下表面300b及連接基底200的下表面200b上形成第一基底700。
可在虛設區DR中的第一基底700的下表面上形成測試墊740。測試墊740可電連接到重佈線圖案720。可在虛設區DR中的連接基底200中設置測試電路。所述測試電路可電連接到測試墊740。
可對第一基底700的電連接進行測試。舉例來說，可將探針與測試墊740接觸來測試重佈線圖案720的電連接。重佈線圖案720的電連接的測試可包括電短路或斷線（disconnection）測試。
參照圖7A及圖7B，可移除載體基底600及緩衝圖案500。可通過與上述製程實質上相同的製程來執行載體基底600的移除製程。舉例來說，在載體基底600的第一移除製程中，可對初步封裝P及載體基底600進行鋸切以將初步封裝P的第二區R2、以及與第二區R2對應的載體基底600的第二部分從初步封裝P的第一區R1分離，從而將第二區R2從初步封裝P移除。再舉例來說，可通過圖5A中所闡述的化學蝕刻製程來移除模製圖案400的第二部分420。在載體基底600的第一移除製程之後，載體基底600可從初步封裝P分開。接下來，可將載體基底600及緩衝圖案500從初步封裝P移除。
參照圖8A及圖8B，可將初步封裝P單體化以使初步封裝P的各第一區R1彼此分離。因此，初步封裝P的經分離的第一區R1可分別形成第一封裝P1。初步封裝P的虛設區DR可從初步封裝的第一區R1分離。因此，可移除初步封裝P的虛設區DR。可在模製圖案400中形成凹槽401以暴露出第二墊224。凹槽401可在初步封裝P的單體化之前或之後形成。
圖9A及圖9C是說明根據示例性實施例的製造半導體封裝的方法的剖視圖。圖9A是沿圖6A所示線I-I'截取的剖視圖。圖9B是說明圖9A中的區II的放大圖。圖9C是沿圖8A所示線I-I'截取的剖視圖。在下文中，不再對與上述重複的說明予以贅述。
參照圖6A、圖9A、及圖9B，可在虛設區DR中的第一基底700中形成對準鍵750。對準鍵750可形成於第一基底700的絕緣圖案710中。可通過蝕刻絕緣圖案710以形成通路孔725以及利用導電材料填充通路孔來形成重佈線圖案720的導電通路722。可在絕緣圖案710中的每一個上形成導電層且可對所述導電層進行蝕刻以形成導電圖案721。可利用對準鍵750來執行用於形成通路孔725及導電圖案721的蝕刻製程，且因此，可確認光掩模是否對準。
在形成第一基底700之後，可移除載體基底600及緩衝圖案500。可對初步封裝P及載體基底600進行鋸切以將初步封裝P的第二區R2及載體基底600從初步封裝P的第一區R1分離，從而將初步封裝P的第二區R2及載體基底600從初步封裝P分離。
參照圖8A及圖9C，可將初步封裝P單體化以製造第一封裝P1。此時，初步封裝P的各第一區R1可分別形成第一封裝P1，且可移除初步封裝P的虛設區DR。
圖10A及圖11A是說明根據示例性實施例的製造半導體封裝的方法的俯視圖。圖10B及圖11B分別是沿圖10A及圖11A中的線I-I'截取的剖視圖。在下文中，不再對與上述重複的說明予以贅述。
參照圖10A及圖10B，初步封裝P的第二區R2可在俯視圖中觀察時與初步封裝P的邊緣區重疊，且可在初步封裝P的各第一區R1之間延伸。初步封裝P的第二區R2可沿第二方向D2與初步封裝P的中心區交叉。可在初步封裝P上設置多個緩衝圖案500。緩衝圖案500可與初步封裝P的第一區R1重疊。緩衝圖案500可不設置在初步封裝P的第二區R2上。在俯視圖中，緩衝圖案500可在第一方向D1上彼此間隔開。模製圖案400的第二部分420可通過緩衝圖案500暴露出。載體基底600可通過模製圖案400的第二部分420來貼合到初步封裝P。
參照圖11A及圖11B，可通過對載體基底600及初步封裝P進行鋸切來執行載體基底600的第一移除製程。初步封裝P的第二區R2以及位於初步封裝P的第二區R2上的載體基底600可如上所論述被移除。在一些實施例中，載體基底600的第一移除製程可進一步包括在執行載體基底600及初步封裝P的鋸切製程之前利用化學蝕刻製程（例如，如上所述）來對初步封裝P的側壁進行處理。之後可通過與圖2C至圖4中所闡述的製程實質上相同的製程來製造半導體封裝。
圖12A及圖12B是說明根據示例性實施例的初步封裝的俯視圖。在下文中，不再對與上述重複的說明予以贅述。
參照圖12A及圖12B，可在初步封裝P的各第一區R1之間進一步提供初步封裝P的第二區R2。可在初步封裝P上設置多個緩衝圖案500。當在俯視圖中觀察時，緩衝圖案500可在第二方向D2上彼此間隔開。在一些實施例中，如圖12A所示，初步封裝P的第二區R2可在第一方向D1上與初步封裝P的中心區交叉。在一些實施例中，如圖12B所示，初步封裝P的第二區R2在第一方向D1及第二方向D2兩個方向上均與初步封裝P的中心區交叉。不論初步封裝P的第二區R2與初步封裝P的中心區在哪一個（或哪一些）方向上交叉，載體基底600的第一移除製程均可通過與圖11A及圖11B闡述的製程實質上相同的製程來執行。
圖13是說明根據示例性實施例的載體基底的剖視圖。在下文中，不再對與上述重複的說明予以贅述。
參照圖13，載體基底600可包括依序堆疊的第一層610、第二層620、及第三層630。舉例來說，第一層610及第三層630可包含例如銅等金屬。第二層620可包含例如玻璃纖維等無機材料。
再次參照圖1C，可使用圖13中所闡述的載體基底600。在這種情形中，第一層610可被設置成面朝初步封裝P且可貼合到緩衝圖案500。然而，載體基底600可有所變化，而並非僅限於此。
儘管已參照本發明概念的示例性實施例具體顯示並闡述了本發明概念，然而所屬領域中的普通技術人員應理解，在不背離由以上權利要求界定的本發明的精神及範圍的條件下可在本文中作出形式及細節上的各種改變。
100‧‧‧支撐基底110‧‧‧黏合層200‧‧‧連接基底200a、300a、420a、500a‧‧‧上表面200b、300b‧‧‧下表面210‧‧‧基底層220‧‧‧導電構件221‧‧‧第一墊222‧‧‧配線圖案223‧‧‧通路224‧‧‧第二墊250‧‧‧開口300‧‧‧第一半導體晶片/半導體晶片350‧‧‧晶片墊400‧‧‧模製圖案401‧‧‧凹槽410‧‧‧第一部分420‧‧‧第二部分500‧‧‧緩衝圖案600‧‧‧載體基底610‧‧‧第一層620‧‧‧第二層630‧‧‧第三層700‧‧‧第一基底710‧‧‧絕緣圖案715‧‧‧保護層720‧‧‧重佈線圖案721‧‧‧導電圖案722‧‧‧導電通路725‧‧‧通路孔730‧‧‧外部端子740‧‧‧測試墊750‧‧‧對準鍵800‧‧‧第二基底810‧‧‧第二半導體晶片820‧‧‧第二模製圖案/模製圖案900‧‧‧連接端子1000‧‧‧移除設備1100‧‧‧真空抽吸頭D1‧‧‧第一方向D2‧‧‧第二方向D3‧‧‧第三方向DR‧‧‧虛設區I-I'‧‧‧線II‧‧‧區P‧‧‧初步封裝P1‧‧‧第一封裝P2‧‧‧第二封裝R1‧‧‧第一區R2‧‧‧第二區
圖1A、圖2A及圖3A是說明根據示例性實施例的製造半導體封裝的方法的俯視圖。 圖1B至圖1E、圖2B至圖2E、圖3B及圖4是說明根據示例性實施例的製造半導體封裝的方法的剖視圖。 圖5A及圖5B是說明根據示例性實施例的移除載體基底的製程的剖視圖。 圖5C是說明根據示例性實施例的移除載體基底的第一移除製程的剖視圖。 圖6A、圖7A及圖8A是說明根據示例性實施例的製造半導體封裝的方法的俯視圖。 圖6B是沿圖6A中的線I-I'截取的剖視圖。 圖6C是說明根據示例性實施例的初步封裝的剖視圖。 圖7B及圖8B分別是沿圖7A及圖8A中的線I-I'截取的剖視圖。 圖9A及圖9C是說明根據示例性實施例的製造半導體封裝的方法的剖視圖。 圖9B是說明圖9A中的區II的放大圖。 圖10A及圖11A是說明根據示例性實施例的製造半導體封裝的方法的俯視圖。 圖10B及圖11B分別是沿圖10A及圖11A中的線I-I'截取的剖視圖。 圖12A及圖12B是說明根據示例性實施例的初步封裝的俯視圖。 圖13是說明根據示例性實施例的載體基底的剖視圖。
100‧‧‧支撐基底
110‧‧‧黏合層
200‧‧‧連接基底
200a‧‧‧上表面
200b‧‧‧下表面
210‧‧‧基底層
220‧‧‧導電構件
221‧‧‧第一墊
222‧‧‧配線圖案
223‧‧‧通路
224‧‧‧第二墊
250‧‧‧開口
300‧‧‧第一半導體晶片/半導體晶片
300a‧‧‧上表面
300b‧‧‧下表面
350‧‧‧晶片墊
400‧‧‧模製圖案
410‧‧‧第一部分
420‧‧‧第二部分
D1‧‧‧第一方向
D3‧‧‧第三方向
P‧‧‧初步封裝
R1‧‧‧第一區
R2‧‧‧第二區

Claims (25)

  1. 一種製造半導體封裝的方法，其特徵在於，所述方法包括：在支撐基底上形成初步封裝，所述初步封裝包括連接基底、半導體晶片、以及位於所述連接基底及所述半導體晶片上的模製圖案；在所述模製圖案上形成緩衝圖案；以及在所述緩衝圖案及所述模製圖案上形成載體基底，所述載體基底包括與所述緩衝圖案接觸的第一部分及與所述模製圖案接觸的第二部分。
  2. 如申請專利範圍第1項所述的方法，其特徵在於，所述緩衝圖案包括非黏性材料。
  3. 如申請專利範圍第1項所述的方法，其特徵在於，進一步包括移除所述載體基底，其中移除所述載體基底包括：第一移除製程，通過對所述載體基底執行鋸切製程來移除所述載體基底的所述第二部分；以及第二移除製程，將所述載體基底從所述緩衝圖案分離。
  4. 如申請專利範圍第3項所述的方法，其特徵在於，進一步包括：移除所述支撐基底，以暴露出所述初步封裝的下表面；以及在所述初步封裝的所述下表面上形成重佈線基底，其中移除所述載體基底是在形成所述重佈線基底之後執行。
  5. 如申請專利範圍第4項所述的方法，其特徵在於，所述重佈線基底包括絕緣圖案及重佈線圖案。
  6. 如申請專利範圍第5項所述的方法，其特徵在於，所述重佈線圖案電連接到所述半導體晶片及所述連接基底。
  7. 如申請專利範圍第1項所述的方法，其特徵在於，在俯視圖中，所述載體基底的所述第二部分與所述初步封裝的邊緣區重疊。
  8. 一種製造半導體封裝的方法，其特徵在於，所述方法包括：提供初步封裝，所述初步封裝包括連接基底、半導體晶片及模製圖案；在所述模製圖案的第一部分上提供緩衝圖案，所述緩衝圖案暴露出所述模製圖案的第二部分的上表面；在所述緩衝圖案及所述模製圖案上提供載體基底，所述載體基底接觸所述模製圖案的所述第二部分的所述上表面；以及移除所述模製圖案的所述第二部分，以將所述載體基底自所述模製圖案分開。
  9. 如申請專利範圍第8項所述的方法，其特徵在於，所述載體基底通過所述模製圖案的所述第二部分貼合到所述初步封裝。
  10. 如申請專利範圍第8項所述的方法，其特徵在於，進一步包括：在將所述載體基底分開之後，從所述初步封裝移除所述載體基底。
  11. 如申請專利範圍第10項所述的方法，其特徵在於，進一步包括：在移除所述載體基底之後，將上部封裝設置在所述模製圖案上， 其中所述連接基底包括基礎層及位於所述基礎層中的導電構件，且其中所述上部封裝電連接到所述導電構件。
  12. 如申請專利範圍第8項所述的方法，其特徵在於，所述模製圖案的所述第二部分設置在所述初步封裝的邊緣區中。
  13. 如申請專利範圍第8項所述的方法，其特徵在於，移除所述模製圖案的所述第二部分包括鋸切所述載體基底及所述初步封裝，以使所述模製圖案的所述第二部分從所述模製圖案的所述第一部分分離。
  14. 如申請專利範圍第8項所述的方法，其特徵在於，移除所述模製圖案的所述第二部分包括對所述初步封裝的側壁進行化學蝕刻。
  15. 如申請專利範圍第8項所述的方法，其特徵在於，在提供所述載體基底之後，所述模製圖案的所述第二部分的所述上表面與所述緩衝圖案的上表面實質上共面。
  16. 一種製造半導體封裝的方法，其特徵在於，所述方法包括：在支撐基底上形成封裝，所述封裝包括：連接基底，所述連接基底包括暴露出所述支撐基底的多個開口；分別位於所述多個開口中的多個半導體晶片；以及模製圖案，覆蓋所述支撐基底及所述多個半導體晶片；在所述封裝上形成緩衝圖案，所述緩衝圖案暴露出所述模製圖案；以及 在所述緩衝圖案及所述模製圖案上形成載體基底，所述載體基底與所述緩衝圖案的上表面及暴露出的所述模製圖案的上表面接觸。
  17. 如申請專利範圍第16項所述的方法，其特徵在於，所述緩衝圖案包括非黏性材料。
  18. 如申請專利範圍第16項所述的方法，其特徵在於，所述緩衝圖案包括彼此間隔開的多個緩衝圖案，且其中所述模製圖案存在於所述多個緩衝圖案之間的間隙中。
  19. 如申請專利範圍第16項所述的方法，其特徵在於，進一步包括在所述封裝的下表面上形成基底，其中所述基底包括多個第一區、及位於所述多個第一區之間的虛設區，在俯視圖中，所述第一區分別與所述多個半導體晶片重疊，且其中在所述基底的所述虛設區中形成有測試墊及/或對準鍵。
  20. 如申請專利範圍第16項所述的方法，其特徵在於，所述載體基底接觸所述封裝的邊緣區中的所述模製圖案。
  21. 一種製造半導體封裝的方法，其特徵在於，所述方法包括：在支撐基底上提供連接基底，所述連接基底具有多個開口；在所述支撐基底上、所述連接基底的所述多個開口中的每一個開口中配置半導體晶片；形成模製圖案，所述模製圖案覆蓋每一所述半導體晶片的上表面及所述連接基底的上表面； 在所述模製圖案上配置載體基底，其中所述載體基底在每一所述半導體晶片的所述上表面及所述連接基底的所述上表面之上延伸，其中所述載體基底在每一所述半導體晶片的所述上表面之上與所述模製圖案間隔開，且其中所述載體基底在所述連接基底的所述上表面之上黏合到所述模製圖案；以及在配置所述載體基底之後，移除所述支撐基底。
  22. 如申請專利範圍第21項所述的方法，其特徵在於，形成所述模製圖案包括將所述模製圖案的上表面成形為具有在所述半導體晶片中的每一所述半導體晶片的所述上表面之上延伸的至少一個凹槽。
  23. 如申請專利範圍第22項所述的方法，其特徵在於，將所述模製圖案的所述上表面成形包括：在所述模製圖案上配置緩衝圖案；以及將所述緩衝圖案按壓到所述模製圖案中。
  24. 如申請專利範圍第23項所述的方法，其特徵在於，將所述緩衝圖案按壓到所述模製圖案中包括：使所述載體基底接觸所述緩衝圖案；以及按壓所述載體基底以抵壓所述緩衝圖案。
  25. 如申請專利範圍第24項所述的方法，其特徵在於，所述緩衝圖案與所述載體基底之間的黏著性小於所述模製圖案與所述載體基底之間的黏著性。
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